Ex Parte 6591353 et al

Board of Patent Appeals and Interferences

Jan 24, 2012

95001169 (B.P.A.I. Jan. 24, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,169 04/21/2009 6591353 2805.003REX9 7283 22852 7590 01/24/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 01/24/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Inter Partes NVIDIA, CORP. Requestor, Appellant & Respondent v. RAMBUS, INC. Patent Owner, Respondent & Cross-Appellant _____ Appeal 2011-010623 Reexamination Control No. 95/001,169 United States Patent 6,591,353 B1 Technology Center 3900 ____________ Before ALLEN R. MacDONALD, KARL D. EASTHOM, and STEPHEN C. SIU, Administrative Patent Judges. EASTHOM, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 This proceeding arose from NVDIA’s request for an inter partes reexamination of the Rambus’s patent, U.S. 6,591,353 B1 to Barth et al., Protocol For Communication with Dynamic Memory (July 8, 22, 2003). Third-party Requestor NVIDIA appeals under 35 U.S.C. §§ 134(b) and 306 from the Examiner’s Right of Appeal Notice (RAN) confirming claims 2-4, 6, 8-10, 12, 13, 15-18, 20-22 and 24-26 of the ‘353 patent under reexamination. (See Req. App. Br. 3, 5 (appealing claims 1-26).) Patent Owner Rambus cross-appeals from the Examiner’s RAN finally rejecting claims 1, 5, 7, 11, 14, 19 and 23. (P.O. Cr. App. Br. 5.) Requestor NVIDIA and Patent Owner Rambus also filed Respondent Briefs (Req. Resp. Br.; P.O. Resp. Br.) and Rebuttal Briefs (Req. Reb. Br.; P.O. Reb. Br.) We have jurisdiction under 35 U.S.C. 35 U.S.C. §§ 6, 134, and 315. We AFFIRM-IN-PART, affirming the Examiner’s decision to maintain the rejection of claims 1, 5, 7, 11, 14, 19, and 23 cross-appealed by Rambus, and reversing the Examiner’s decision not to reject claims 1-26 appealed by NVIDIA. We decline to reach some of the proposed rejections. STATEMENT OF THE CASE Rambus refers to several related judicial and other proceedings including inter partes and ex parte reexaminations, International Trade Commission proceedings, and Federal District Court and Circuit Court proceedings in their briefs. (P.O. Cr. App. Br. 4.) An oral hearing of this appeal transpired at the BPAI on October 19, 2011 and was transcribed. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 3 The ‘353 Patent (Factual Findings) P1. The ‘353 patent states that the “present invention relates to dynamic random access memory (DRAM), and more specifically to a method and apparatus for controlling data transfers to and from a dynamic random access memory.” (Col. 1, ll. 11-14.) More generally, “[t]he present invention provides a method and apparatus for performing data transfers within a computer system.” (Col. 3, ll. 63-64.) “A memory device reads . . . control information on the bus.” (Col. 4, ll. 6-7.) P2. The ‘353 patent describes a related prior art system at Figure 4 which sends data in packets to memory: “The request packet format . . . communicate[s] between master devices, such as processors, and slave devices, such as memories.” (Col. 2, ll. 49-52.) Figures 2 and 4 are reproduced below: Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 4 Both figures depicted above show a DRAM device connected to a bus via a “bus interface of the DRAM receiver” (col. 2, l. 65). (The depicted interface “R/T” in Figure 4 implies a receiver/transmitter - see infra P4.) The ‘353 patent also refers to communication between “slave devices coupled to the bus” connected to the bus lines. (Col. 2, ll. 53-59.) P3. The ‘353 patent disclaims any implied claim limitations based on disclosed embodiments: In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 5 drawings are accordingly, to be regarded in an illustrative rather than a restrictive sense. (Col. 24, ll. 3-9.) P4. In addition to memory arrays, the memory devices in the ‘353 patent comprise control logic 1910, a receiver 620, a transmitter 616, and a clock generator 618. (See Fig. 6, col. 5, l.61 to col. 6, l. 20.) Definitions D. A “device” is defined as “[a] circuit or logical group of circuits resident on one or more boards capable of interacting with other such devices through the bus.” IEEE Standard Dictionary of Electrical and Electronics Terms 257 (1988). (Req. Resp. Br. 5 (citing Ex. 7).) E. A “DRAM” definition follows: A volatile store in which the fundamental storage devices are capacitors arranged in matrix formation. Associated with each capacitor are field-effect transistors which act as switches when data is put into the store or withdrawn from it. To prevent loss of data as the capacitors discharge through the inevitable leakage paths, their charges are regularly ‘topped up’ - a process known as refreshing. Despite the need for refreshing the dynamic RAM is simpler, more compact and cheaper than a static RAM and, although its speed is lower, is more widely used. Newnes Dictionary of Electronics, Newnes (1999) at http://www.credoreference.com/entry/bhelec/dynamic_random_access_mem ory_dram (last visited Oct. 20, 2011) (emphasis added). The Claims Exemplary claims of the ‘353 patent under reexamination follow: 1. A method of operation in a memory device that includes a plurality of memory cells, the method comprising: receiving a command to sample data; Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 6 deferring sampling a first portion of the data until an external strobe signal is detected; and sampling the first portion of the data from an external signal line in response to detecting the external strobe signal. 2. The method of claim 1, wherein the first portion of the data is sampled synchronously with respect to an external clock signal. 5. The method of claim 1, further comprising: detecting an external terminate signal; and sampling additional portions of the data during a time interval between detection of the external strobe signal and detection of the external terminate signal. 11. A method of controlling a memory device that includes a plurality of memory cells, the method comprising: issuing a first write command to the memory device, the memory device being configured to defer sampling data that corresponds to the first write command until a strobe signal is detected; delaying for a first time period after issuing the write command; and after delaying for the first time period, issuing the strobe signal to the memory device to initiate sampling of a first portion of the data by the memory device. 19. A memory device having a plurality of memory cells, the memory device comprising: a plurality of input receiver circuits to receive a write command and sample data that corresponds to the write command in response to detecting a strobe signal that is delayed relative to the write command by a first time period. PRINCIPLES OF LAW In reexaminations of non-expired patents, claims are given the “broadest reasonable construction consistent with the specification.” See In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Circ. 1984) (not addressing expired patents). In all cases, “the words of a claim ‘are generally given Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 7 their ordinary and customary meaning’” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc) (internal citations omitted), with the caveat that claims “must be read in view of the specification. . . . [T]he specification ‘is always highly relevant to the claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of a disputed term.’” Id. at 1315 (Fed. Cir. 2005) (en banc) (citation omitted). “Even when the specification describes only a single embodiment, the claims of the patent will not be read restrictively unless the patentee has demonstrated a clear intention to limit the claim scope using ‘words or expressions of manifest exclusion or restriction’.” Leibel-Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004) (citation omitted). “We have cautioned against reading limitations into a claim from the preferred embodiment described in the specification, even it is the only embodiment described, absent clear disclaimer in the specification.” In re Am. Acad. Of Science Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). RAMBUS’s CROSS APPEAL Rejection on Cross-Appeal Claims 1, 5, 7, 11, 14, 19, and 23 as anticipated under 35 U.S.C. § 102(b) based Hayes et al., U.S. Patent 5,218,684 (June 8, 1993) (“Hayes”). Issues Patent owner Rambus contends that Hayes does not disclose sending a strobe signal or a terminate signal to a memory device, which according to Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 8 Rambus, must be a single chip (see e.g., P.O. Cr. App. Br. 11, 16, 28-30), thereby raising the following issues: Did Rambus demonstrate the Examiner erred in finding that Hayes anticipates claims 1, 11, and 23 which recite a strobe signal and a memory device? Did Rambus demonstrate the Examiner erred in finding that Hayes anticipates claims 5, 14, and 24 which require sampling additional data portions between a strobe and terminate signal? Hayes -Factual Findings H1. Figure 2 from Hayes is depicted below: Figure 2 shows the slave (i.e., a memory board - see infra H5) controlled, inter alia, by a write signal and a data strobe (DS) signal (see infra H2) from the bus master via local data and address lines <31:0>. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 9 The bus master depicted refers to either the processor 10 or chip 16. (See Fig. 1 and col. 14, ll. 16-20.) H2. In reference to Figure 2 supra, a general description of the master (bus controller) and slave (memory) communication follows: For a write cycle, “[t]he bus master . . . drives data onto DAL 31:0] and asserts DS [data strobe col. 7, l. 56], indicating that the data is valid on DAL [31:0]. If no error occurs, the slave device reads the data, and the external logic asserts RDY. If an error occurs, external logic asserts ERR, which aborts the bus cycle. This causes the processor 10 to execute a machine check. Finally, the bus master deasserts AS and DS to end the cycle.” (Col. 9, ll. 58-65.) More specifically, Hayes describes how the assertion and deassertion of the DS (data strobe) provides timing for read and write operations as follows: The Data Strobe line (DS) provides timing information for data transfers. During a read cycle or an interrupt acknowledged cycle, the bus master asserts DS to indicate that it is ready to receive incoming data. The bus master then deasserts DS to indicate that it has received and latched the incoming data. During a write cycle, the bus master asserts DS to indicate that DAL [31:0] contains valid write data. The bus master then deasserts DS to indicate that it is about to remove the write data from DAL [31:0]. (Col. 7, ll. 56-65.) H3. External logic asserts the ERR function “whenever a parity error occurs on a read from a local RAM 13, provided that parity is enabled.” (Col. 11, ll. 33-35). The ERR function indicates “the abnormal termination of a read, write or interrupt acknowledge cycle.” (Col. 8, ll. 9-11.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 10 H4. Bus master read and write cycles typically last at least eight clock phases, with longer intervals possible in groups of four clock cycles. During the write cycle, the bus master drives an address onto DAL (data and address lines) and outputs data to the slave memory device at the end of the write cycle. (Col. 7, ll. 3-6; col. 9, ll. 33-65.) H5. In addition to the “slave device” as a memory board (see col. 7, l. 36, l. 44, H1), the “daisy chained memory array boards 15” (col. 5, l. 5 (emphasis added)) are also described as “devices” as follows: “The term ‘daisy chain’ in the system of the present invention implies . . . sequentially connecting a series of devices such that the output connection of device one is the input connection of device two . . . and so on. . . . A ‘memory node’ . . . refers to the points at which a device may be connected.” (Col. 2, ll. 33-43 (emphasis added).) Also, communication occurs “between any two devices on the local bus 17 . . . within a master/slave relationship.” (Col. 6, ll. 14-16 (emphasis added).) (The memory array boards 15 are on a bus 21 which “is an off-board extension of the local bus 17.” (Col. 5, ll. 3-5).) H6. Communication between the master and slave devices is time multiplexed. The time-multiplexed data and address lines (32 lines) on the local bus (see Figs. 1 and 2 (copied supra H1)) carry address information transmitted first to the slave device, followed by data, during a read or write cycle. Data can be 8 bits (one byte) 16 bits (one word), 32 bits (one longword), or 64 bits (one quad word.) (Col. 6, ll. 9-63; col. 7, ll. 3-6.) H7. Figure 7 depicts the components resident on the slave memory board 15 (depicted in Fig. 2, H1 supra). Figure 7 shows 32 “DAL 31:00” (data and address lines) external to the slave memory board (see H1 supra) directly connected to an on-board transceiver (interface) 57, which directly Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 11 connects to 32 on-board data and address lines “DATA <31:0>,” which directly connects to on-board RAM chips 64. The DS signal connects to RAM control logic 62 on the slave memory board. (Fig. 7; col. 22, ll. 10-15; col. 24, ll. 21-27.) Hayes - Anticipation of Claims 1, 7, 11, and 19 Rambus argues independent claims 1, 11, and 19 together, asserting that Hayes does not disclose a “memory device,” because the memory device in Hayes, a memory board, is not a single chip. (P.O. Cr. App. 12- 28.) However, claims 1 and 19 only recite a “memory device” in their respective preambles. Claims typically are not limited by such preamble recitations. Claim 1 does not refer back to the memory device in the body of the claim. Thus, under one claim interpretation here, claim 1 does not require a memory device. Similarly, claim 19 recites a memory device in the preamble which comprises, according to the claim body, receiver circuits having functional limitations. The body of claim 11 recites “the memory device” and refers back to the preamble’s “memory device.” Consequently, under the claim interpretation noted, Rambus’s arguments directed to the asserted lack of a memory device as a single chip are deemed to apply only to claim 11. The second claim interpretation assumes, for the sake of argument, that all the claims require a memory device. That second interpretation follows. Requestor NVIDIA’s contentions and the Examiner’s findings persuasively show that neither the plain and ordinary meaning of “memory device,” nor the ‘353 patent, requires a “memory device” to be limited to a single chip so as to preclude reading the independent claims onto the memory board of Hayes. The record also reveals no error in the finding that Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 12 Hayes’s DS signal constitutes a strobe signal as recited in the disputed claims. Mr. Murphy, Rambus’s expert, “read[s] the term ‘memory device’ in the context of the specification and claims as a device that is implemented on a single monolithic chip.” (Murphy Decl. ¶ 33 (attached to Rambus Cr. App. Br. at Ex. 9).) Mr. Murphy reasons that “the claims themselves are directed to ‘memory devices’ and as such, their recited features define the characteristics of a ‘memory device.’” (Id. at ¶ 34.) Mr. Murphy also reasons that the claims require “an array of memory cells,” and this feature and others, “are typical of those specifically directed to a memory device on a single monolithic chip.” (Id.) Mr. Murphy also opines that skilled artisans would have recognized that other portions of the ‘353 patent, such as the specification and the abstract, indicate that memory devices are consistent with a single chip. (Id. at ¶¶ 35-37.) Mr. Murphy also points to a DRAM with a unique device ID which “supports the understand [sic] that each DRAM is a separate ‘memory device’.” (Id. at ¶ 39.) Mr. Murphy further opines that the Examiner’s claim interpretation (under which Hayes’s memory board constitutes a memory device) is “inconsistent with the specification and inconsistent with how that term would have been understood by one of ordinary skill in the art.” (Id. at ¶ 32.) Mr. Murphy makes a similar statement in his testimony about Hayes, i.e., the Examiner’s use “is also inconsistent with how the term is commonly used in the DRAM field.” (Id. at ¶ 62.) Mr. Murphy’s bases his understanding on what someone “in the DRAM field would understand the term ‘memory device’” to be. (Murphy Decl. ¶62.) But the ‘353 patent is not limited to DRAM technology - just as Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 13 the memory device is not limited to a DRAM. For example, in other places, Rambus implies that the relevant field is “memory systems, memory controllers, and memory devices.” (See Rambus Cr. App. Br. 21.) Similarly, the ‘353 patent describes the invention even more broadly: “The present invention provides a method and apparatus for performing data transfers within a computer system.” (P1) (emphasis added).) In other words, Mr. Murphy’s understanding is based on an overly narrow foundation. Mr. Murphy’s testimony may show that the term “memory device,” as used in the ‘353 patent, is consistent with a single DRAM chip, but it does not show that the claims are limited to a single chip or that the Examiner’s interpretation of a memory device as a memory array board is inconsistent with the ‘353 patent. NVIDIA relies, inter alia, upon an IEEE publication defining “device” as including circuits on a board (D) to show that the disputed claims read on Hayes’s memory board pursuant to the ordinary and plain meaning of the term. (Req. Resp. Br. 5; compare H1-H5 with D.) Rambus’s contentions notwithstanding, NVIDIA’s contention has merit because the IEEE definition coalesces with Hayes’s memory board device; and “does not contradict any definition found in” the ‘353 patent. See Phillips, 415 F.3d at 1322-23 (“judges are free . . . at any time . . . [to] . . . rely on dictionary definitions when construing claim terms, so long as the dictionary definition does not contradict any definition found in or ascertained by a reading of the patent documents”). 1 1 Rambus argues that the Board should not consider the IEEE definition because the proffer is “substantively improper” and “procedurally improper” (P.O. App. Br. 21-22), but this argument runs counter to Phillips which Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 14 Rambus also argues that the ‘353 patent describes connecting the bus lines in Figure 4 to “each device” (P.O. Br. Cr. App. Br. 16) and that Figure 4 depicts single chip devices such as DRAMs and CPUs (id. at 16-17 (also citing and quoting Murphy Decl. at ¶ 38 and the ‘353 patent).) But Figure 4 represents the prior art, not necessarily the invention, and also shows interfaces, including R/T units, connected to the DRAMs and CPUs. Figure 4 does not unequivocally limit a memory device as recited in the claimed invention to a single chip memory device. Regardless of what Figure 4 represents, claims typically are not limited to embodiments shown in a figure. The ‘353 patent does not define a “memory device” as a chip as NVIDIA maintains. (Req. Resp. Br. 6-9.) The ‘353 patent broadly refers to “slave devices, such as memories.” (P2 (emphasis added).) In other words, even though the disclosure discusses DRAMs, the disclosure is consistent with including as a slave device, a typical slave memory, such as a slave memory board. Hayes supports this general understanding in the art. (See H1, H2, H5.) Hayes describes “slave invites judges at any time to consider such sources. Rambus relies upon, but the Examiner apparently did not consider, Mr. Murphy’s untimely second supplemental declaration (countering the IEEE definition). (See P.O. Cr. App. Br. 22-24 (citing Murphy 2 nd Supp. Decl. Ex. 15).) Rambus essentially repeats Mr. Murphy’s assertions in the noted declaration and argues that the definition is relevant to electrical circuits but not relevant to the memory arts, out of date, too general, too specific, too varied, untimely, and fails to define a “memory device.” (See P.O. App. Br. 21-25.) The definition, published in 1988, corroborated by Hayes, and consistent with the ‘353 patent, is probative, even if it also applies to earlier systems as Mr. Murphy maintains. (See Murphy 2 nd Supp. Decl. ¶¶ 7-10.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 15 device[s]” as memory array boards (H5), thereby underscoring, in line with Requestor’s proposed definition (E), that the term “memory device,” especially in reference to a slave device, carries a broad general understanding in the art. Requestor relies on this general understanding and refers to the Hayes “’SLAVE’ device” memory board in Figure 2 as a “memory device.” (Req. Resp. Br. 10-11; see H1, H5.) In the ‘353 patent and in Hayes, the slave memory devices each have their own control logic and memory arrays, and each slave device is tied to a bus node and responds to a master in a time multiplexed fashion. (Compare H4-H7 with P2, P4.) Moreover, the ‘353 patent unequivocally states that the disclosed embodiments are to be construed as illustrative and not as limiting the claims. (P3.) Rambus’s arguments here ignore that simple disclosure and attempt to read the DRAM embodiment as limiting. Carrying such arguments to their logical conclusion would require limiting the claims to other disclosed features and lead to absurd results. For example, the ‘353 patent describes four memory banks, two queues, control circuitry, and an I/O unit (see Fig. 20A) in one memory device embodiment and a slew of advantageous functional capabilities seemingly important to the invention. (Accord Murphy Decl. ¶¶ 19-20, 24, 35, 39 (describing interleave control, control and data decoupling, control circuits for precharging, internal interface clocks, four memory banks, and a unique device ID, as part of the disclosed memory device’s functionality to provide various benefits and improved ability).) Interpreting analogous claim terms involving a related Rambus patent, Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1094-95 (Fed. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 16 Cir. 2003) refused to read the ordinary term “bus” restrictively as a “multiplexed bus” even though the patentee described the “present invention” in terms of a “multiplexed bus” in isolated portions of the specification because “the remainder of the specification and the prosecution history shows that Rambus did not clearly disclaim or disavow such claim scope in this case.” 2 And in a related example, the ‘353 patent refers to “[d]ynamic random access memory (DRAM) components . . . [as] inexpensive solid-state storage technology for today’s computer systems.” (Col. 1, ll. 18-19.) Under Rambus’s theory of limiting claims based on preferred or sole disclosed embodiments, a memory component, which includes a DRAM, would also be limited to a single chip. Nowhere does the ‘353 patent unequivocally restrict a “memory device” to a DRAM or a single chip. The ‘353 patent does not “demonstrate[] a clear intention to limit the claim scope using ‘words of manifest exclusion or restriction’.” See Leibel-Flarsheim Co., 358 F.3d at 906; accord In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004) (“Absent claim language carrying a narrow meaning, the PTO should only limit the claim based on the specification or prosecution history when those sources expressly disclaim the broader definition.”). There is no “clear disclaimer in the specification,” Am. Acad. Of Science Tech. Ctr., 367 F.3d at 1369, and 2 Also stating that “‘[t]he present invention is designed to provide a high speed, multiplexed bus ’”(quoting Rambus’s related ‘918 patent, col. 5, ll. 36-46), but “the prosecution history shows that a multiplexing bus is only one of many inventions disclosed in the ‘898 application.” Id. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 17 the claims do not “bear only one interpretation.” 3 The ultimate purpose of the ‘353 patent is to maximize utilization of the channel over which communications are to be performed- i.e., increase the computer speed by interleaving the data packets over the bus to multiple devices thereon. (See ‘353 patent Abstract; accord P1).) Limiting the open-ended claims to a single memory chip is without support, as is limiting them to the disclosed DRAM chip embodiment. Claim 19 defines the memory device recited in the preamble as comprising a plurality of receiving circuits to handle write and strobe functions. NVIDIA contends (see Inter partes Request for Reexamination 18-19 “I.P. Request”), and the Examiner finds (Action Closing Prosecution 1-16), that Hayes’s memory board in Figure 7 comprises the recited receiving circuits performing the recited functions, and Rambus does not particularly dispute that finding (see P.O. Cr. App. Br. 18) other than to assert that the Hayes’s device is not a chip and does not receive a strobe 3 Johnson Worldwide Assocs., Inc. v. Zebco Corp., 175 F.3d 985, 991 (Fed. Circ. 1999) (distinguishing Laitram Corp. v. Morehouse Industries, Inc., 143 F.3d 1456 (Fed. Cir. 1988) as involving a “written description that made clear that ‘the asserted claims will bear only one interpretation . . . .’ Here of course, there is no such unambiguous language in the written description; nothing suggests that ‘heading’ is required to be the heading of the trolling motor.”). See also Edwards Life Sciences LLC v. Cook Inc., 582 F.3d 1322, 1329 (2009) (holding that the consistent interchanging of “interluminal graft 10” with “graft 10” in the patent and use of the phrase, “as defined above,” created a narrowing definition of graft to mean an interluminal graft). “[I]f the intrinsic evidence shows that the patentee distinguished that term from prior art on the basis of a particular embodiment, expressly disclaimed subject matter, or described a particular embodiment as important to the invention.” Id. at 1329. (citation omitted). Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 18 signal. Mr. Murphy agrees that the claims’ “recited features define the characteristics of a ‘memory device’” (Murphy Decl. ¶ 34), contradicting his opinion that the memory device is limited to a chip. Claim 11 recites related functional limitations implicit in a memory device, while claim 1 at most implies certain functions in a memory device. In any event, Hayes discloses a memory device as recited in independent claims 1, 11, and 19. As noted supra, Rambus objects to the dictionary definition provided by NVIDIA, but Rambus and Mr. Murphy do not provide similar objective corroborative and persuasive support by way of other patents, treatises, or dictionaries, to show why the term “memory device” is generally considered to be restricted to a chip. Cf. Infineon 318 F.3d at 1091 (holding that the term “integrated circuit device” as recited in claim 26 of Rambus’s related ‘804 patent takes its ordinary meaning of “chip”) (internal quotation marks and citations to trade dictionaries and other authority omitted); Mangosoft, Inc. v. Oracle Corp., 525 F.3d 1327, 1331 (Fed. Cir. 2008) (“‘the persistent memory device will be understood to include a plurality of local persistent memory devices’”) (quoting U.S. Pat. No. 6,148,377). Mr. Murphy also points to other Rambus patents (Murphy at ¶¶ 63-65), but in at least one occasion in a related Rambus patent, the Board found that the term “memory device” is not restricted to single chip. 4 NVIDIA notes that Rambus refers to the term “memory device” as a generic term in over 400 of their patents. (Req. Resp. Br. 4-5.) In the 4 BPAI Appeal No. 2010-011178, Reexam. No. 90/010420, now on appeal to the Federal Circuit (Appeal No. 2011-1247). See also infra note 9 and surrounding discussion. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 19 related patent just noted (note 4), the Board found that Rambus refers to and equates a memory stick, having a transceiver, multiple memory chips, and optionally, other controllers thereon, to a memory device, showing that at least some of Rambus’s related patents indicate that the ordinary meaning of a memory device includes a memory stick (i.e., a memory board). NVIDIA also points out that Rambus recited claims in other patents to a device “‘formed on a single semiconductor substrate’” and to a “‘single chip memory device.’” (Req. Resp. Br. 5 (citation to Rambus patents omitted).) While Rambus argues that “[e]ach patent is a separate legal instrument and should be interpreted separately with respect to its own claims and specification,” (P.O. Cr. App. Br. 21), NVIDIA’s reliance on these other Rambus patents to show the ordinary meaning of a memory device as including a memory board, is persuasive. (See Req. Resp. Br. 4- 5.) Mr. Murphy also cites to the iRAM handbook 5 and quotes a discussion there of “semiconductor memories” and the announcement there that “more than 3,000 different memory devices are now available.” (See Murphy Decl. ¶ 65 (quoting iRAM at 1-1 (emphasis by Mr. Murphy).) But referring to memory devices as semiconductor memories indicates that other forms of memory devices were known, such as the memory board devices of Hayes. On the same page cited by Mr. Murphy, the authors issue a caveat delimiting the scope of the article and supporting the notion that other known memories would, absent the caveat, otherwise be included in the 5 Memory Components Handbook, Intel. Corp., Ch. 1, 3 (1985) (“iRAM”). Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 20 term: “Tape and disk storage are also non-volatile memories but are not included within the scope of this book which confines itself to solid-state technologies in an IC form factor.” (iRAM 1-1 (emphasis added).) The ‘353 patent not only fails to issue a similar caveat, it does the opposite and proclaims that the claims are not to be limited by any disclosed embodiment. (P3.) Moreover, “[a]bsent an express definition in their specification, the fact that appellants can point to definitions or usages that conform to their interpretation does not make the PTO’s definition unreasonable when the PTO can point to other sources that support their definition.” In re Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997) Rambus also asserts that Hayes’s DS signal does not constitute the claimed strobe signal. (P.O. Cr. App. Br. 26-28.) This contention is not persuasive. The DS signal, a “data strobe” signal (H1, H2), reasonably indicates that data is valid on the data lines as the Examiner finds. (ACP 13- 14 (quoting Hayes at col. 9, ll. 49-65 and citing col. 7, ll.41-43); accord H2.) Figure 2 of Hayes depicts a slave memory board (the “memory device” in claims 1, 11, and 19) receiving “INFORMATION TRANSFER”s on data and address lines <31:0> under direct “BUS CONTROL” by the “BUS MASTER” which issues “DATA STROBE” (DS) and “WRITE” signals to the “SLAVE” memory device to cause such a write transfer of data based on the DS signal which indicates valid data on the bus. (H1, H2; see Req. Resp. Br. 10-11.) In sum, the bus master asserts DS when data is valid on the bus, the slave then reads the data (absent an abnormal abort as discussed below), and then the bus master deasserts DS when data is about to be removed from the bus. (H2.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 21 Rambus’s related assertion that data is not sampled until after an ERR signal in Hayes does not disturb the finding about DS. (P.O. Cr. App. Br. 27.) Rambus agrees with the Examiner that “the claims do not exclude other control signals” (P.O. Cr. App. Br. 27) but mischaracterizes another of the Examiner’s findings: “CRU [i.e., the Examiner at the Central Reexamination Unit] agreed that the memory device does not sample data in response to DS.” (Id.) To the contrary, the Examiner finds that “[t]he DS signal . . . functions to let the memory device known [sic] when to start to read/write data.” (RAN 10.) As the Examiner explains, the ERR signal provides a parity check which may override normal read/write functions, but the DS signal, the “data strobe” signal, tells the slave memory device in Hayes that the data is valid on the bus so that the slave memory device knows when to sample (read) it. (See RAN 9-10.) The record supports the Examiner. (H1-H3.) During a write cycle, the bus master asserts DS and the “slave device reads [samples] the data.” (H2, H6.) If there is no ERR signal after DS is asserted, the memory device reads (i.e., “samples”) the data from the bus. And any ERR signal only occurs rarely, in “abnormal” situations. (H3.) Moreover, parity must be, but need not be, enabled. (See H2.) In other words, in Hayes, the ERR function is an option which need not be enabled, and, in any event, occurs during an “abnormal” termination of a read, write, or interrupt. (H2, H3.) Rambus agrees that the independent claims do not preclude additional control as noted supra. It follows that the independent claims do not preclude the abnormal ERR control, whether optional or not. In a related argument, Rambus also contends that Hayes’s slave memory device does not sample data in response to Hayes’s DS signal. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 22 (P.O. Cr. App. Br. 27-28.) This argument lacks merit. The DS “provides timing for data control transfers” (H2), signifies to the the memory “slave” (H5) that data is valid (H2), and thereby starts the data transfer response of the “slave” memory to the “master” bus controller. (H2, H5.) Claim 1 “defer[s] sampling . . . until an external strobe signal is detected” and does not require an immediate response based on the strobe signal. As NVIDIA further points out, the ‘353 patent describes a delay between the strobe signal and subsequent data sampling (with a data sample occurring sometime after the strobe in further response to an external clock). (Req. Resp. Br. 12.) Rambus corroborates NVIDIA’s point and describes a similar delay between the data and the strobe. (P.O. Cr. App. Br. 10.) Since claim 1 neither requires an immediate response, nor precludes an infrequent (abnormal) or optional interrupt (such as by Hayes’s ERR system), even if Hayes delays sampling after the DS, in light of the ‘353 patent, the DS constitutes a strobe signal as recited in the independent claims because Hayes discloses that data is normally read by the slave memory device after DS during a write cycle. (H2, H4.) Rambus also argues that the doctrine of intervening rights forecloses the practical ability to freely amend claims during reexamination so that there is no valid policy reason for interpreting claims under a broadest reasonable standard. (P.O. Cr. App. Br. 25-26; .P.O. Reb. Br. 13-14.) This argument implies that Rambus seeks a substantive change to claim scope by presenting arguments as opposed to amending the claims, see e.g., Marine Polymer Technologies, Inc. v. HemCon, Inc., 659 F.3d 1084, 1092 (Fed. Cir. 2011) en banc rehearing granted, ___ Fed. Appx. ___ (2012), contradicting Rambus’s other assertions addressed supra about the intrinsic meaning of Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 23 the claim terms. But in any event, as NVIDIA maintains, Rambus’s position runs counter to In re Yamamoto, 740 F.2d 1569, 1571-72 (Fed. Cir. 1984) (opportunity to amend during reexamination dictates same broadest reasonable claim construction standard as applied during original prosecution). (See Req. Res. Br. 9-10.) Also, Rambus does not show that a different result necessarily would flow from a different standard under these facts, and Rambus does not show that the interpretations by the Examiner violate claim construction principles under Phillips, 415 F.3d 1303. Based on the foregoing discussion, the Rambus did not show that the Examiner erred in rejecting independent claims 1, 11, and 19 and dependent claim 7 not argued separately as anticipated by Hayes. Claims 5, 14, and 23 Dependent claims 5, 14, and 23 respectively depend from independent claims 1, 11, and 19, and further recite a terminate signal: Claim 5 recites “sampling additional portions of the data during a time interval between detection of the external strobe signal and detection of the external terminate signal.” Claim 14 recites “issuing additional portions of the data to the memory device; and issuing a terminate signal to the memory device to signal to the memory device to stop sampling data.” Claim 23 recites “wherein the plurality of input receiver circuits receive additional portions of the data before detection of a terminate signal.” The Examiner reasons that in Hayes, the deassertion of the DS signal constitutes the terminate signal satisfying these dependent claims. The Examiner also reasons that a 32 bit “longword,” which Hayes transmits between the assertion and deassertion of DS, comprises a first portion and additional portions of data as recited in the claims. (RAN 11-12.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 24 Rambus treats the claims as a group and argues that “the CRU appears to have construed the claims erroneously.” (P.O. Cr. App. Br. 28.) Rambus maintains that since Hayes only discloses that data is about to be removed from the bus after the deassertion of DS, Hayes does not satisfy the claims because data sampling is still possible after the DS assertion and Hayes does not signify exactly when the sampling stops. (P.O. Cr. App. Br. 29.) 6 Claim 14 requires the terminate signal “to signal to the memory device to stop sampling data.” Claims 5 and 11 are similar. Like the system in Hayes, claims 5, 11, and 14 fail to define exactly when the sampling must stop (or for how long it must stop). For example, the claim reasonably allows for the memory device to complete the sampling of data already on the data lines (e.g., within a predetermined number of clock cycles after the terminate signal), and thereafter, to allow more sampling after the next strobe or DS signal. As NVIDIA explains, the ‘353 patent supports this claim interpretation: i.e., data transmission, and hence sampling thereof, occurs for at least three clock cycles after the terminate signal. (Req. Resp. Br. 13 (citing table and ‘353 patent, cols. 25-28).) NVIDA’s explanation of this delay coalesces with Rambus’s. (See Rambus App. Br. 10 (showing 6 Rambus points to Hayes as removing data from DAL lines (connected externally to the asserted memory device in Hayes (see H1, H7), and argues that the data lines “DATA” are the only ones connected to “the alleged memory device.” (See P.O. Cr. App. Br. 29.) This argument is not clear. In any case, during a write operation, the DAL lines (connected externally to the memory board device (H1)) and the DATA lines (connected internally on the memory board device (H7)) are connected together via the data transceiver 57 of the memory device and the assertion of DS indicates that both buses contain valid write data. (See Parris Decl. ¶¶ 15-16; Hayes, Fig. 2, H7.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 25 data transmission beginning between the strobe and terminate signal and ending after the terminate signal).) Rambus also maintains that Hayes does not disclose sampling “additional portions” of the data before the deassertion of DS because “quadwords are transferred over two write cycles.” (Rambus App. Br. 29.) But claim 14 does not even require the additional portions to be sampled because it recites “stop sampling data” which may refer to the “first portion of the data” introduced in independent claim 11. Claim 23, a product claim, recites an intended use of the terminate signal, and requires the device to be capable of receiving additional data before a terminate signal. Hayes’s slave device at least has that capability since it responds to the assertion of DS and the data is removed after the deassertion of DS, thereby signifying to the slave device not to read data after the DS deassertion as the Examiner finds. (See RAN 12, H2, H4.) Claim 5 requires sampling additional portions between the strobe and terminate signal, and to the extent claims 14 and 23 could be interpreted similarly, the following discussion applies. The above-noted quadwords are 64 bits long, and represent two 32 bit longwords. (See H6.) According to Rambus, each write transaction corresponds to one DS assertion followed by its deassertion, so that for one quadword transaction, “the DS signal would be asserted and deasserted twice” - once for each longword which occurs over two write cycles. (P.O. Reb. Br. 17.) Under Rambus’s description, Hayes still satisfies the claims, because the terminate signal in the claims is broad enough to read on the second deassertion of DS in Hayes, since the claims simply do not define when the terminate signal occurs. Therefore, under the quadword scenario described Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 26 by Rambus, the first Hayes longword of the quadword constitutes a first portion of the data and the second longword of the quadword corresponds to the additional portion of data in the claims. (See Req. App. Br. 13-14 (asserting the second longword write corresponds to additional data portions).) Alternatively, as NVIDIA and the Examiner also maintain, a single longword (32 bits) constitutes two portions of data - for example, one 16 bit group in the word for the first portion and another 16 bit group for the additional portion). (RAN 12; Req. Resp. Br.13-14.) Rambus asserts that this is not “rational” because all 32 bits in Hayes are sampled at one time. (P.O. Cr. App. Br. 18.) But the claims simply do not require sampling the two different portions at different times and Rambus fails to direct attention to any claim term which precludes simultaneous sampling of different data portions on the 32 bit lines of Hayes. Based on the foregoing discussion, Rambus fails to show error in the rejection of claims 5, 14, and 23. NVIDIA’s APPEAL The Examiner did not maintain the following proposed rejections by Requestor: Claims 11, 15-16, and 18 as invalid under 35 U.S.C. § 101 for obviousness-type double patenting based on Farmwald et al., U.S. 6,584,037 B2 (June 24, 2004)(“Farmwald ‘037”). Claims 11, 15, 16, and 18 as anticipated under 35 U.S.C. § 102(e) by Farmwald ‘037. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 27 Claims 3, 4, 12, 13, 22, and 23 are obvious as obvious under 35 U.S.C. § 103(a) based on Barth et al., U.S. 5,748,914 (May 5, 1998) and Kushiyama et al., A 500-Megabytes Data-Rate 4.5M DRAM, IEEE J. Sol. State Circ., V. 28, No. 4 (April 1994) (“Kushiyama”). Claims 2, 6, 10, 17, and 25-26 as obvious under 35 U.S.C. § 103(a) based on Hayes and Bennett et al., U.S. Patent 4,734,909 (Mar. 29, 1988) ("Bennett"). Claims 3-4, 12-13, and 21-22 as obvious 35 U.S.C. § 103(a) based on Hayes, Bennett and Inagaki, JP 57-210495 (Dec. 24, 1982). Claims 12 and 13 as obvious under 35 U.S.C. § 103(a). based on Hayes and Inagaki. Claims 2-10, 12-14, 16-17, and 20-26 as obvious under 35 U.S.C. § 103(a) based on Hayes and Ohshima et al., High Speed DRAMs with Innovative Architectures IEICE Trans. Electron V. ECC-7, No. 8, 1303-15 (Aug. 1994) (“Ohshima”). Claims 1-14, 16-17, and 19-26 as obvious under 35 U.S.C. § 103(a) based on Kushiyama, Hayes, and Lu, The Future of DRAMs, 1988 IEEE Inter. Solid-State Cir. Conf. (ISSCC), Digest Tech. Papers, 98-99 (Feb. 1988)(“Lu”). Claims 1-4, 6-9, 11-13, 15-16, 18-22, and 24-26 as obvious under 35 U.S.C. § 103(a) based on Farmwald et al., U.S. 5,319,755 (June 7, 1994) (“Farmwald ‘755”) and Lu. Claims 1-4, 6-9, 11-13, 15-16, 18-22, and 24-26 as obvious under 35 U.S.C. § 103(a) based on Farmwald ‘755 and iRAM (supra note 5). (See Req. App. Br. 5-6.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 28 Issues As the discussion below indicates, the Briefs and Answer raise the following issues of whether NVIDIA demonstrated that the Examiner erred in failing to maintain the rejections listed supra. Based on the finding of error with respect to claims 1-26, which are all of the claims on appeal, we decline to reach the first three rejections listed supra. Hayes with Bennett - Obviousness of Claims 2, 6, 10, 17, 25, and 26 NVIDIA’s contentions are persuasive to show that the Examiner erred by not maintaining the obviousness rejections based on Hayes and Bennett. 7 (Req. App. Br. 6-9.) NVIDIA’s Inter Partes Request for Reexamination (attached to Req. App. Br. as Exhibit 1) and as supplemented by NVIDIA’s explanations of record, including the Briefs, are also incorporated here by reference. The Examiner agrees that Hayes discloses a memory device and anticipates claim 1, but maintains that including all the RAM control logic into each Hayes DRAM chip would not have been obvious. (See RAN 3, 33, 40-43.) But dependent claim 2 recites sampling data synchronously and does not require all the RAM control logic to be integrated into each chip. NVIDIA points out that the term “memory device” in these claims is not limited to a single chip (Req. App. Br. 7 n. 3), but even if they are, NVIDIA 7 As discussed supra, the Examiner maintained NVIDIA’s proposed anticipation rejection of claims 1, 5, 7, 11, 14, 19, and 23 based on Hayes. While NVIDIA also proposed alternative obviousness rejections based on Hayes and Bennett with respect to those rejected claims, NVIDIA does not appeal with respect to them. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 29 persuasively shows the obviousness of creating a single chip. (See Req. Reb. Br. 4 n. 7(citing IP Request at 24); see also IP Request 19-24). The claim 2 memory device, whether as a chip or a broader device, requires strobe functionality which Hayes teaches and synchronization which Bennett teaches according to this record. As NVIDIA persuasively explains, Hayes describes time-multiplexed clock data transfers between a master and slave during different clock cycles, and Bennett teaches benefits to providing a synchronized interface in a memory device using an external clock. (See Req. App. Br. 6-9; H6.) The Examiner does not appear to disagree with these findings. (See RAN 41-43.) NVIDIA also relies on Mr. Parris who testifies that ordinarily skilled artisans were shifting from asynchronous to synchronous operations to increase speed. (Req. App. Br. 8 n. 8 (citing Parris Decl. at ¶ 17 attached to Req. App. Br. at Ex. 30); see also Paris Decl. ¶¶ 18-20).) Based on this record, NVIDIA shows that it would have been obvious in view of Bennett to implement certain control logic, including a synchronous logic interface, into the memory device of Hayes. (See Req. App. Br. 6-9.) Hayes, Bennett, and Inagaki - Obviousness of Claims 3, 4, 12, 13, 21, and 22 Additional Findings of Fact Inagaki 8 I1. Inagaki teaches a desire to increase data transfer rates in computers, and discloses a method for increasing data rates in block access 8 Reference hereinafter is to an English translation attached to NVIDIA’s Appeal Brief as Exhibit 5. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 30 memory. As background, Inagaki teaches that conventional methods to increase data transfer rates in RAMs were to increase the data bus width, which adds cost of packaging and pin count, or to increase the clock rate. (Inagaki 2.) Inagaki’s solution involves using dual edges of an external clock as the following quotations indicate. I2. “The rise and fall of external clock φ are detected, and clocks φ1 and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift register. . . . In this way, since one bit is output on each half-cycle, the operating speed is twice that of the conventional speed.” (Id. at 4.) I3 “[T]he present invention presents block access memory that transfers data with a speed that is twice the conventional speed, by performing I/O [input/output] of data on every half-cycle of the external clock that drives the I/O shift register.” (Id. at 3.) Discussion NVIDIA’s contentions are persuasive to show Examiner error in failing to maintain the rejection. The Examiner relied on the above- discussed reasons with respect to Hayes and Bennett. (See RAN 43.) Inagaki’s system improves memory access speed by providing data transfers at odd and even (i.e., both) clock edges thereby doubling the overall speed. (See Req. App. Br. 9-11; I1-I3.) Rambus’s contention that Inagaki “uses the word ‘clock’ in numerous locations” but does not disclose a clock because the clock is pulsed and not periodic, lacks merit. (P.O. Resp. Br. 10.) The clock is periodic while it runs, and in any event, skilled artisans would have understood that using the dual clock edges in Bennett’s external clock would have doubled the system speed, provided for the same speed using a slower Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 31 clock, or provided a mechanism to minimize the number of data lines. (See I1-I3.) Inagaki discloses an “external clock φ” (I2) having odd and even phases (i.e., on dual rising and falling edges of the external clock (Inagaki Fig. 6; see I1-I3)) which in turn generate clock phases “to transfer data with . . . twice the conventional speed” (I3). Rambus also contends that Inagaki’s clock signal is not external and that that motivation to combine the references lacks because Hayes describes an asynchronous system. (P.O. Resp. Br. 11.) These arguments are not persuasive. Asynchronous to synchronous migration was well-known and common. (See Paris Decl.) Hayes, Bennett, and Inagaki disclose external clocks, and a “universal” desire for “faster” operations creates an “implicit motivation,” which is not isolated to asynchronous devices. See Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit motivation to combine exists … when the ‘improvement’ is technology-independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”) Also, Hayes employs a clock to drive time multiplexed signals between a master and slave (H6), thereby suggesting a substitute clock operating at half the speed, a fewer number of data lines based on using both clock edges, or a faster clock, as Inagaki (I1-I3) suggests. Based on the foregoing discussion, the Examiner erred by failing to maintain Requestor’s proposed rejection of claims 3, 4, 12, 13, 21-23, 33, and 34. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 32 Hayes with Inagaki - Claims 12 and 13 Based on the Rambus’s explanation (P.O. Resp. Br. 11-12), NVIDIA did not specifically propose the above-listed rejection, but instead also included Bennett in the rejection heading and claim chart. (See Req. App. Br. 11 (citing claim chart “Exhibit L” which is attached as Exhibit 13 to Requestor’s Appeal Brief).) But it is apparent that Bennett’s teachings were employed to suggest a single chip under the narrow definition of memory device, and to suggest synchronization as necessary to reach claim 2, but claims 12 and 13 do not require either. Therefore, this rejection is hereby remanded for further consideration and under the broader interpretation of a “memory device” which is not limited to a single chip. Hayes with Ohshima - Claims 2-10, 12-14, 16, 17, and 20-26 Based on the NVIDIA’s explanation, the Examiner erred by failing to consider the above rejection. (See Req. App. Br. 12-13 n.16 (citing Exhibit M and the IP Request at 30-35 which are attached respectively as Exhibits 1 and 14 to Requestor’s Appeal Brief).) Taking claim 3 as an example, NVIDIA discusses providing the relevant functionality of Ohshima’s clocking scheme in the system of Hayes. (See IP Request 30-31 and claim chart at Ex. 14 of Requestor’s Appeal Brief.) Requestor provides a similar explanation in the Brief for claims 12 and 13. The Examiner agrees that “Ohshima discloses the incorporation of logic into a memory device” (RAN 44) but finds that it would not have been obvious to incorporate all of the Hayes RAM control logic into the DRAMs of Hayes since some of the logic must be kept separate from the DRAMs. (See RAN 44-45.) However, the claim rejections here do not require incorporating all the circuits and functionality into all the DRAMs, though a Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 33 focus on remand as to which particular circuits and functions would have been obvious and required by the claims may shed more light. Based on the foregoing discussion, the Examiner erred by not maintaining the above rejections of claims 2-10, 12-14, 16, 17, and 20-26. Kushiyama with Hayes and Lu - Claims 1-14, 16, 17, and 19-26 Based on the NVIDIA’s explanation, the Examiner erred by failing to maintain the above rejection. (See Req. App. Br. 14-16.) Similar to the above rejection, the Examiner agrees that Lu teaches incorporating logic circuits into memory, but finds that it would not have been obvious to incorporate the Hayes RAM control logic into DRAMs since some of the logic must be kept separate from the DRAMs. (See RAN 44-45.) However, the rejection here does not require incorporating all the RAM control logic into DRAMs and the finding indicates the obviousness of keeping some functions in a controller. NVIDIA reasons that integrating the DS logic of Hayes into the Kushiyama chips would have been obvious where Lu teaches incorporating on-chip logic to make DRAMs more intelligent and to optimize performance at the system level. (Req. App. Br. 14-15.) Mr. Paris corroborates this point and notes that chip designers were employing asynchronous circuits on-chip, including some strobe signals, like RAS and CAS, and that moving such circuits on-chip increase speed. (Parris Decl. ¶¶ 9, 19.) Therefore, based on this record, the Examiner erred by failing to maintain the obviousness rejection of claims 1-14, 16, 17, and 19-26. Farmwald ‘755 with either of Lu or iRAM Obviousness of Claims 1-4, 6-9, 11-13, 15, 16, 18-22, and 24-26 Primarily, the parties dispute whether or not Farmwald ‘755, in view of either Lu or iRAM, renders obvious sending a strobe signal to a “memory Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 34 device” as required by the independent claims at issue. (See Req. App. Br. 18-21.) Rambus does not dispute that Farmwald ‘755 sends a strobe signal called the TrncvrRW signal to a memory stick. (See P.O. Resp. Br. 21 (stating that the TrncvrRW signal “allegedly function[s] as the claimed strobe signal” without arguing otherwise).) Additional Findings of Fact Farmwald ‘755 FW1. Farmwald employs a master/slave bus-based system. A master gives “each device on the bus a unique device identifier (device ID)” (col. 15, ll. 23-24) and uses the identifier to access a specific device. “[E]ach device connected to the bus contains a special device-type register which specifies the type of device, for instance CPU, 4 MBit memory, 64 MBit memory or disk controller.” (Col. 15, ll. 33-36.) Masters also send request packets and detect collisions for bus arbitration. (Col. 13, ll. 7-12; col. 14, ll. 52-61.) FW2. The disclosed invention saves power by performing a row access on a “single RAM to supply all the bits for a block request (compared to a row-access in each of multiple RAMs in conventional memory systems) [and thus] the power per bit can be made very small.” (Col. 18, ll. 9-12.) Such reduced power allows RAMs to be stacked and/or placed closer together than RAMs in the prior art. (Col. 18, ll. 13-16, ll. 45-49.) FW3. The invention also provides for a multiplexed time shared bus on a small number of bus lines. Therefore, the number of pins per device, even for an “arbitrarily large memory device[,] can be kept quite small - on the order of 20 pins . . . . [, and] kept constant from one generation of DRAM density to the next.” (Col. 18, ll. 20-23.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 35 FW4. An op code transmitted in a request packet to a slave DRAM device specifies the time delay for writing a block of data to the data lines. The code either directly specifies a register in the DRAM which holds the delay value or the DRAM indirectly responds to the codes with preselected access times (apparently via a table). (See col. 9, l. 27 to col. 10, l. 17.) FW5. The DRAMs in Farmwald ‘755 differ from conventional DRAMs in a number of ways. Registers are provided which may store control information, device identification, device-type and other information appropriate for the chip such as the address range for each independent portion of the device. New bus interfaces circuits must be added and the internals of prior art DRAM devices need to be modified so they can provide and accept data to and from the bus at the peak data rate of the bus. This requires changes to the column access circuitry in the DRAM, with only a minimal increase in die size. A circuit is provided to generate a low skew internal device clock for devices on the bus, and other circuits provide for demultiplexing input and multiplexing output signals. (Col. 4, ll. 21-35.) FW6. Farmwald teaches that up to about 32 of the above-described DRAMs can be used on the bus while maintaining speed. If more memory is required, anther device can be used, a memory stick, also called a primary bus unit (see Fig. 9), which itself can carry up to about 32 such DRAMs on the stick (i.e., a circuit board), and the memory system can employ multiple memory sticks. Each memory stick includes a transceiver in addition to one or more DRAMs, all connected on a primary bus. Each memory stick, with its primary bus of DRAMs, then connects via the transceiver device to a larger system bus, called a transceiver bus. (Col. 20, l. 48 to col. 21, l. 17; col. 22, ll. 1-31.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 36 “The transceivers are quite simple in function. They detect request packets on the transceiver bus and transmit them to their primary bus unit.” (Col. 21, ll. 18-20.) FW7. Farmwald ‘755 refers to a “memory device,” a “transceiver device” and “peripheral devices” as follows: In a preferred implementation, all masters are situated on the transceiver bus so there are no transceiver delays between masters and all memory devices are on primary bus units so that all memory accesses experience an equivalent transceiver delay, but persons skilled in the art will recognize how to implement systems which have masters on more than one bus unit and memory devices on the transceiver bus as well as on primary bus units. In general, each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices on an attached primary bus unit. Other devices, generically referred to as peripheral devices, including disk controllers, video controllers or I/O devices can also be attached to either the transceiver bus or a primary bus unit as desired. (Col. 20, l. 67 to col. 21, l. 14 (emphasis added).) FW8. The system uses a TrncvrRW signal to control writing and reading as follows: Persons skilled in the art will recognize that a more sophisticated transceiver can control transmissions to and from primary bus units. An additional control line, TrncvrRW can be bused to all devices on the transceiver bus, using that line in conjunction with the Addr-Valid line to indicate to all devices on the transceiver bus that the information on the data lines is 1) a request packet, 2) valid data to a slave, 3) valid data from a slave, or 4) invalid data (or idle bus). Using this extra control line obviates the need for the transceivers to keep track of when data needs to be forwarded from its primary bus to the transceiver bus - all transceivers send all data from their Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 37 primary bus to the transceiver bus whenever the control signal indicates the condition 2) above. (Col. 21, ll. 35-49 (emphasis supplied).) Farmwald’ ‘755 discloses a “still more sophisticated transceiver” (which only sends signals at requested times) in addition to the just- described transceiver. (Col. 21, ll. 65-68.) FW9. Farmwald ‘755 describes device interfaces as follows: The device interface to the high-speed bus can be divided into three main parts. The first part is the electrical interface. This part includes the input receivers, bus drivers, and clock generation circuitry. . . . The final part, specifically for memory devices such as DRAMs, is the DRAM column access path . . . . Persons skilled in the art recognize how to modify prior-art address comparison circuitry and prior-art register circuitry in order to practice the present invention. (Col. 22, ll. 34-52 (emphasis supplied).) FW10. Circuitry which is “well-suited for use in DRAM devices . . . can be used or modified by one skilled in the art for use in other devices connected to the bus of this invention.” (Col. 22, ll. 57-61.) Lu L1. The Lu moderator predicts that “opportunities arise for incorporating complex on-chip logic functions to make DRAMs more intelligent.” (Lu 98, ¶ 1.) One of the Lu article panelists explains that adding logic functions on-chip with the memory, provide high density and high performance in electronic systems. Data processing executed within one chip eliminates interface loss in speed and power consumption, which has been existing inevitably in combinations of standard DRAMs with basic common functions and logic parts. (Lu 99, ¶ 1.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 38 Discussion The Examiner and Rambus dispute NVIDIA’s contention that it would have been obvious to employ the ‘755 patent’s TrncvrRW (i.e., strobe) signal as a signal to a memory device - as recited in the claims at issue. (P.O Resp. Br. 21-29; RAN 12-24.) Contrary to Patent Owner’s arguments and the Examiner’s findings, Farmwald ‘755, with or without Lu’s or iRAM’s teachings, at least renders obvious employing the TrncvrRW strobe signal to a “memory device” as recited in the claims at issue here. Requestor presents two theories for the obviousness rejection: 1) sending the TrncvrRW signal to a single chip device would have been obvious, and 2) modifying the memory stick device to form a single chip would have been obvious. (Req. App. Br. 18-22.) Farmwald ’755 states that “TrncvrRW can be bused to all devices on the transceiver bus.” (FW8 (emphasis added).) Requestor notes that the Examiner acknowledges this teaching. (Req. App. Br. 19 n.25 (citing RAN at 22).) But the Examiner finds that it is “unknown” whether chip memory devices are on the transceiver bus. (RAN 22.) Rambus similarly maintains that the TrncvrRW signal is only provided to the transceiver device (P.O. Resp. Br. 23) and that Figure 9 depicts only transceiver devices, not memory devices, on the transceiver bus (P.O. Resp. Br. 26). According to Rambus, since only memory stick transceivers receive the TrncvrRW signal, motivation for the proposed modification lacks and Farmwald ’755 teaches away from applying the TrncvrRW signal to a single memory device. (See P.O. Resp. Br. 24-27). Rambus also maintains that NVIDIA failed to Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 39 respond to the Examiner’s teaching away finding, thereby waiving the issue. (P.O. Resp. Br. 21.) There is no dispute that Farmwald ‘755 discloses at least two embodiments, a single-chip DRAM device (Fig. 2), and a primary bus unit - also described as a memory stick device (Fig. 9). (See FW6.) This memory stick includes at least one DRAM and a transceiver. (FW6; FW7.) By arguing that only transceiver (i.e., memory stick) devices are on the transceiver bus, and that the phrase “all devices on the transceiver bus” (FW8) refers only to such memory stick devices and not to memory chip devices, Rambus ignores the phrase “all devices” and another passage in the ‘755 patent which describes “memory devices on the transceiver bus as well as on primary bus units” (FW7 (emphasis added)). (Similar to arguments presented supra that a memory device is limited to a single chip, Rambus asserts that a memory stick can replace, but is not, a memory device in a related reexamination now on appeal to the Federal Circuit (BPAI App. No. 2010-0011178, Reexam. No. 90/010420.) 9 As such, NVIDIA’s argument is persuasive and supported by the record: The TrncvrRW signal indicates that “‘valid data to a slave’” is available on the data bus, and that “[c]learly, a slave (e.g., a memory device should not begin sampling data from the bus if the data is not valid. Also . . . all devices on the bus receive the TrncvrRW signal”, including the 9 See supra note 4. The Board held in Appeal No. ‘1178 that the memory stick embodiment disclosed in the related ‘918 patent there under reexamination is a memory device. The ‘918 patent claims continuity to the ‘755 patent which both claim continuity back to the same underlying application. Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 40 single-chip DRAM memory devices and the primary bus units. (Req. App. Br. 19.) Farmwald ‘755 also specifically teaches that “each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices,” i.e., can be practiced using a memory stick. (FW7 (emphasis added).) Thus, even if Farmwald ‘755 does not anticipate the claims at issue here, skilled artisans would have recognized that teachings involving a single-chip (DRAM) memory device apply to transceiver devices and vice versa as Farmwald ‘755 indicates. (FW7; see also FW10 (showing that skilled artisans would have recognized that other devices on the bus can be modified similarly to DRAMs).) The Examiner’s findings do not rebut persuasively NVIDIA’s contentions for obviousness. The Examiner points to arguments by Rambus and Respondent’s expert Mr. Murphy and concludes that Farmwald ‘755 teaches away from the claimed invention because the memory stick embodiment provides for chip expansion - i.e., allowing the number of chips on the stick to increase. (RAN 23 (citing Murphy Supp. Decl. ¶ 34).) According to the Examiner, integrating the memory stick into a single chip removes the benefit of chip expansion, thereby teaching away from such integration. (RAN 23.) Based on the discussion above, the Examiner’s rationale, like Rambus’s, fails to address the fact found supra that all memory devices in Farmwald ‘755 receive the strobe signal, TrncvrRW. Thus, Farmwald’ 755 cannot teach away as asserted. And the finding of teaching away contradicts the Examiner’s finding that it is unknown whether the signal goes to both Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 41 devices and Rambus’s assertion that the chip and stick embodiments act as (slave) replacements for one another. The ‘353 patent at least suggests that each device can receive a TrncvrRW signal to indicate valid data to that slave. Also, contrary to the Examiner’s and Patent Owner’s rationales, even if memory sticks allow for chip expansion, this does not relate to NVIDIA’s first listed rationale for combining Farmwald ‘755 and Lu (or iRAM) - i.e., whether or not applying the TrncvrRW signal to a single chip would have been obvious. In other words, Farmwald ‘755’s memory sticks could have been expanded regardless of whether or not it would have been obvious to send the TrncvrRW signal directly to the single-chip devices disclosed in Farmwald ‘755. As NVIDIA similarly points out, one major benefit of the Farmwald ‘755 system is to allow different types of devices, including peripheral devices, DRAMs, and memory sticks, to attach to the bus. (Req. Reb. Br. 6-7 n.12; accord FW1; FW7.) Farmwald ‘755 also indicates other goals, such as decreasing the power per pin while allowing for natural DRAM expansion in “an arbitrarily large memory device” (FW3). (Accord FW2.) Modifying a DRAM so that it accepts the TrncvrRW signal in the manner proposed does not deter from the goal of also providing an expandable memory stick and other devices attached to the bus, and such DRAM modifications were well within the skill in the art. (See e.g. FW7, FW9, FW10, L1, Paris Decl. ¶¶ 9, 14).) Farmwald ‘755 teaches modifying existing DRAMs (FW4, FW9, FW10) and teaches “sophisticated” and “still more sophisticated” devices (FW8.) And Farmwald ‘755 does not clearly define a transceiver (on a Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 42 memory stick) as a master (see FW7), as masters have relatively complicated functions (FW1), and the transceiver devices are described as bus interfaces with relatively simple functions (FW6). Accordingly, Rambus’s contention that one of the Farmwald ‘755 goals is to keep slaves as simple as possible (P.O. Resp. Br. 27) ignores the fact that a memory stick typically functions as a slave (with some embodiments having masters thereon) but can become more sophisticated to obtain other goals (i.e., a tradeoff). Most if not all of the goals (e.g., low power per pin, DRAM memory expansion, attachment of multiple devices to a small bus, high speed, etc., see FW2, FW3) would not have been compromised by sending a TrncvrRW strobe signal to a DRAM. NVIDIA further relies on Lu to show that it would have been obvious to employ known memory stick functions in a single integrated DRAM package to increase speed and decrease power consumption. (Req. App. Br. 20 (quoting Lu at 99); accord L1.) Farmwald ‘755 buttresses Lu and shows that skilled artisans knew how to modify existing DRAM logic circuits (FW9), and Farmwald ‘755 specifically teaches modifying such DRAMs (FW1-3, FW5, FW10). Rambus’s counter arguments that Lu is equivocal and teaches away from moving logic on-chip are not persuasive. (P.O. Resp. Br. 27-30.) Rambus’s arguments show that Lu teaches tradeoffs in terms of “economics” versus “generic[ ]. . . benefits.” (P.O. Resp. Br. 27.) But the benefits of speed, reduced power (i.e., efficiency), and compactness constitute universal motivators “even absent any hint of suggestion in the references themselves.” Dystar, 464 F.3d at 1368 (“[A]n implicit motivation to combine exists … when the ‘improvement’ is technology- Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 43 independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”) “In such situations, the proper question is whether the ordinary artisan possesses knowledge and skills rendering him capable of combining the prior art references.” Id. Rambus does not direct attention to sufficient evidence showing that skilled artisans were incapable of combining memory stick functions into a DRAM (which would have rendered the DRAM faster, smaller, and more durable than the memory stick). Under another, but similar, rationale involving the proposed rejection based on Farmwald ‘755 and Lu or iRAM, NVIDIA contends that it would have been obvious to integrate the transceiver and DRAMs of Farmwald’s memory stick into a single chip. (Req. App. Br. 20-22 (id. at 22 citing I.P. Request at 58-59.) Here, the Examiner’s and Respondent’s teaching away rationale based on defeating chip expansion on the memory stick may be more applicable, but it is not persuasive. Even if a manufacturer would have produced memory sticks for the purpose of providing a customer the option of adding more DRAM chips to the memory stick as the Examiner and Rambus maintain, it does not follow that other customers would not have desired a large amount of memory in a single integrated chip, based on the reasons discussed supra. For example, such a chip would have offered speed, compactness, efficiency, and durability based on the integration, universal desires carrying implicit motivation according to Dystar, 464 F.3d at 1368. Farmwald ‘755, like iRAM, (I1-I3) describes a natural growth in the industry toward enhanced memory DRAMs (FW3), and indicates that Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 44 integrating new circuits and logic into existing single-chip DRAMs was routine (FW 5, FW9, FW10). Moreover, iRAM assumes an integrated memory device (i.e., iRAM means integrated RAM) and teaches shifting some of the CPU tasks to this integrated RAM, relieving the CPU of hardware and transceiver functions. (iRAM 1-1; 3-432-433.) 10 In other words, iRAM teaches integrating more functions into a single device, an integrated memory, to relieve the CPU. Rambus’s arguments fail to show with persuasive evidence that a memory stick device would have been as fast (or as compact or durable) as an integrated DRAM. And iRAM points skilled artisans towards an integrated memory - based, for example, on the noted universal desires. Mr. Murphy relies on Farmwald ‘755 (Murphy Supp. Decl. at ¶50 (citing col. 21, ll. 27-34) to show speed reduction, but Mr. Murphy does not explain why this occurs. 11 The evidence and common sense indicates that an integrated transceiver and DRAM would have been faster than a non-integrated transceiver and DRAM merely based on the distance (propagation delay) between the two. (See Parris Decl. ¶ 19; L1; iRAM 4-433 (“optimized timing”)). Rambus and the Examiner do not contend, much less show, that skilled artisans, motivated by the universal desire for speed, durability, and 10 These latter pages, i.e., 3-432, etc., appear under headings of “AP-132” on each page, which appear to signify an attached application note by John J. Fallin and William H. Righter (Intel. Corp. 1982). (See iRAM at 3-431.) 11 Mr. Parris states that Mr. Murphy fails to provide a reason why “moving logic on-chip” would decrease speed, and explains that physically closer devices increase speed. (Parris Decl. ¶ 19.) Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 45 compactness, would have lacked the capability to integrate the memory stick components into a single chip. Pursuant to the foregoing discussion, the Examiner erred by not maintaining NVIDIA’s proposed rejection of claim 1, based on Farmwald ‘755 and Lu or iRAM, and also, the proposed rejection of claims 2-13, 15, 16, 18-22, and 24-35, because the Examiner focuses on the alleged deficiencies of the rejection of claim 1. Remaining Proposed Rejections Reversal of the failure to maintain the proposed rejections of claims 1- 26 makes it unnecessary to reach the remaining rejections for anticipation and double patenting based on Farmwald ‘037, and for obviousness based, inter alia, on Barth. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding anticipation). DECISION The Examiner’s decision to reject claims 1, 5, 7, 11, 14, 19, and 23 as anticipated based on Hayes is affirmed. The Examiner’s decision not to reject appealed claims 1-26 for obviousness based on the listed references supra is reversed. 12 AFFIRMED-IN-PART ak 12 See Bd.R. 41.77(b) (reversal of determination not to reject is denominated a new ground of rejection). Appeal 2011-010623 Reexamination Control 95/001,169 Patent 6,591,353 B1 46 Finnegan Henderson Farabow Garrett & Dunner, LLP 901 New York Avenue, NW Washingon, DC 20001 Third Party Requester: Haynes and Boone, LLP IP Section 2323 Victory Avenue Suite 700 Dallas, TX 75219