Ex Parte 6584037 et al

Board of Patent Appeals and Interferences

Jan 27, 2012

95001154 (B.P.A.I. Jan. 27, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,154 03/03/2009 6,584,037 8963.002.RXUS00 7630
22852 7590 01/27/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
01/27/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Inter Partes
RAMBUS, INC.
Patent Owner

v.

SAMSUNG ELECTRONICS, CO., LTD. and
MICRON TECHNOLOGY INC.
Requestors
____________

Appeal 2012-000142
Reexamination Control Nos. 95/001,108 & 95/001,154
United States Patent 6,584,037 B2
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037

This proceeding arose out of separate third party requests by Samsung
Electronics Co., Ltd, and Micron Technology, Inc., for inter partes
reexaminations of U.S. patent 6,584,037 B2 to Farmwald et al., Memory
Device Which Samples Data After an Amount of Time Transpires(June 24,
2003) (claiming priority to April 18, 1990) assigned to Rambus, Inc. The
USPTO granted and subsequently merged the two requests, respectively
assigned Reexamination Control Nos. 95/001,108 and 95/001,154. (See
Decision, Sua Sponte, to Merge Reexamination Proceedings, July 21, 2009.)
Requestor Samsung Electronics, Co., Ltd. has not filed a brief in this
proceeding.
Requestor Micron appeals from the Examiner’s decision in the Right
of Appeal Notice (RAN) confirming claim 34. (Micron App. Br. 3.)
Rambus filed a responsive brief supporting the Examiner’s decision. (See
Rambus Resp. Br. 1.)
Micron also filed a rebuttal brief. (Micron Reb. Br.) The Examiner’s
Answer relies on the RAN, incorporating it by reference.
We have jurisdiction under 35 U.S.C. §§ 134(b) and 315.
We REVERSE the Examiner’s decision confirming claim 34.

STATEMENT OF THE CASE
Appellant Micron and Respondent Rambus refer to several related
judicial and other proceedings including inter partes and ex parte
reexaminations, International Trade Commission proceedings, and Federal
District Court and Circuit Court proceedings in their briefs. An oral hearing
of this appeal transpired on January 18, 2012 and was subsequently
transcribed.
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
3
MICRON’s APPEAL
Claim
Claim 34 on appeal by Micron follows:
34. A method of operation of a synchronous dynamic random access
memory device, wherein the method comprises:
sampling an operation code synchronously with respect to an external
clock signal, wherein the operation code specifies that the
memory device sample data to be written into a plurality of
dynamic memory cells, and wherein the operation code further
specifies that the memory device precharge a plurality of sense
amplifers;

sampling the data, in response to the operation code, after a
delay transpires

sampling address information to identify a subset of the
plurality of dynamic memory cells;

writing the data to the subset of the plurality of dynamic
memory cells using the plurality of sense amplifiers; and

precharging the plurality of sense amplifiers in response to the
operation code, wherein the plurality of sense amplifiers is
precharge automatically after the data is written.

Rejections
The Examiner refused to maintain the following rejections of claim 34
appealed by Micron.

Claim 34 as anticipated by the JEDEC Standard.1

1 Joint Electronic Device Engineering Counsel (JEDEC) Standard No. 21-C,
Revision 9 (1999).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
4
Claim 34 as obvious based on Bennett,2 and Wicklund,3 or Bowater4
Claim 34 as obvious based on Park and the JEDEC Standard.5

Introduction
Micron’s Appeal and Rebuttal Brief show Examiner error in the
refusal to maintain the Bennett based obviousness rejections, but not in the
refusal to maintain the Park and JEDEC based rejections, which turn on
priority. The portions of Micron’s Brief and Rebuttal Brief discussing the
Bennett-based obviousness rejection are hereby incorporated by reference
and adopted, as are the portion of Rambus’s Brief discussing the priority
issue. The findings in the RAN supporting the decision here are also
adopted.
Factual Findings
Background Definition
D. A “DRAM” definition follows:
A volatile store in which the fundamental storage devices are
capacitors arranged in matrix formation. Associated with each capacitor are
field-effect transistors which act as switches when data is put into the store
or withdrawn from it. To prevent loss of data as the capacitors discharge
through the inevitable leakage paths, their charges are regularly ‘topped up’
— a process known as refreshing. Despite the need for refreshing the
dynamic RAM is simpler, more compact and cheaper than a static RAM
and, although its speed is lower, is more widely used.

2 Bennett et al., Patent No. 4,734,909 (March 1988).
3 Wicklund et al., U.S. Patent No. 5,159,676 (Oct. 27, 1992, effective filing
Dec. 5, 1988).
4 Bowater, U.S. Patent No. 5,301,278 (Apr. 5, l994, effective filing Apr. 29,
1988).
5 Park et al., US 5,590,086 (Dec. 31, 1996, effective filing Oct. 1993).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
5
Newnes Dictionary of Electronics, Newnes (1999) at
http://www.credoreference.com/entry/bhelec/dynamic_random_access_mem
ory_dram (last visited Oct. 20, 2011) (emphasis added).
Farmwald ‘037
F1. The ‘037 patent describes normal and page access mode control
for DRAMS, with page mode providing the fastest access:
One such access mode determines whether the access is page
mode or normal RAS access. In normal mode (in conventional
DRAMS and in this invention), the DRAM column sense amps
or latches have been precharged to a value intermediate
between logical 0 and 1. This precharging allows access to a
row in the RAM to begin as soon as the access request for
either inputs (writes or outputs (reads) is received and allows
the column sense amps to sense data quickly. In page mode
(both conventional and in this invention), the DRAM holds the
data in the column sense amps or latches from previous read or
write operation. If a subsequent request to access data is
directed to the same row, the DRAM does not need to wait for
the data to be sensed (it has been sensed already) and access
time for this data is much shorter than the normal access time.
(Col. 10, ll. 23-38.)
F2. If data is not in a selected row during a page mode, the access
time becomes longer than the page mode access time because the system
must wait for the DRAM sense amps to precharge before latching in a new
value (the next row) and shifting to the normal mode access. (Col. 10, ll. 40-
43; ll. 56-64.) While the lines are kept open for page mode accesses, the
system can precharge after a page mode access. (Col. 10, ll. 47-55.)
Bennett
B1. Bennett discloses Verasatile Bus Interfaces as VLSIC (very large
scale integrated circuit) user devices and interfaces “upon the same chip
substrate” (col. 12, l. 31) with such a user device including memory (col. 39,
ll. 59-61). (Col. 12, ll. 14-38; col. 14, ll. 19-24; col. 35, ll. 59-68; col. 66, l.
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
6
9 - col. 67, l. 18.) Bennett’s chips have up to 120 pins. (Col. 9, ll. 60-61.)
Bennett also discloses different memory types as fast or slow with the
memory having 16, 24, or 32 pins or bits. (Col. 92, ll. 15-42; col. 94, ll. 24-
36) Figure 38 shows “memory device[s]” connected to a bus. (Col. 97, ll.
8-10).
B2. Bennett discloses synchronous clocked communication between
bused VLSIC chips, noting that synchronous communication is more
efficient that asynchronous communication. (Col. 66, l. 9 – col 67, l.18.)
B3. Figures 32 and 33 represent memory write operations using data
on 16 pins and 16 other pins for arbitration and slave ID. (See col. 93, l. 12
to col. 94, l. 56.)
B4. Bennett discloses multiple functions in a memory write code.
(See Bennett Fig. 34 (read-modify-write code signifying multiple
functions).)
Wicklund
W1. “At the present time, the most popular form of read/write
memory is the semiconductor DRAM . . . . because it offers the best
available combination of density, performance, and price, but it does have
some disadvantages.” (Col. 1, ll. 36-42.) The disadvantages include
complex multiplexing circuitry to refresh the DRAM. That is, since the
DRAM memory is based on capacitor charge which dissipates over time, the
charge must be periodically refreshed by addressing and accessing rows and
columns of the capacitors. (See col. 1, ll. 42-49, col. 2, ll. 42-49.)
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
7
Refreshing (precharging) also occurs after a normal read or write (i.e.,
during a non-page mode). (Col. 3, ll. 45-54; col. 5, ll. 31-34.)6
Another device, a SRAM (Static Random Access Memory), is ten
times faster, but not as dense as a DRAM, and more complex and expensive.
(Col. 2, ll. 18-24.)
W2. The page mode, in which a row (page) in a DRAM is accessed,
is faster than the standard or normal mode. There is a limit to how long the
device can be in page mode, in which a RAS (row address strobe) signal is
kept low to access a row. (Col. 1, ll. 50-62, col. 2, ll. 41-42.) Because
“DRAMs need to be refreshed at regular intervals, the page mode may need
to be interrupted to perform a refresh cycle.” (Col. 2, ll. 43-45.)
W3. Wicklund’s system “automatically switch[es] between page
mode and non-page mode of DRAM operation depending on some
prediction of whether the next access will be on the same page or on another
page.” (Col. 2, ll. 57-61.) Page mode is only faster than the normal
(standard) mode if successive memory accesses are in fact on the same row,
otherwise a page “miss” (col. 3, l. 3) time access penalty occurs. A page
miss requires taking RAS high and closing the currently open row before the
new address can be input, and then taking RAS low to access the different
row (as occurs in normal mode). (See col. 2, l. 40 to col. 3, l. 10; col. 3, ll.
44-54; col. 5, ll. 31-34; col. 6, ll. 12-19.)7 External or controller timers can

6 The Examiner (RAN 25, 41, 42), Micron (Micron App. Br. 9), and Rambus
(Rambus Resp. Br. 15) describe Wicklund’s system as precharging – in
other words, refreshing and precharging are interpreted to be the same or
similar function for purposes of this appeal.
7 According to Rambus, Wicklund’s system “attempt[s] to guess whether
[the system] should keep a row open or close it”- i.e., stay in page mode and
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
8
be employed to track the proper page mode time before refreshing is
required. (Col. 3, ll. 39-43.)
W4. Wicklund’s prediction algorithm (which saves time if accurate)
is based on the history of past page hits or misses. After the prediction, the
memory controller compares the current address requested for a read or
write with the previous requested address and shifts to the new row (in
normal mode) or stays on the current row (in page mode), regardless of the
prediction. The prediction algorithms can be modified or controlled by the
operating system software. The controller can be integrated, and Wicklund
notes that some CPUs control refresh. (Col. 3, l. 12 to col. 4, l.25.)
Analysis
Bennett with Wicklund or Bowater
Micron’s contention that Bennett discloses synchronous memory
chips and that the combination of Bennett and Wicklund or Bowater renders
obvious using DRAM chips is persuasive. (See Micron App. Br. 5-13;
Micron Reply Br. 9-16) (adopted and incorporated herein by reference).
Bennett discloses synchronous memory chips. (B1, B2). DRAMs
were a well-known, if not dominant, form of a memory chip device at the
time of the invention. (See e.g. Micron App. Br. 6 (citing Wicklund) n. 5
(citing iRAM at 1-1);8 accord W1.) For example, Wicklund shows that
DRAMs were the most popular form of memory chips at the time of the
invention. (W1.) Neither Rambus, nor the Examiner, dispute that DRAMs
were ubiquitous memory chips. Micron also persuasively shows that

not precharge or get out of page mode which closes the current row and
precharges it. (Rambus Resp. Br. 15.)
8 Memory Components Handbook, Intel. Corp., Ch. 1, 3 (1985).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
9
Bennett teaches synchronous memory chips receiving op codes. (Micron
Reb. Br. 9-13.)
The Examiner contends that Micron did not show the obviousness of a
precharge indication together with a write indication in the same claimed op
code. But the Examiner finds that “Bennett discloses controlling memory
devices using operation codes. Wicklund discloses that a memory controller
should decide whether or not to automatically precharge an associated
memory chip after a current access in order to improve the speed of memory
operation.” (RAN 41.) Rambus and Micron agree with this
characterization of Wicklund, with Rambus arguing that, “[a]fter the data is
input or output, the row is then closed and the internal circuitry is
precharged.” (Rambus Resp. Br. 15.)9 In other words, Micron’s contention
that prior art systems typically precharge DRAMs in the non-page (normal)
mode after a read or write operation (Micron App. Br. 7-9) is not in dispute.
(See D, F1, F2, W2-W4.) These findings, showing that the precharge and
write functions (and their signals) are intimately coupled together in prior art
systems, support the obviousness of the disputed limitations of claim 34
requiring the signals to be in a single op code.(see e.g. F1, W2, W3).
Further, Bennett discloses controlling memory chips using multiple
functions in a write code. (See B1-B4.) In other words, Bennett discloses
banding together related write signals in one code. (B4.) As discussed, two
typical well-known modes for DRAM writes existed at the time of the
invention, a normal mode after which a DRAM row closes and a precharge

9 It appears, based on these and other arguments and the evidence, that
closing the row by taking RAS high causes precharging of the DRAM
circuits. (Accord W3.)
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
10
occurs, and a page mode, which typically did not involve a precharge during
that mode. (See F1 (discussing conventional DRAMs); W1-W4.)
Based on the foregoing discussion, it would have been obvious to
place the prior art coupled write and precharge signals as described in the
‘037 patent or Wicklund into Bennett’s op code which carries related write
signals together, so that the modified chips of Bennett (DRAMs) can be
precharged after a write function as was typically required in DRAMs.
Putting Wicklund’s coupled precharge and write DRAM control signals into
Bennett’s synchronous multiple function write control op code amounts to
no “more than the predictable use of prior art elements according to their
established functions.” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417
(2007).
Additionally, Wicklund also teaches that if a DRAM is in page mode
for too long, as determined by a counter, it must be closed and refreshed
(i.e., precharged). (W2, W3.) Therefore, Wicklund also suggests that if the
row address request has matched the previous request during page mode for
several consecutive write cycles as determined by the counter (and/or is
predicted to match for a another write cycle), the system CPU or controller
should send a signal to close the row after the current write to institute a
precharge after that write (interrupting the page mode). (See W1-W4.)
In other words, under an alternative analysis, it also would have been
obvious to send a precharge signal with a write signal in an op code, before
writing to the currently open DRAM row in a page mode, but after
determining, pursuant to a clock, that the page mode time is about to expire,
as Wicklund (W2-W4) and Bowater (see Bowater, col. 7, l.55 to col. 8, l. 9)
suggest. (See Micron App. Br. 12-13 (also relying on the ‘037 patent’s
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
11
admissions describing prior art DRAM precharges (see F1).) As Micron
contends, employing Bowater’s (or Wicklund’s) counter in Bennett to
indicate when to send a precharge signal with Bennett’s write op code would
have been obvious, in order to ensure that a DRAM row in page mode is not
kept open too long. (See Micron Reb. Br. 15.)
And if the row does not match in a current page mode, Wicklund
teaches switching to the non-page mode which closes the row, writes data to
the newly requested row, and automatically precharges, suggesting another
reason for sending a precharge signal with the write signal to the DRAM
(i.e., so precharge can occur after writing as normally occurs in non-page
mode). (See F1, W2-W4; Micron App. Br. 10-11; Micron Rep. Br. 14-15.)
The Examiner finds that Wicklund does not suggest sending the write
and precharge indications together as claim 34 requires because in
Wicklund, “precharging is not determined/invoked automatically after the
writing of data but before,” and Wicklund “precharges prior to the writing of
data.” (RAN 43.) The Examiner also finds that “‘if the new address is
different form [sic from] the current row address then the current page mode
will have to be terminated and a new cycle started.’” (Id. (quoting
Wicklund).)
The Examiner’s rationale for nonobviousness based on these findings
appears to be that row closing causes a precharge on the current row, and
then writing on the next row occurs. (See RAN 42-43.) While the findings
underlying the rationale appear to be factually supported to an extent, the
findings support obviousness, because the rationale does not consider that
the controller signals a precharge on the DRAMs after writing in the normal
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
12
mode. Also, the controller signals a precharge after shifting from the page
mode to the normal mode and writing to a new row pursuant to the shift.
The implicit coupling of writing and precharging together for the
current or next row as the prior art teaches, suggests the claim limitation in
dispute. DRAMs typically have to be, and were, refreshed (precharged)
after a write operation, pursuant to control signals, suggesting sending the
two signals in Bennett’s multiple function op code to achieve the same result
of writing and then precharging.
Rambus also contends, using somewhat “truncated arguments,” see
In re Lovin, 652 F.3d 1349, 1353 (Fed. Cir. 2011), that Bennett does not
disclose other claimed features of claims 34. Micron’s responses are
persuasive where the Examiner does not disagree with Micron’s contentions
as to any remaining claim terms and focuses on the reasons discussed supra.
Of course, on remand, the Examiner has the discretion to sort out any
remaining contentions and make specific findings. But Micron shows that
on this record, the Examiner erred by failing to maintain the rejection of
claim 34 based on the conclusion that it would not have been obvious to
employ a well-known precharge signal in a write op code signal, when such
a precharge normally followed a write in the prior art systems.
Based on the foregoing discussion, Micron demonstrates that the
Examiner erred in refusing to maintain the obviousness rejection of claim 34
based on Bennett and Wicklund or Bowater.
Secondary Considerations
Rambus relies on secondary considerations of nonobviousness.
(Rambus Resp. Br. 18-20.) Micron contends that Rambus has failed to
establish a nexus or show that its secondary evidence is commensurate in
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
13
scope with the claim 34. (See Micron Reb. Br. 16.) For example, Micron
contends that Rambus provided the same evidence in ten related
reexamination proceedings. (Id.) Micron’s contentions are supported at
least because Rambus directs attention to the same or similar evidence relied
upon in the reexamination proceeding addressed in the Board’s related
decision (App. No. 2011-009644), which is adopted and incorporated herein
by reference to the extent it applies to the similar arguments and evidence.
Rambus does argue that the op code as recited in claim 34 frees up
bandwith and satisfies a longfelt need. (Rambus Resp. Br. 19-10.) But
Rambus fails to tie persuasive evidence to this claimed feature in
combination with other well-known reasons to support the contentions of
unobviousness. For example, any success would have been due partly to
DRAMs themselves, the most popular chip at the time of the invention,
thereby showing a lack of nexus.10 (W1.) Synchronous memory chips were
also known. (B1, B2.) Precharging was also well-known to occur after
writing and required by DRAM devices for speed. (See F1; W1-W4.)
Rambus fails to present evidence that precharging in combination
with other claimed features, and in the absence of a multiplexed bus, and
other touted features, solves a longfelt need, or otherwise demonstrates or
outweighs obviousness by way of the alleged secondary considerations. As
another example, Rambus mentions licensing under the “Farmwald Family,”

10 See Tokai Corp. v. Easton Enters., Inc., 632 F.3d 1358, 1369 (Fed. Cir.
2011) (“If commercial success is due to an element in the prior art, no nexus
exists.”); Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299, 1312 (Fed.
Cir. 2006) (“[I]f the feature that creates the commercial success was known
in the prior art, the success is not pertinent.”).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
14
but that “Family” may or may not require, or be limited to, the combination
recited in claim 34. (See Rambus Resp. Br. 19.)
And as discussed in the related ‘9664 decision, any secondary
considerations likely flow from a variety of several unclaimed features
touted here or in other Rambus proceedings or patents, such as an internal
DLL (delay locked loop), eight data lines, small DRAM sizes, multiplexed
buses, packetized control, identification control mechanisms, doubly
terminated clocks, and time access schemes. See also Rambus Inc. v.
Infineon Technologies AG, 318 F.3d 1081, 1095 (Fed. Cir. 2003) (“The
present invention is designed to provide a high speed, multiplexed bus’”
(quoting Rambus’s related ‘918 patent, col. 5, ll. 36-46), but “the
prosecution history shows that a multiplexing bus is only one of many
inventions disclosed in the ‘898 application.”)11
Based on the foregoing discussion, Rambus fails to direct attention to
persuasive countervailing secondary considerations outweighing Micron’s
showing of obviousness based on Bennett and Wicklund or Bowater.
Priority and Anticipation by JEDEC and Park
Micron asserts that claim 34 does not recite a multiplexed bus, and as
such, is not originally supported back to the (first-filed) ‘898 application
having a filing date of April, 1990 because the claim is too broad; i.e., too
broad absent a recitation to a multiplexed bus which the ‘037 patent touts as
important. Based on this contention, Micron asserts that claim 34 is not

11 See 318 F.3d at 1084-86 (finding that the written descriptions of each of
four related Rambus patents, 5,954,804; 5,953,263; 6,034,918; and
6,032,214, are substantially identical to the written description of the
07/510,898 application to which they, and the ‘037 patent here, all claim
continuity).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
15
entitled to a filing date prior to the ‘037 patent’s application filing date of
February 4, 2002, and is therefore anticipated by the JEDEC and Park
references which antedate the 2002 date. (See Micron App. Br. 3, 23, 14-
28).) In turn, Rambus relies, inter alia, on Infineon, 318 F.3d at 1094, to
show that claim 34 does not require a multiplex bus and is therefore
originally supported. (Rambus Resp. Br. 8.)12
In rebuttal, Micron asserts that Infineon was decided before Phillips v.
AWH Corp., 415 F.3d, 1303, 1317 (Fed. Circ. 2005) (en banc), and Infineon
was therefore “decided under the wrong legal standard.” (Micron Reb.
Br. 7.) Micron also asserts that Infineon was “directed to issues of claim
construction, not to the issue of whether specific claims were entitled to an
earlier priority date.” (Id.)
Micron’s contentions are unconvincing to show that Infineon was
wrongly decided or would somehow require reaching a different result based
on a written description priority analysis as opposed to its claim construction
analysis. Infineon held that the ordinary term “bus” could not be read
restrictively as a “multiplexed bus” even though the patentee described the
“present invention” in terms of a “multiplexed bus” in isolated portions of
the specification because “the remainder of the specification and the

12 Rambus’s contention that Micron lacks standing to raise these issues
which were originally proposed by Requestor Samsung (Rambus Resp. Br.
1-3) is not persuasive for the reasons articulated by the Board’s April 15,
2011 Decision on Petition in Merged Reexaminations 95/000183 and
95/001,112 (Acting Chief APJ Moore) (reasoning inter alia that Micron’s
appeal is an appeal of the Examiner’s position on Samsung’s request and
noting that appeals in reexaminations are from any final decision favorable
to patentability) (merged reexaminations culminating in Appeal No. 2011-
008431).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
16
prosecution history shows that Rambus did not clearly disclaim or disavow
such claim scope in this case.” Infineon, 318 F.3d at 1094-95. In other
words, Infineon relied on the specification and prosecution history, as
opposed to relying unnecessarily on “much diminished” precedent involving
pre-Phillips “dictionary” cases, contrary to Micron’s arguments. (See
Micron Reb. Br. 7.)
Despite Infineon, Micron maintains that claim 34 can be described as
a “multiplexed bus-less” claim which is “neutral regarding the presence or
absence of an interface to a multiplexed bus” and therefore violates the
written description requirement since the ‘898 patent application touts the
importance of a multiplexed bus and disparages prior art generic bus
inventions. (See Micron App. Br. 23.) Micron supports the theory, which in
essence, amounts to a scope of enablement attack on claim 34, by relying,
inter alia, on LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d
1336, 1344 (Fed. Cir. 2005) (generic seamless DWT claim too broad absent
an udapted sums limitation). (Micron App. Br. 15-16.) Micron relies on a
“key factor” in LizardTech as embodied in an analogy there to an inventor
who describes a fuel-efficient engine in such detail that it would not
necessarily support “a broad claim to every possible type of fuel-efficient
engine.” (Id. at 16 (quoting LizardTech at 1346).) As another example,
Micron reasons that claim 34 is analogous to the “spikeless” valve claimed
addressed in ICU Medical. (Micron App. Br, 22 (citing ICU Medical, Inc. v.
Alaris Medical Systems, Inc., 558 F.3d 1368 (Fed. Cir. 2009).
But the gravamen of these arguments is that the ‘037 patent’s
inventors were not in possession of claims not requiring a multiplexed bus
scheme. However, Infineon’s claim construction analysis, at the minimum,
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
17
implies that skilled artisans were in possession of generic bus claims. See
Infineon, 318 F.3d at 1094-95 (noting that “multiplexing is not a requirement
in all of Rambus’s claims” and that the PTO issued a restriction to a
multiplexing group and a latency group, that “the PTO demonstrated an
understanding of “bus” that is not limited to a multiplexing bus”).
Rambus supports the possession of generic bus claims by pointing out
that original claims 73 and 91 in the first-filed ‘898 application recite a
generic bus. (Rambus Resp. Br. 8.) As Rambus also points out, and as the
discussion of secondary considerations supra indicates, skilled artisans
would have understood that other important touted features in Rambus’s
disclosure, including synchronous operation and writing a block of a group
of data, could have been practiced on generic buses without multiplexing.
(See id. at 6-8.) Accord Infineon, 318 F.3d at 1095 (noting that “a
multiplexing bus is only one of many inventions disclosed in the ‘898
application”); cf. Crown Packaging Tech. Inc. v. Ball Metal Beverage
Container Corp., 635 F.3d 1373, 1382-84 (Fed. Cir. 2011) (district court
erred in finding lack of written description in generic claims where the
application discloses separate solutions to related problems).
Claim 34 at issue here requires synchronous writing “into a plurality
of memory cells” and op code precharge information. Skilled artisans would
have recognized that these touted features could have been practiced on
known buses, whether multiplexed or not, especially since op codes,
synchronous writing, and precharging operations were well known before
the invention. The lack of multiplexing would have been much simpler than
a multiplexing scheme. Cf. Hynix Semiconductor Inc. v. Rambus Inc., 645
F.3d 1336, 1351-53 (2011) (holding that evidence supported jury verdict of
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
18
written description for similar Rambus claims where “the supposed genus
consists of only two species, a multiplexed bus and a non-multiplexed bus”).
Also, Micron’s spikeless valve analogy is not entirely apt here
because valves were recited in the ICU Medical claims, but in the ‘037
patent claim 34, a bus is not recited, so ICU Medical does not dictate that
claim 34 must support any type of bus. But even if claim 34 implicitly
requires a bus, Rambus, the Examiner (see Office Action 3-7 (Feb. 13,
2009)), the Infineon claim construction, and the Hynix Semiconductor
written description analysis, shows that on this record, the inventors
originally possessed inventions directed to a generic bus scheme.
Based on the foregoing discussion, Micron has not shown error in the
Examiner’s finding that claim 34 has original written description support as
necessary to antedate Park or JEDEC as prior art anticipation references.
CONCLUSION
Micron demonstrated that the Examiner erred in deciding not to
maintain the obvious rejections of claim 34 based on Bennett and either
Bowater or Wicklund. Micron did not demonstrate that the Examiner erred
in deciding not to maintain the anticipation rejections of claim 34 based on
Park or JEDEC.
DECISION
The Examiner’s decision not to maintain the rejection of claim 34 is
reversed.13
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

13 See 37 C.F.R. § 41.77(b) (denominating a reversal of a refusal to reject as
a new ground of rejection).
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037
19

REVERSED

cu

cc:
Third Party Requester Samsung
HAYNES AND BOONE, LLP IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219

Third Party Requester Micron
NOVAK, DRUCE & QUIGG, LLP
(NDQ REEXAMINATION GROUP)
1000 LOUISIANA STREET, 53RD FLOOR
HOUSTON, TX 77002