Ex Parte 6433419 et al

Patent Trial and Appeal Board

Nov 17, 2014

95000227 (P.T.A.B. Nov. 17, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,227 02/09/2007 6433419 TESSERA 3.5-018CCIIDC 6504
530 7590 11/17/2014
LERNER, DAVID, LITTENBERG,
KRUMHOLZ & MENTLIK
600 SOUTH AVENUE WEST
WESTFIELD, NJ 07090
EXAMINER
NGUYEN, MINH T
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/17/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

SILICONWARE PRECISION INDUSTRIES CO., LTD and
SILICONWARE, U.S.A., INC.
Requester, Cross-Appellant, and Respondent

v.

TESSERA, INC.
Patent Owner, Appellant, and Respondent
____________

Appeal 2014-002712
Reexamination Control 95/000,227
Technology Center 3900
Patent 6,433,419 B2
____________

Before DAVID M. KOHUT, ERIC B. CHEN, and IRVIN E. BRANCH,
Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON EXAMINER’S DETERMINATION
UNDER 37 C.F.R. § 41.77(d)

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This is a decision under 37 C.F.R. § 41.77 (f) on the Examiner’s
determination under 37 C.F.R § 41.77(d) maintaining the rejections of
claims 1–19, 22–24, and 27. We have jurisdiction under 35 U.S.C. §§ 6(b),
134, and 315. We reverse.

STATEMENT OF THE CASE
In a prior Decision on Appeal, entered December 26, 2012, another
panel of this Board reversed the Examiner’s decision favorable to the
patentability of claims 1–19, 22–24, and 27 under 35 U.S.C. §§ 102(e) and
103(a) as proposed and appealed by Requesters Siliconware Precision
Industries Co., Ltd. and Siliconware USA, Inc. These rejections were
entered as a new ground of rejection pursuant to our authority under 37
C.F.R. § 41.77(b), as follows:
1. Claims 1–14, 16–19, 22–24, and 27 are rejected under 35 U.S.C.
§ 102(e) as anticipated by Mullen (US 5,241,133; Aug. 31, 1993).
2. Claim 15 is rejected under 35 U.S.C. § 103(a) as obvious over
Mullen and White (US 4,601,526; July 22, 1986).
Patent Owner Tessera, Inc. submitted a Request to reopen prosecution
before the Examiner under 37 C.F.R. § 41.77(b)(1), dated February 21, 2013
(“Requester § 41.77(c) Comments”), accompanied by arguments and
additional evidence in the form of a Declaration under 37 C.F.R. § 1.131 of
Craig Mitchell, Senior Vice President of Tessera, Inc. (“Tessera
Declaration”), accompanied by numerous supporting documents.
In response to Patent Owner’s Request, Requesters Siliconware
Precision Industries Co., Ltd. and Siliconware USA, Inc. filed written
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comments to Patent Owner Tessera, Inc., dated March 21, 2013. Requesters
Siliconware Precision Industries Co., Ltd. and Siliconware USA, Inc.
subsequently filed a notice of withdrawal from the inter partes
reexamination proceeding, dated May 9, 2013.
The Examiner determined that claims 1–19, 22–24, and 27 were
unpatentable, and issued a Determination under 37 C.F.R. § 41.77(d), dated
September 25, 2013 (“Determination”).
Patent Owner contends that the Examiner’s Determination
maintaining these rejections is erroneous for various reasons, and has
submitted Requester Comments on the Examiner’s Determination, dated
October 25, 2013 (“Requester § 41.77(e) Comments”).
Claims 1 and 3 are exemplary, with disputed limitations in italics:
1. A semiconductor assembly comprising:
a) a semiconductor chip having a front surface, a rear
surface and contacts on said front surface, said semiconductor chip
having a coefficient of thermal expansion;
b) a substrate adapted to physically support the chip and
electrically interconnect the chip with other elements of a circuit, said
substrate having a set of contact pads thereon, said substrate having a
coefficient of thermal expansion, said semiconductor chip overlying
said substrate so that said chip overlies at least some of said contact
pads of said set and so that said rear surface of said chip faces toward
said substrate and said contact pads;
c) a backing element having electrically conductive
terminals and electrically conductive lead portions electrically
connected to said terminals and to said contacts on said chip, said
backing element having a central region aligned with said chip and
disposed between said rear surface of said chip and said substrate, said
terminals of said backing element being bonded to said contact pads
on said substrate, at least some of said terminals of said backing
element being disposed in said central region of said backing element
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and being movable with respect to the chip to compensate for
differential thermal expansion of the chip and substrate.

3. A semiconductor assembly comprising:
a) a semiconductor chip having a front surface, a rear
surface and contacts on said front surface, said semiconductor chip
having a coefficient of thermal expansion;
b) a substrate adapted to physically support the chip and
electrically interconnect the chip with other elements of a circuit, said
substrate having a set of contact pads thereon, said substrate having a
coefficient of thermal expansion, said semiconductor chip overlying
said substrate so that said chip overlies at least some of said contact
pads of said set and so that said rear surface of said chip faces toward
said substrate and said contact pads;
c) a backing element having terminals and having
electrically conductive lead portions connected to said terminals, said
backing element having a central region aligned with said chip and
disposed between said rear surface of said chip and said substrate, at
least some of said terminals of said backing element being disposed in
said central region, and bonded to said contact pads on said substrate;
and
d) a compliant layer disposed between said rear surface of
said chip and said backing element, said compliant layer facilitating
movement of said terminals in said central region of said backing
element with respect to the chip to compensate for differential thermal
expansion of the chip and substrate.

ANALYSIS
Written Description Support
Claims 1, 2, 5, and 6
The Examiner found that priority U.S. Patent No. 5,148,265 (the
“’265 patent”), filed March 21, 1991, does not provide written description
support for the limitation “a backing element . . . being movable with respect
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to the chip to compensate for differential thermal expansion of the chip and
substrate,” as recited in claims 1, 2, 5, and 6. (Determination 4, 6.) In
particular, the Examiner found that “[t]here is no teaching that this
configuration [in Figure 13 and 14] could be used as a stand-alone package
without an interposer” because “[t]he backing element 660 . . . is only used
to allow for a stacked configuration” (Determination 6) and “[t]he ’265
Patent does not describe or teach anything about the backing element 660
itself – such as elastic modulus, flexibility, compliance, or other material
properties – that potentially could provide for the claimed movement”
(Determination 7–8). We do not agree with the Examiner’s determination.
In the “Background of the Invention” section, the ’265 patent
discloses that an improved semiconductor chip assembly features “a
semiconductor chip [that] can be connected to a substrate using a sheet-like,
and preferably flexible, interposer” (col. 3, ll. 62–66) and “[b]ecause the
terminals are movable relative to the contacts on the chip, the arrangements
. . . provide excellent resistance to thermal cycling” (col. 4, ll. 9–12).
Furthermore, “[i]n a variant of the present invention, the securement means
may include a backing element having a top surface overlying the rear
surface of the chip, the backing element extending outwardly beyond at least
some of the edges of the chip” (emphasis added). (Col. 6, ll. 38-43.) Thus,
in view of the disclosure in the ’265 patent that movability of terminals with
respect to the chip results provides resistance to thermal cycling and a chip
overlying a backing element, the ’265 patent provides an implicit disclosure
of a “compliant layer” between the chip and the backing element.
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Accordingly, we disagree with the Examiner’s finding that the ’265
patent does not provide written description support for the limitation “a
backing element . . . being movable with respect to the chip to compensate
for differential thermal expansion of the chip and substrate,” as recited in
claims 1, 2, 5, and 6.

Claims 3, 4, 7, and 8
The Examiner further found that the ’265 patent does not provide
written description support for the limitation “a compliant layer disposed
between said rear surface of said chip and said backing element,” as recited
in claims 3, 4, 7, and 8. (Determination 7–8.) In particular, the Examiner
found that “[t]he ’265 Patent does not describe a compliant layer between
the chip and the backing element” and “[t]he ’265 Patent simply states that
the ‘backing element 660 abuts the rear face 623 of chip 620.’”
(Determination 7.) We do not agree with the Examiner’s determination.
Figure 13 of the ’265 patent, which illustrates a perspective view of a
semiconductor chip assembly, including a chip 620 having a front
surface 622 and a rear surface 623, and an interposer 636 that overlies the
chip front surface 622 (col. 18, ll. 37–45), is reproduced below:
App
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7
sheetlike b
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of said chip”) overlies the interposer 636 of the middle chip assembly (i.e.,
the claimed “compliant layer”) and the backing element 660 of the middle
chip assembly (i.e., the claimed “backing element”). Thus, Figure 14 of the
’265 patent provides support for the limitation “a compliant layer disposed
between said rear surface of said chip and said backing element.”
Accordingly, we disagree with the Examiner’s finding that the ’265
patent does not provide written description support for the limitation “a
compliant layer disposed between said rear surface of said chip and said
backing element,” as recited in claims 3, 4, 7, and 8.

Conception
The Examiner found that the laboratory notebook of inventors Igor
Khandros and Thomas DiStefano provided insufficient evidence to support
conception of the invention prior to December 21, 1990, the effective filing
date of Mullen. (Determination 23–25.) In particular, the Examiner found
that “there is no support for a conception date of ‘June 10, 1990’ for any
of the claims of the ’419 Patent” and “Dr. Khandros’s notebook is filled with
many ideas and drawings for things other than chip packages, including
structures of printed wiring boards and manufacturing processes.”
(Determination 23.) Furthermore, the Examiner found that “the ‘June 10,
1990’ drawing in Dr. Khandros’ notebook has nothing to do with the claims
of the ’419 Patent’” and that “[t]he notebook entry of June 10, 1990 is titled
‘Ultrasonic Bonding of Composites based on Thermoplastic Polymers’.”
(Id.) We do not agree with the Examiner’s determination.
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Patent Owner has provided a table, in which the elements of
independent claim 1 are cross-referenced to the supporting evidence,
including the inventors’ notebook (Tessera Declaration, Annex 1).
(Requester § 41.77(e) Comments 12–19; see also Requester § 41.77(c)
Comments 3–10.) In particular, the relevant pages of the inventor’s
notebook, dated June 1, 1990, states that “[t]he problem with FLIP-CHIP
joining is that solder balls/joints must accomodate [sic] the thermal stress
due to TCE [thermal coefficient expansion] mismatch between silicon chip
and the substrate.” (P. TESS070651.) The inventors’ notebook further states
that a “[d]ecal structure [is] overlayed on top of the chip . . . . The i/o pads
on the chip are connected with WB pads on the decal by a way of ball or
wedge WIREBONDING” (p. TESS070652) such that “[t]he chip is
decoupled from the substrate, and the thermal stresses simply buckle the
wires of the wirebond, without danger of failure of joints” (p. TESS070653).
Figure 3 of the inventors’ notebook is a perspective view of a semiconductor
chip (labeled “chip”) having contacts (labeled “chip i/o area pad”) with an
overlying backing element (labeled “DECAL”). Figure 3 further illustrates
that the backing element (labeled “DECAL”) has overlying terminals
(labeled “wirebond pad on DECAL”) and an electrically conductive lead
(labeled “Au or Ag wire bond”) that connects the contact on the chip with
the terminal on the backing element.
Accordingly, Patent Owner’s evidence in the form an inventors’
notebook provided sufficient evidence to support conception of the invention
prior to December 21, 1990, the effective filing date of Mullen.
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Thus, because Mullen is not available as prior art, we do not agree
with the Examiner that the rejection of claims 1–19, 22–24, and 27 under 35
U.S.C. §§ 102(e) and 103(a) should not be maintained.

DECISION
We reverse the Examiner’s decision to maintain the rejection of
claims 1–14, 16–19, 22–24, and 27 under 35 U.S.C. § 102(e) as anticipated
by Mullen.
We reverse the Examiner’s decision to maintain the rejection of
claim 15 under 35 U.S.C. § 103(a) as obvious over Mullen and White.
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.
This is a final decision. Parties to the proceeding seeking judicial
review of the decision must comply with the notice and service requirements
of 37 C.F.R. § 90.2.

REVERSED

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Patent 6,433,419 B2

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Patent Owner:

LERNER, DAVID, LITTENBERG,
KRUMHOLZ & MENTLIK
600 South Avenue West
Westfield, NJ 07090

Third Party Requester:

ORRICK, HERRINGTON & SUTCLIFFE, LLP
IP Prosecution Department
2050 Main Street, Suite 1100
Irvine, CA 92614