Ex Parte 6,324,120 et al

Board of Patent Appeals and Interferences

Jan 19, 2012

95000178 (B.P.A.I. Jan. 19, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,152 02/27/2009 6,324,120 8963.002.RXUS00 4649 22852 7590 01/19/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 01/19/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/000,178 10/06/2006 6,324,120 38512.4 8591 22852 7590 01/19/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 01/19/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Inter Partes RAMBUS, INC. Patent Owner v. SAMSUNG ELECTRONICS, CO., LTD. and MICRON TECHNOLOGY INC. Requestors ____________ Appeal 2011-009664 Reexamination Control Nos. 95/000,178 & 95/001,152 United States Patent 6,324,120 B2 Technology Center 3900 ____________ Before ALLEN R. MacDONALD, KARL D. EASTHOM, and STEPHEN C. SIU, Administrative Patent Judges. EASTHOM, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 This proceeding arose out of separate third party requests by Samsung Electronics Co., Ltd, and Micron Technology, Inc., for inter partes reexaminations of U.S. patent 6,324,120 B1 to Farmwald et al., Memory Device Having a Variable Output Length (Nov. 27, 2001) assigned to Rambus, Inc. The USPTO granted and subsequently merged the two requests, respectively assigned Reexamination Control Nos. 95/000,178 and 95/001,152. (See Decision, Sua Sponte, to Merge Reexamination Proceedings, July 21, 2009.) Requestor Samsung Electronics, Co., Ltd. has not filed a brief in this proceeding. Appellant, Patent Owner Rambus, appeals under 35 U.S.C. §§ 134(b) and 306 from the decision in the Examiner’s Right of Appeal Notice (RAN) rejecting claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 of the ‘120 patent. (Rambus App. Br. vii.) Respondent, Requestor Micron, filed a Responsive Brief disputing contentions by Rambus and supporting the Examiner’s decision. (Micron Resp. Br. 1-2.) The Examiner confirmed claims 5, 7, 12- 14, 17, 18, 20, and 26-39. (See RAN 2.) 1 Requestor Micron cross-appeals from the Examiner’s decision in the RAN confirming claims 26, 29, and 33. (Micron Cr. App. Br. 3.) Rambus filed a responsive brief opposing the cross-appeal and supporting the Examiner’s decision not to maintain these proposed rejections. (Rambus Resp. Br. 1-2.) 1 As Rambus points out, the RAN does not list claims 35-39 as confirmed but does not list them as rejected either. (Compare RAN 2 with Rambus App. Br. vii. n.3.) Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 3 Rambus and Micron also each filed rebuttal briefs. (Rambus Reb. Br.; Micron Reb. Br.) The Examiner’s Answer relies solely on the RAN, incorporating it by reference. We have jurisdiction under 35 U.S.C. §§ 134(b) and 315. We AFFIRM the adopted rejections of claims 1-4, 6, 8-11, 15, 16, 19, and 21-25, and REVERSE the Examiner’s decision confirming claims 26, 29, and 33. We decline to reach one of the proposed rejections which the Examiner maintained and two of the proposed rejections which the Examiner did not maintain. See 37 C.F.R. 41.77 (a) (“The Board . . . may affirm or reverse each decision of the examiner on all issues raised on each appealed claim . . . .”); cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding anticipation). STATEMENT OF THE CASE Appellant Rambus and Respondent Micron refer to several related judicial and other proceedings including inter partes and ex parte reexaminations, International Trade Commission proceedings, and Federal District Court and Circuit Court proceedings in their briefs. An oral hearing of this appeal and a related inter partes reexamination appeal (App. No. 2011-008431) involving the same parties transpired concurrently on Sept. 21, 2011 and was subsequently transcribed as one document. Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 4 RAMBUS’s APPEAL Claim Claim 1 on appeal by Rambus follows: 1. A method of operation of a synchronous memory device, wherein the memory device includes an array of memory cells, the method of operation comprises: receiving an external clock signal; receiving block size information, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code; sampling the first operation code synchronously with respect to the external clock signal wherein the first operation code instructs the memory device to perform a read operation; and outputting the amount of data in response to the first operation code. Rejections The Examiner maintained the following proposed rejections: Claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 under 35 U.S.C. 102(b) as anticipated based on iAPX. 2 Claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 under 35 U.S.C. 102(b) as anticipated based on Budde. 3 (See Rambus App. Br. 1-2.) 2 iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982). 3 Budde et al., U.S. 4,480,307 (Oct. 30, 1984). Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 5 Issue Rambus and Micron raise the issue of whether the Examiner erred in finding that the memory device recited in claim 1 reads on the memory module of iAPX. The iAPX Manual -Factual Findings A1. Figure 1-2 of the iAPX Manual follows: Figure 1-2 depicts a memory module comprising a memory storage array and a MCU (Memory Control Unit). “The storage arrays will typically be constructed with high-density dynamic RAM (DRAM) components.” The MCU requires a “modest amount of external logic . . . to interface the MCU to the storage array RAMs - - for simple configurations, as few as 12 external TTL packages are required.” (iAPX Manual 1-4.) The BIU (bus interface unit) works in conjunction with a GDP (general data processor) in a processor module. (iAPX 1-1 - 1-3; Fig. 1-2.) “The BIU is also responsible for arbitrating the usage of the memory bus.” Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 6 (iAPX 1-3.) It also “decides which memory bus(es) will be used to form the [memory bus] access.” (Id.) A2. The memory module constitutes “a memory confinement area.” (iAPX Manual 1-8, 3-2.) The MCU “interfaces memory storage arrays to the memory bus.” (iAPX Manual 1-4.) A3. A component level constitutes the lowest level of hardware in the system, an example of which is a RAM chip. A module comprises a group of interconnected components. (iAPX Manual 2-1.) The presence or absence of any module does not prevent communication between any other modules. (iAPX Manual 2-6.) Analysis Rambus’s arguments with respect to the iAPX module raise the same or similar issues as raised in at least two related appeals before the Board (App. No. 2011-008431 mentioned supra and App. No. 2010-011178). 4 The two patents involved in those appeals claim continuity back to the same application (App. No. 07/510,898) as the ‘120 patent under reexamination here and appear to have the same or substantially the same disclosures. 5 The findings and reasoning from those two related appeal decisions the findings of the Examiner and contentions of Micron on the record of the instant proceedings are adopted and incorporated by reference here. 4 The latter decision is now on appeal to the Federal Circuit (Fed. Appeal No. 2011-1247). 5 Accord Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1084-86 (Fed. Cir. 2003) (finding that the written descriptions of each of four related Rambus patents, 5,954,804; 5,953,263; 6,034,918; and 6,032,214, are substantially identical to the written description of the 5,243,703 patent and the 07/510,898 application to which they all claim continuity). Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 7 Rambus’s arguments reduce to the unsupported argument that the claims, which recite a “synchronous memory device,” require a single chip. (See Rambus App. Br. 6-26; accord Micron Resp. Br. 14 (“Rambus’s brief relies on substantially the same single-chip argument rebutted above (although stated in different forms), and should be rejected because the relevant claims are not limited to single-chip structures.”).) Rambus does not present persuasive objective evidence establishing that the ordinary and customary meaning of a “synchronous memory device” is a “chip.” 6 Moreover, as similarly found in our previous decisions, the term “memory device” includes the disclosed memory device embodiment in Figure 9 of the ‘120 patent, “sometimes called a memory stick,” (‘120 patent, col. 19, ll. 60-61 (emphasis supplied)), or a “primary bus unit,” (id. at l. 59): “In general, each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices on an attached memory bus unit.” (Id. at col. 20, ll. 4-7 (emphasis added).) In other words, “this invention” includes what can sometimes be called a memory stick, but in general, each reference to a memory device includes a memory stick. Bolstering this interpretation is the fact that the ‘120 patent refers to “memory devices on the transceiver bus as well as on the primary bus units” 6 Cf. Infineon, 318 F.3d at 1091 (holding that the term “integrated circuit device” as recited in claim 26 of Rambus’s related ‘804 patent takes its ordinary meaning of “chip”) (internal quotation marks and citations to trade dictionaries and other authority omitted); see also Mangosoft, Inc. v. Oracle Corp., 525 F.3d 1327, 1331 (Fed. Cir. 2008) (“‘the persistent memory device will be understood to include a plurality of local persistent memory devices’”) (quoting U.S. Pat. No. 6,148,377). . Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 8 (col. 20, ll. 3-4) and refers to preferably busing a TrncvrRW signal to “a more sophisticated transceiver” on a memory stick attached to the transceiver bus and generally busing that signal to “all devices on the transceiver bus” (id. at ll. 29-33 (emphasis added)). Since memory sticks are on the transceiver bus 65 (Fig. 9, col. 19, l. 62), it follows that a memory stick is a memory device. The ‘120 patent also refers to “[o]ther devices, generically referred to as peripheral devices, including disk controllers, video controllers or I/O devices,” implicitly distinguishing such “[o]ther devices” from “memory devices.” (See col. 20. at ll. 7-10.) Faced with this disclosure, Rambus acknowledges, with respect to this memory stick embodiment, that “a transceiver in combination with one or more memory device [sic] can replace a memory device in the disclosed embodiments” (Rambus App. Br. 11 (emphasis added)), but contends that the “specification does not state that [the memory stick] is itself a memory device” (id.) Rambus’s “replace[ment]” characterization bolsters the findings here and in the related decisions mentioned supra by showing that skilled artisans would have understood that when the ‘120 patent refers to a synchronous memory device, it includes the chip’s “replacement” device, i.e., the synchronous memory stick. Similar to the related findings in the previous BPAI ‘1178 decision, one disclosed memory device, “sometimes called a memory stick” (‘120 patent, col. 19, ll. 60-61) as disclosed in the ‘120 patent, can include masters, other controllers, and/or transceivers thereon. (Id. at col. 20, ll. 1-13, Fig. 9.) These findings also contradict Rambus’s related argument that a memory device precludes a controller and other prior art memory board functions (see e.g. Rambus App. Br. 9, 20-21). (Accord RAN 18; Micron Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 9 Resp. Br. 9.) In other words, since the disclosed ‘120 patent’s memory stick device includes the controllers noted (i.e., transceiver, master, or other controller), the claims do not preclude the memory control unit (MCU) on the iAPX memory controller. (See A1-A3; accord Micron Resp. Br. 14.) Rambus’s arguments fail to demarcate a meaningful claimed difference (implied or express) between the iAPX MCU and the controllers and/or transceivers disclosed as part of the ‘120 patent’s memory stick device (or control functions disclosed as part of the chip embodiment). Similar to the memory device interfaces disclosed in the ‘120 patent (i.e., including the transceiver interface between the memory stick memory arrays and bus, and the chip interface), the MCU “interfaces memory storage arrays to the memory bus.” (A2; accord A1.) Rambus also unpersuasively argues that the following ‘120 patent sentence distinguishes the disclosed memory devices over prior art memory boards (and their controllers) such as the iAPX module: “‘Another unique aspect of this invention is that each memory device is a complete, independent memory subsystem with all the functionality of a prior art memory board’.” (Rambus App. Br. 9 quoting ‘120 patent at col. 7, ll. 21-24).). To the contrary, the sentence shows no distinction, and rather, shows that the “invent[ive]” memory devices, including the memory stick device, includes prior art controller functions such as those in the iAPX module’s MCU, because the iAPX’s module and the ‘120 patent’s memory stick (and chip) are “complete independent memory subsystem[s]” (id.) (which may include a controllers and/or masters). Hence, in context, the sentence shows that the memory devices include prior art memory board controller functions or hardware with other Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 10 purportedly inventive functions and/or hardware circuits disclosed in the ‘120 patent, for example, such as the “[n]ew bus interface circuits” (‘120 patent, col. 4, l. 26) and the device identification and multiplexing features (see id. at col. 3, ll. 33-40). 7 (Accord Micron Resp. Br. 8-9 (discussing interface and other touted benefits); RAN 6, 7, 18, 20).) And of course, many, if not all, of these touted features would be within both of the disclosed embodiments (i.e., the chip and stick), based, inter alia, on Rambus’s “replacement” argument supra (with the stick likely having more functional capability since it can include transceivers, masters, and other controllers (see ‘120 patent at col. 19, l. 45 to col. 20, l. 65)). Rambus’s arguments with respect to claim 15 largely track those for claim 1. (See Rambus App. Br. 22-24.) Rambus also points out that claim 15 also recites a separate “controller” (see Rambus App. Br 23), but claim 15 only recites “[a[ method of controlling a synchronous memory device by a controller” in the preamble without relating any specific functions in the body of the claim to that preamble controller. In any event, the Examiner describes control functions in the iAPX system as emanating from a BIU (bus interface unit) working in conjunction with a GDP (general data processor). (See RAN 69-71; A1 (showing the GDP and BIU to be part of a processor module).). As discussed supra, the MCU, an “interface” to memory arrays (A1, accord A2), forms part of the memory device recited in claims 1 and 15. (See RAN 21, 23, 63-64, 69-71; 7 See also Infineon, 318 F.3d at 1094 (“‘The present invention is designed to provide a high speed, multiplexed bus . . . .’”) (quoting Rambus’s related ‘918 patent, col. 5, ll. 36-46). Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 11 Micron Resp. Br. 14-15; Rambus App. Br. 2.) Apart from the MCU and regarding the controller of claim 15, the Examiner finds, inter alia, that the BIU “provides operation codes,” (RAN 71) and checks for errors. (See RAN 71-72.) The iAPX BIU also aids in arbitrating access to the memory bus and makes other memory bus access decisions. (A1.) As such, Rambus’s argument that the BIU is merely an “intelligent switch” and the MCU acts as an “‘intelligent memory controller’,” so that the BIU cannot satisfy the controller limitation of claim 15 (Rambus App. Br. 23 (emphasis by Rambus quoting the iAPX Manual)), and other related arguments, fail to rebut the Examiner’s findings, Micron’s contentions, and the record (see A1-A3), which show that the iAPX processor module (including the BIU and/or GDP) satisfies the controller recited in claim 15. Based on the foregoing discussion, the contemporaneous and prior Board decisions mentioned supra, and the findings and contentions of the Examiner and Micron, the Examiner did not err in rejecting claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 for anticipation based on iAPX. Affirmance of the iAPX anticipation rejection renders it unnecessary to reach the Budde anticipation rejection. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding anticipation). MICRON’s CROSS-APPEAL Claims Claims 26, 29, and 33 on cross-appeal by Micron follow: 26. A synchronous dynamic random access memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 12 input receiver circuitry, including a first plurality of input receivers to sample block size information synchronously with respect to the external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code; and a plurality of output drivers to output the amount of data in response to the first operation code. 29. The memory device of claim 26 wherein the input receiver circuitry samples the first operation code synchronously with respect to the external clock signal. 33. The memory device of claim 29 wherein the first operation code includes precharge information. Refused Rejections The Examiner refused to maintain several rejections of claims 26, 29, and 33 appealed by Micron. (See Micron Cr. App. Br. 3 (listing refused rejections).) Only the following rejections listed next are considered here: 8 Claims 26 and 29 as anticipated and/or obvious based on Bennett. 9 Claim 33 as obvious based on Bennett, Wicklund, 10 Bowater, 11 or Olson. 12 8 The Micron listed rejections based on a primary reference to Moussouris are not considered in this Decision. (See Micron App. Br. 3 (i.e., Micron issues numbered 3 and 4).) 9 Bennett et al., Patent No. 4,734,909 (March 1988). 10 Wicklund et al., U.S. Patent No. 5,159,676 (Oct. 27, 1992, effectively filed Dec. 5, 1998). 11 Bowater, U.S. Patent No. 5,301,278 (Apr. 5, l994, effectively filed Apr. 29, 1998). 12 Olson et al., U.S. Patent No. 4,933,910 (June 12, 1990, effectively filed July 6, 1988). Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 13 Claims 26 and 29 as obvious based on iAPX and iRAM. 13 Claim 33 as obvious based on iAPX, iRAM, and Olson. Claims 26, 29, and 33 as anticipated by the JEDEC Standard. 14 Claims 26, 29, and 33 as anticipated by Park. 15 Additional Factual Findings-iRAM I1. The term “iRAM” means integrated RAM. The iRAM Manual teaches shifting some of the CPU tasks to such an integrated RAM, relieving the CPU of hardware functions. (iRAM 1-1; 3-432-434.) 16 In other words, the iRAM Manual teaches integrating more functions into a single device, an integrated memory, to relieve the CPU. In general, a dynamic RAM (DRAM) “holds a commanding position” in terms of cost for larger memory systems, as opposed to the static RAM (SRAM). (iRAM at 3-432.) The iRAM may be synchronous. (Id. at 3-446.) “Two basic RAM types have evolved since 1970.” The first type - “[d]ynamic RAMs” and “the second type - static RAMs.” (iRAM at 1-1.) I2. The iRAMs evolved in part because “with the advent of VLSI technology and 64KRAM densities, it became possible to further integrate or simplify memory system design.” (Id. at 3-432.) “An iRAM integrates all the components of a dynamic RAM memory system into a single device.” 13 Memory Components Handbook, Intel. Corp., Ch. 1, 3 (1985). 14 Joint Electronic Device Engineering Counsel (JEDEC) Standard No. 21-C, Revision 9 (1999). 15 Park et al., US 5,590,086 (Dec. 31, 1996, effective filing Oct. 1993). 16 These latter pages, i.e., 3-432, etc., appear under headings of “AP-132” on each page, which appear to signify an attached application note by John J. Fallin and William H. Righter (Intel. Corp. 1982). (See iRAM at 3-431.) Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 14 (Id. at 3-433.) The iRAM “permits a very simple interface to the CPU and yet provides guaranteed refresh, optimized timing, and minimal hardware support requirements.” (Id.) “The integration used in the iRAM includes the refresh timer, refresh address control and counter, address multiplexing, and memory cycle arbitration as well as an 8-bit wide memory array.” (Id.) Figure 3 indicates that the microprocessor retains some memory control functions, for example, memory addressing, while putting the memory control circuits in the iRAM. (See Fig. 3 at 3-433). Other functions including multiplexing are controlled by the CPU and/or a bus controller connected to an iRAM array. (See 3-448, § 5.2) Based on eliminating some of the “overhead involved in the design and cost of the hardware for the controller. . . . iRAMs have a clear advantage for anything other than very small or very large memory systems.” (Id. at 3-434.) Analysis Micron’s Cross-Appeal and Rebuttal Brief discussing the rejections listed supra are persuasive to show Examiner error in the refusal to maintain the Bennett and iAPX based obviousness rejections, but not in the refusal to maintain the Park and JEDEC based anticipation rejections. Micron’s Brief discussions of the above-listed Bennett and iAPX rejections are hereby incorporated by reference and adopted. Bennett- Claims 26 and 29 Micron’s contention that the memory chips discussed in Bennett are necessarily synchronous dynamic random access memory devices (i.e., Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 15 synchronous DRAM chips) need not be addressed here based on the alternative obviousness rejection. (See Micron Cross App. Br. 5-9.) 17 With respect to obviousness, Micron persuasively shows that DRAMs were a well-known, if not dominant, form of a memory chip device at the time of the invention (see e.g. Micron Br. 7 n. 4; 19 n. 12; accord supra I1 (showing only two basic types of RAM); I2). Neither the Examiner nor Rambus take issue with or rebut Micron’s contention that DRAMs were well known, if not dominant, at the time of the invention. Rather, the Examiner contends that Micron did not initially (i.e., in the Request for Inter Partes Reexamination) raise the obviousness of DRAMs in light of Bennett’s teachings (see RAN 55, ACP 112-113). The Examiner concludes that in any event, Micron’s Request fails to adequately articulate the obviousness of a using a single DRAM chip as a memory device. (See RAN 55-56.) Micron, in turn, persuasively points out that Micron did initially raise the obviousness of using DRAMs in light of Bennett. (See Micron Cr. App. 17 Micron also asserts that claim 26 is not limited to a single DRAM chip because the term “synchronous dynamic random memory device” is recited only in the claim’s preamble. (See Micron Reb. Br. 3.) Micron’s assertions do not address the term “the memory device” which appears in the body of the claim and which relates back to the preamble. See Bell Comm. Research, Inc. v. Vitalink Comm. Corp., 55 F.3d 615, 621 (Fed. Cir. 1995) (claimed method for transmitting a packet including source and destination addresses according to the preamble limits the claim to packets with such addresses where the body of claim refers back to the preamble using the term “said packet”). Micron’s arguments indicate that Micron concedes that if the preamble is limiting, claim 26 requires a single chip DRAM. (Accord ACP 47 (finding claim 26 limited to a synchronous DRAM).) In any event, the obviousness rejections proposed by Micron based on Bennett, and iAPX with iRAM, cover that narrow (i.e., single chip DRAM) interpretation. Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 16 Br. 5 (quoting Request for Inter Partes Reexamination 29-30) which describes Bennett’s “‘inherent or obvious description of DRAM based devices’”) (emphasis in Micron’s Brief).) Moreover, Micron persuasively shows here that the various discussions of memory chips as preferred devices over cards in Bennett and other related teachings relied upon in Micron’s Briefs would have rendered obvious employing such a ubiquitous device as a DRAM, a “synchronous dynamic random access memory device” as recited in claim 1. (See Micron Cr. App. Br. 5-9; Micron Reb. Br. 4-7 (further responding to Rambus’s contentions, citing speed and power (id. at 5) as showing the inherency of a chip versus a card).) 18 Rambus contends that Bennett does not disclose other claimed features of claims 26 and 29. In turn, Micron points to the Request for Inter Partes Reexamination (Micron Cr. App. Br. 5 (citing Request 15-16, 29-31)) and further responds (Micron Reb. Br. 9-11) to show how Bennett purportedly satisfies these other claimed features. The Examiner does not appear to have made relatively recent specific findings in this reexamination proceeding as to these other alleged missing elements (see ACP 112-113; RAN 56-57), though Micron points out that an earlier action supports 18 These speed and power features of chips, although cited by Micron for inherency, also evidence an “implicit motivation” for obviousness, of using a chip versus the card compared thereto in Bennett (i.e., such as a known DRAM chip). See Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit motivation to combine exists … when the ‘improvement’ is technology- independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”) Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 17 Micron’s position (see Micron Reb. Br. 8 (citing Office Action at 121-123 (July 22, 2009).) On remand, the Examiner has the discretion to sort out the various contentions and make specific findings either way. But Micron shows that on this record, the Examiner erred by failing to maintain the rejection of claims 26 and 29 based on the unsupported conclusion that it would not have been obvious to employ a well-known DRAM as a substitute for a similar generic memory chip as disclosed by Bennett. Bennett with Wicklund, Bowater, or Olson - Claim 33 Similarly, based on this record, absent specific recent and relevant findings by the Examiner, Micron also persuasively demonstrates the obviousness of adding the precharge information as recited in claim 33 based on the further teachings of Wicklund, Bowater, or Olson. (See Micron Cr. App. Br. 9-12; Micron Reb. Br. 11-15 (responding to Rambus and noting (id. at 11) early office action agreement by the Examiner as to Bennett’s operation code).) Wicklund shows, in a similar fashion to the ‘120 patent, that precharge normally (i.e., when the DRAM is not in page mode) occurs at the end of a read or write function, showing the obviousness of banding the two related functions into Bennett’s write code. (Compare Wicklund col. 3, ll. 45-52 with ‘120 patent, ll. 16-24.) Also, Bennett discloses multiple functions in a code. (See Bennett Fig. 34 (read-modify-write code signifying multiple functions).) In any event, the Examiner appears to rely primarily on the above-discussed erroneous conclusion that Micron did not persuasively show that Bennett, in light of known prior art components, renders a DRAM chip obvious. (See RAN 57, ACP 112-113.) Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 18 Moreover, the type of information added to the operation code introduced in claim 26, in this case, precharge information as recited in claim 33, constitutes nonfunctional descriptive material, because claim 33 does not require the memory device to precharge, decide to precharge, or even have the ability to do either, based on that information. In other words, under this alternative claim interpretation, claim 33 does not require the memory device of claim 29 to operate any differently based on that information (i.e., as compared to some other type of information). See In re Ngai, 367 F.3d 1336, 1338 (Fed. Cir. 2004) (requiring a “new and unobvious functional relationship between the printed matter [i.e., information] and the substrate [i.e., device]”) (quoting In re Gulack, 703 F.2d 1381, 1385 (Fed. Cir. 1983)). Based on the foregoing discussion, Micron demonstrates that the Examiner erred in refusing to maintain the obviousness rejection of claim 33 based on Bennett and Wicklund, Bowater, or Olson. iAPX with iRAM - Claims 26 and 29 With respect to the obviousness rejection of claims 26 and 29 based on iAPX and iRAM, Micron persuasively addresses the contentions of the Examiner (see RAN 55-56), and shows how it would have been obvious based on iRAM to integrate known functions of the iAPX memory module into a single DRAM chip. (Micron Cross App. Br. 15-22.) Essentially, the iRAM reference shows that prior to the claimed invention, chip designers were integrating typical control functions into DRAM memories, to free controllers (e.g., a CPU), of those memory control tasks, thereby minimizing cost, optimizing timing, and simplifying memory systems by eliminating such CPU tasks. (See Micron Cross App. Br. 18 (discussing e.g., iRAM at Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 19 1-1 and 3-432; accord supra I1, I2).) Such chip integration results in “cheaper, cleaner, faster [i.e., based on shorter signal paths] . . . [or] more durable” devices, amounting to an “implicit motivation,” see Dystar, 464 F.3d at 1368. (See I1, I2.) Notwithstanding this universal motivation for integration, Rambus asserts that “iRAM teaches away from integrating the entire memory control unit of iAPX onto the DRAM devices in the storage array.” (Rambus Resp. Br. 25.) But this argument is not commensurate in scope with claims 26 and 29 since they do not require integrating all the MCU circuits onto all the DRAMs described in the iAPX Manuel. 19 Micron persuasively lists the specific control circuits in the iAPX MCU, including clock circuitry, input receiver circuitry, etc., required to produce synchronous DRAM as set forth in claim 26. (See Micron App. Br.17.) Micron also explains that the iRAM solution suggests a system of iRAMs and a processor, thereby indicating some processor control (see Micron App. Br. 18-19), and suggesting a simple “integrated solution” involving an “MCU interface” (id. at 21.) Rambus’s argument that the iRAM Manual only teaches integrating specific functions (Rambus Resp. Br. 25-26) does not show unobviousness. To the contrary, the arguments support obviousness. Such functions, and their circuits, including refresh, timing, and multiplexing, all involve maintaining a simple DRAM interface to relieve the CPU of certain control functions (I1, I2), thereby suggesting an integrated iAPX MCU interface 19 Micron also argues that Rambus’s chip calculation of 40 DRAMs in the iAPX module is faulty because it relies on a single data pin, whereas iRAM shows that 8 data pins were known, “lowering Rambus’s 40 chip calculation to 5.” (Micron Reb. Br. 26.) Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 20 with a DRAM chip, especially where the MCU is an interface ( A1, A2). The iRAM solution also includes synchronous iRAMs (I1), similar to the synchronous MCU operation (under the rejection of claim 1). Micron also points out that the Examiner finds “‘that it was known to integrate a MCU with a DRAM as shown by iRAM’” (Micron App. Br. 20 (quoting RAN at 52)), and as Micron also demonstrates, the Examiner’s and Rambus’s countervailing rationale for not maintaining that finding is not persuasive (see Micron App. Br. 19-22). In sum, this record shows little, if any, dispute over the fact that the iRAM Manual suggests integrating some control functions onto a DRAM chip to create an integrated synchronous memory chip having advantageous memory control and CPU interface features. As such, the combined teachings render obvious integrating at least some of the iAPX MCU control circuits and their functions onto single (or multiple) DRAM memory chip(s). Bolstered by the universal desire for integration, the combined teachings suggest synchronous integrated DRAMs (iRAMs), which, for example, might include multiplex, refresh, and optimal timing for memory access requests by a CPU or other control as suggested by iRAM (see I1, I2), and the underlying control circuits in the iAPX MCU identified by Micron, to synchronously access a desired amount of data, thereby rendering obvious the recited control circuits set forth in claims 26 and 29. Based on the foregoing discussion, Micron demonstrates that the Examiner erred in refusing to maintain the rejection of claims 26 and 29 based on the combined teachings of iRAM and iAPX. Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 21 iAPX with IRAM and Olson - Claim 33 The Examiner finds that Olson teaches sending precharge information to memory devices. (See ACP 88.) Micron agrees, and Rambus does not present persuasive evidence otherwise. (See Micron Cr. App. Br. 22; Rambus Resp. Br. 10, 27.) The Examiner also finds that the combination of Olson and the iAPX Manual suggests determining “whether or not to precharge.” (ACP 89.) However, the Examiner maintains that “iAPX and Olson fails to disclose” sending the precharge information of claim 33 with the first operation code which has block size information as recited in claims 26 and 29. (See Micron Cr. App. Br. 22 (quoting the Examiner’s rationale in the ACP at 89).) Micron responds that based on the combined teachings of iAPX and Olson, sending the required (e.g., block and precharge) read information in the same (i.e., first) operation code would have been obvious as one of a predictable number of finite solutions. (See id.) Setting aside the response for a moment, as discussed supra, the type of information added to the first operation code in claim 33, in this case, precharge information, constitutes nonfunctional descriptive material, because claim 33 does not require the device to precharge, decide to precharge, or to have the ability to do either (i.e., to operate differently based on the precharge information versus some other type of information). Such nonfunctional descriptive material concerning information which the claimed device need not even process to render a distinct decision fails to render claim 33 patentably distinct over iAPX and iRAM (i.e., with or without the added teachings of Olson). But even if the information is functional, on this record, Micron’s response is persuasive. For example, sending one operation code with information as required to perform certain Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 22 read operations would have been obvious for the purpose of keeping related read control information together in an existing (or modified) iAPX operation code. Based on the foregoing discussion, Micron shows that the Examiner erred in refusing to maintain the obviousness rejection of claim 33 based on iAPX, iRAM, and Olson. Secondary Considerations As Micron argues, Rambus has failed to establish a nexus or show that its secondary evidence is commensurate in scope with the claims 26, 29, and 33. (See Micron Reb. Br. 28-30 (adopting the Examiner’s findings).) For example, Micron contends that Rambus provided the same evidence in ten related reexamination proceedings. (Micron Reb. Br. 29.) Micron’s contentions are supported at least because Rambus directs attention to the same or similar evidence relied upon in the reexamination proceeding addressed in the Board’s companion ‘(App. No. 2011-008431) decision mentioned at the outset. In any case, Rambus fails to direct attention to relevant differences (and specific claim limitations). The discussion of secondary considerations in the companion (App. ‘8431 decision (at 30-36) applies here with almost equal force - with an exception. One difference here is that claims 26, 29, and 33 require DRAMs (and arguably a single DRAM chip according to the discussion supra (see e.g., note 17)), whereas the analysis in the companion decision relies partially on the premise that the claims involved there are not limited to DRAMs (single or multiple chips). On this record, Micron persuasively shows, and the Examiner apparently agrees, that Bennett discloses single memory chips having the other claimed features of claims 26 and 29 Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 23 (besides the DRAM limitation), and as such, those other features were not novel. As such, it follows that Rambus fails to show a nexus as to those non-novel features. 20 As also discussed in the companion ‘8431 decision (at 34), such generic considerations likely flow from a variety of several unclaimed features touted here or in other Rambus proceedings or patents, such as an internal DLL (delay locked loop), eight data lines, small DRAM sizes, multiplexed buses, packetized control, identification control mechanisms, doubly terminated clocks, and time access schemes. 21 Rambus also does not persuasively direct attention to sufficient secondary considerations which relate to a difference between specific types of memory chip devices (i.e., DRAMs as opposed to ROMs, SRAMs, DD RAMs, etc.) or to the added recitations in claim 33 (i.e., pertaining to the precharge information recited therein). While Rambus asserts that “precharging the sense amplifiers and bit lines depending on the information provided in the operation code improve [sic] efficiency of memory access by freeing up control bandwidth,” thereby helping to solve an alleged long-felt need to a memory bottle neck problem (Rambus Resp. Br. 28), the device 20 See Tokai Corp. v. Easton Enters., Inc., 632 F.3d 1358, 1369 (Fed. Cir. 2011) (“If commercial success is due to an element in the prior art, no nexus exists.”); Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299, 1312 (Fed. Cir. 2006) (“[I]f the feature that creates the commercial success was known in the prior art, the success is not pertinent.”). 21 See also Infineon, 318 F.3d at 1094, 1095 (“‘The present invention is designed to provide a high speed, multiplexed bus’” (quoting Rambus’s related ‘918 patent, col. 5, ll. 36-46), but “the prosecution history shows that a multiplexing bus is only one of many inventions disclosed in the ‘898 application.”) Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 24 claims at issue here do not require the claimed memory devices to precharge anything, as noted supra. Therefore, Rambus’s argument, which may loosely correspond to the precharge information recited in claim 33, shows that claims 26, 29, and 33 fail to satisfy any alleged long-felt need because the claims do not require precharging of circuits in the memory device. And as our ‘8431 decision further explains, Rambus’s proffered arguments and evidence about long-felt need (and failure of others) relates to purported solutions to memory bottle neck problems predicted to occur (or failures that allegedly did occur) in the relative future - i.e., in the mid-1990’s, after the effective 1990 filing date of the ‘120 patent. Therefore, Rambus does not show a long-felt need at the time of the effective filing date of the ‘120 patent. Rambus’s proffer of the same or similar evidence in related reexaminations involving claims directed to broader “memory devices” having other claimed features indicates that Rambus considers the generic evidence to be untied to (i.e., lack a nexus to) any specific type of memory device (i.e., DRAMs), or a device having the claimed features of claims 26, 29, or 33. (See Micron App. Br. 29.) Along these lines, Rambus mentions licensing under the “Farmwald Family,” which may or may not apply to DRAM memory stick devices and other disclosed, but not claimed, “Farmwald Family” features in single or multiple chip devices or systems. (See Rambus Resp. Br. 29.) Based on the foregoing discussion, Rambus fails to direct attention to persuasive countervailing secondary considerations outweighing Micron’s showing of obviousness based on Bennett, iAPX and iRAM. Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 25 Priority and Anticipation by JEDEC and Park Micron asserts that claims 26, 29, and 33 do not recite a multiplexed bus, and as such, are not originally supported back to the (first-filed) ‘898 application filing date (April, 1990, see supra note 4) - because the claims are too broad (i.e., too broad absent a recitation to a multiplexed bus which the ‘120 patent touts as important). Based on this contention, Micron asserts that claims 26, 29, and 33 are not entitled to a filing date prior to February 8, 2001, and are therefore anticipated by the JEDEC and Park references which antedate the 2001 date. (See Micron Cr. App. Br. 3, 26- 37.) In turn, the Examiner and Rambus rely, inter alia, on Infineon, 318 F.3d at 1094, to show that claims 26, 29, and 33 do not require a multiplex bus and are therefore originally supported. (RAN 35-40; Rambus Resp. Br. 20-21.) In rebuttal, Micron asserts that Infineon was decided before Phillips v. AWH Corp., 415 F.3d, 1303, 1317 (Fed. Circ. 2005) (en banc), and Infineon was therefore “decided under the wrong legal standard.” (Micron Reb. Br. 24.) Micron also asserts that Infineon was “directed to issues of claim construction, not to the issue of whether specific claims were entitled to an earlier priority date.” (Id.) Micron’s contentions are unconvincing to show that Infineon was wrongly decided or would somehow require reaching a different result based on a written description priority analysis as opposed to its claim construction analysis. In the Board’s previous ‘1178 decision mentioned at the outset, to support a claim construction for the term “memory device,” the Board relied on rationale from Infineon which serendipitously relates to the multiplex bus issue involved here as follows: Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 26 Under analogous circumstances involving the ‘918 patent, our reviewing court [in Infineon] held that the ordinary term “bus” could not be read restrictively as a “multiplexed bus” even though the patentee described the “present invention” in terms of a “multiplexed bus” in isolated portions of the specification because “the remainder of the specification and the prosecution history shows that Rambus did not clearly disclaim or disavow such claim scope in this case.” Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1094-95 (Fed. Cir. 2003); (‘1178 BPAI Dec. at 19 (quoting Infineon).) The passage shows that Infineon relied on the ‘918 patent specification and prosecution history, as opposed to relying unnecessarily on “much diminished” precedent involving pre-Phillips “dictionary” cases, contrary to Micron’s arguments. (See Micron Reb. Br. 24). The gravamen of Micron’s arguments is that the inventor was not in possession of generic memory devices which are “neutral regarding the presence or absence of an interface to a multiplexed bus” (Micron Cr. App. Br. 32), but Micron’s arguments are not persuasive to show that skilled artisans would not have recognized that the ‘898 application discloses other important aspects of the invention for use in generic bus systems. See Infineon, 318 F.3d at 1094-95 (noting that “multiplexing is not a requirement in all of Rambus’s claims,” that the PTO issued a restriction to a multiplexing group and a latency group, and that “the PTO demonstrated an understanding of ‘bus’ that is not limited to a multiplexing bus”); see also Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1351-53 (2011) (holding that evidence supported jury verdict of written description for similar Rambus claims where “the supposed genus consists of only two species, a multiplexed bus and a non-multiplexed bus”). Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 27 Also, original claims 73 and 91 in the ‘898 application recite a generic bus. While Micron contends that these claims are directed to different disclosed inventions (Micron Cr. App. Br. 28-29), these claims bolster the finding here that skilled artisans would have understood that many of the touted features in the ‘898 application, including the synchronous sampling of block size information as recited in device claim 26 to obtain speed gains and power reduction (see ‘120 patent, col. 3, ll. 4-6, 23-27), could have been practiced using known generic buses not requiring multiplexing. Cf. Crown Packaging Tech. Inc. v. Ball Metal Beverage Container Corp., 635 F.3d 1373, 1382-84 (Fed. Cir. 2011) (district court erred in finding lack of written description in generic claims where the application discloses separate solutions to related problems). Based on the foregoing discussion, Micron has not shown error in the Examiner’s finding that claims 26, 29, and 33 have original written description support as necessary to antedate Park or JEDEC as prior art anticipation references. Moussouris Reversal of the above-discussed obviousness rejections of claims 26, 29, and 33 renders it unnecessary to reach the propriety of the Examiner’s decision to refuse to maintain the rejections based on Moussouris (supra note 8). Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding anticipation). CONCLUSION Rambus did not demonstrate that the Examiner erred in deciding that iAPX anticipates claims 1-4, 6, 8-11, 15, 16, 19, and 21-25. Micron did Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 28 demonstrate that the Examiner erred in deciding not to maintain the obvious rejections of claims 26 and 29 based on Bennett, or iAPX and iRAM, and the obvious rejections of claim 33 based on the added teachings of one or the other of Olson, Bowater, or Wicklund. Micron did not demonstrate that the Examiner erred in deciding not to maintain the anticipation rejections of claims 26, 29, and 33 based on Park or JEDEC. DECISION The Examiner’s decision to reject claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 is affirmed. The Examiner’s decision not to maintain the rejections of claims 26, 29, and 33 is reversed. 22 Requests for extensions of time in this inter partes reexamination proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79. AFFIRMED-IN-PART ak Counsel for Patent Owner: Naveen Modi, Esq. Finnegan, Henderson, Farabow, Garrett & Dunner, LLP 901 New York Avenue, NW Washington, DC 20001-4413 22 See 37 C.F.R. § 41.77(b) (denominating a reversal of a refusal to reject as a new ground of rejection). Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 29 Counsel for Third Party Requester Samsung Electronics Co., Ltd.: David L. McCombs, Esq. Haynes and Boone, LLP 2323 Victory Avenue, Suite 700 Dallas, TX 75219 Counsel for Third Party Requester Micron Technology Inc.: Tracy W. Druce Novak Druce & Quigg, LLP (NDQ Reexamination Group) 1000 Louisiana Street, 53 rd Floor Houston, TX 77002