Ex Parte 6304937 et al

Patent Trials and Appeals Board

May 20, 2013

95001188 - (R) (P.T.A.B. May. 20, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,188 05/12/2009 6304937 9278.002.937 2299
86497 7590 02/11/2015
Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
02/11/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

RAMBUS INC.
Patent Owner, Appellant

v.

NVIDIA CORP.
Requester
____________

Appeal No. 2013-004540
Inter Partes Reexamination Control No. 95/001,188
United States Patent 6,304,937 B1
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON REMAND
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Reexamination Control No. 95/001,188
Patent 6,304,937 B1

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This case returns to the Board upon a remand from the Federal
Circuit. See In re Rambus, Inc., Appeal 2013-1957 (Fed. Cir. Jan. 31, 2014)
(“Remand Order”). In the Remand Order, the Court remanded the case in
light of its recent decision in Rambus v. Rea, 731 F.3d 1248 (Fed. Cir. 2013)
(“Rambus-Rea”), because, as the Court noted, the two cases involve similar
issues.
1

Rambus-Rea affirmed-in-part, vacated-in-part, and remanded the case
heard in the appeal Rambus, Inc. v. NVIDIA Corp., Appeal No. 2012-000171
(BPAI 2012)(“’171 proceeding”), which involved an inter partes
reexamination of Rambus’s related U.S. Pat. No. 6,260,097 (“’097 patent”).
See Rambus- Rea. Ultimately, Rambus-Rea directed the Board to consider
certain facts of record, including secondary considerations of non-
obviousness, and to issue a new ground of rejection in the ’171 proceeding if
the facts so warrant. See id. at 1258. Rambus-Rea noted that the Board’s
“procedure [for issuing a new ground of rejection] ensures that appellants
have an appropriate opportunity to respond and, if necessary, supplement the
record before the examiner.” Id. at 1256.
Pursuant to the remand in Rambus-Rea , the Board issued a new
decision, Rambus, Inc. v. Lee, Appeal No. 2012-000171 (PTAB Sept. 2,
2014) (Reexamination Control No. 95/001134) (“’171 Remand Decision”).
Rambus elected not to seek Board review of the ’171 Remand Decision (by
rehearing) or seek to re-open prosecution before the examiner in that case.
Subsequently, the Board terminated the appeal in Rambus-Rea. See ’171
Order Board Rule 41.77(f) (PTAB Nov. 19, 2014).

1
As is the case here, NVIDIA Corp. withdrew from the proceeding.
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The instant proceeding arose out of NVIDIA Corp.’s request for inter
partes reexamination of U.S. Patent No. 6,304,937 B1 (“’097 Patent”) to
Farmwald et al., Method of Operation of a Memory Controller (issued Oct.
16, 2001, and claiming priority to Apr. 18, 1990 based on a series of
continuation applications starting with application number 07/510,898)
assigned to Patent Owner Rambus. The ’937 Patent involved here and the
’097 patent involved in Rambus-Rea each claim continuity back to common
application number 07/510,898.
In the instant case, the Examiner confirmed claims 4–7, 9, 17, 19–22,
31–35, and 39. Appellant, Patent Owner Rambus, appeals from the
Examiner’s decision in the Right of Appeal Notice (RAN) rejecting claims
1–3, 8, 10–16, 18, 23–30, 36–38, and 40.
We have jurisdiction under 35 U.S.C. §§ 134(b) and 315.
We AFFIRM, pro forma, the Examiner’s decision to confirm claims
4–7, 9, 17, 19–22, 31–35, and 39 (see note 1), and AFFIRM the decision to
reject claims 1–3, 8, 10–16, 18, 23–30, 36–38, and 40.
STATEMENT OF THE CASE
Rambus refers to several related judicial and other proceedings
including inter partes and ex parte reexaminations, International Trade
Commission proceedings, a Federal Trade Commission proceeding, and
Federal District Court and Circuit Court proceedings in its opening Appeal
Brief. (See Rambus App. Br. iii-vii.) We have considered each decision
relevant to this proceeding to which Rambus or Rambus-Rea directs
attention, and other proceedings, as discussed below.

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Exemplary claims 1 and 3 (emphasis added) on appeal follow:
1. A method of controlling a synchronous memory
device, wherein the memory device includes a plurality of
memory cells, the method of controlling the memory device
comprises:
issuing a first operation code to the memory
device, wherein in response to the first operation
code, the memory device outputs first and second
portions of data;
sampling the first portion of data synchronously
with respect to a rising edge transition of an
external clock signal; and
sampling the second portion of data synchronously
with respect to a falling edge transition of the
external clock signal.
3. The method of claim 1 wherein, in response to the first
operation code, the first portion of data is output after a
programmed amount of time transpires.
NEW GROUND OF REJECTION
In Rambus-Rea, the court held certain claims, in the ’097 patent,
including claims 1 and 2 (emphasis added), which follow, to be anticipated
by Inagaki:
2

1. A method of controlling a synchronous memory
device, wherein the memory device includes a plurality of
memory cells, the method of controlling the memory device
comprises:
issuing a write request to the memory device,
wherein in response to the write request,
the memory device samples first and second
portions of data;

2
Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record).
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providing a first portion of data to the memory
device synchronously with respect to a
rising edge transition of an external clock
signal; and
providing a second portion of data to the memory
device synchronously with respect to a
falling edge transition of the external clock
signal.

2. The method of claim 1 wherein the write request
includes an operation code.

See Rambus-Rea at 1251, 1254. The central difference between claim 1 here
and anticipated claim 1 in Rambus-Rea is that the latter claim 1 recites a
“write request” to cause the memory device to “sample” (i.e., input) data,
and claim 1 here recites an “operation code” to cause the memory device to
“output data.” A “write request” includes an “operation code,” according to
dependent claim 2, which Rambus–Rea held to be anticipated by Inagaki.
According to the ’937 Specification, “an op code (operation code) specifies
the type of access,” and can be merely a “single Read/Write switch: if it is a
1, then the operation calls for a read from the slave . . . ; if it is a 0, the
operation calls for a write into the slave.” (’937 Patent, col. 9, ll. 50–56.)
Mr. Murphy, Rambus’s declarant, agrees that the operation code can be “one
or more bits to specify a type of action.” (Murphy Decl. ¶ 25.)
Regarding the distinction between inputting and outputting data, most
memory devices, including Inagaki’s RAM (random access memory),
perform both functions. (See I1 infra (factual findings citing Inagaki 2).)
For example, Inagaki’s system performs “data input or output every half-
cycle based on an external clock.” (Id. at 2 (emphasis added.)
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The examiner in the ’171 proceeding found that Inagaki discloses
issuing an external signal for inputting/sampling and outputting data (i.e.,
writing and reading) to and from the RAM memory device.3 (’171 Right of
Appeal Notice 35 (“’171 RAN”)). Addressing claim 2 of the ’097 patent in
that proceeding, the examiner found that “Inagaki performs operations such
as read or write to the random access memory [(RAM)] thus, the signals
indicating a write operation includes an operation code.” Id. at 38. The
examiner also quoted Inagaki: “‘[A]n I/O shift register . . . read[s] signals so
as to continuously read data [a read operation], or that reads an external
signal to . . . read[] . . .data into the memory cells [a write operation] . . .
wherein the I/O shift register performs data input or output every half-cycle
based on an external clock.” (Id. at 39 (quoting Inagaki 3 ¶ 5, additions by
examiner).)
Rambus did not challenge this finding or reasoning at the Federal
Circuit in Rambus-Rea. Following the examiner’s findings and rationale in
the ’171 RAN and the holding of Rambus-Rea, it follows that the signal in
Inagaki that specifies a read from the RAM either includes, or, is itself, an
operation code to indicate sampling.
Regarding sampling, the Examiner indicates that must occur by
another receiving device: “[I]f the memory of Inagaki is to output every
half-cycle, then there must be a receiving device that is capable of receiving
the data every half cycle. If not, then the memory device of Inagaki would

3
The term “Examiner” refers to this proceeding, and the term “examiner”
refers to related proceedings. Rambus also cites to and relies upon our
decision in the ’171 proceeding, which involves the ’097 patent. (See, e.g.,
Reb. Br. 9 (citing the “’097 [patent] Decision”).)
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not be able to output data every half cycle since a bottleneck would be
created.” (RAN 57 (emphasis added).) The record supports the finding,
which Rambus does not challenge. Inagaki implies a receiving device
samples the memory device’s transmitted data on rising and falling clock
edges otherwise a bottleneck would occur. Inagaki discloses “transfer[ring]
data [at] . . . twice the conventional speed,” and refers to the “operating
speed.” (Inagaki 2.) The sole reason for outputting data fast is to receive it
just as fast––to increase the overall operating speed.
Therefore, Inagaki anticipates claim 1 here in a parallel fashion to the
anticipation of claim 2 in Rambus-Rea. Inagaki also anticipates claim 13,
which requires the rising and falling edges “to transpire in the same clock
cycle.” In the alternative, Inagaki renders obvious claim 1, 2, and 13,
because skilled artisans would have recognized that Inagaki’s system would
have benefitted from a receiver to sample the clocked memory device data in
order to take advantage of the speed doubling disclosed by Inagaki, where
Inagaki generally discloses “increasing the data rate,” and receiving and
transmitting “block access memory,” to increase “operating speed.” (See
Inagaki 2.)
In Q.I. Press, B.V. v. Lee, 752 F.3d 1371 (Fed. Cir. 2014), the Federal
Circuit indicated that in similar circumstances that involve a rejected claim
and a claim of apparent similar scope, “an obligation is owed to the public”
to enter a new ground of rejection to the claim of similar scope. See id.
at1383. Accordingly, in addition to the new grounds pursuant to the remand,
we enter a new ground of rejection: anticipation by Inagaki, or obviousness
over Inagaki, of claims 1, 2, and 13, based on the findings in the ’171
proceeding by the examiner with respect to that claim, which are herein
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incorporated by reference, and the new findings herein. (’171 RAN 35–39
(outlining anticipation of ’171 patent claims 1 and 2 by Inagaki); ’171
Action Closing Prosecution 42–51.)
RAMBUS’s INSTANT APPEAL
Rambus appeals the rejection of claims 1–3, 8, 10–16, 18, 23–30, 36–
38, and 40 based on the iAPX Manual
4
and the iAPX Specification,
5
or
Budde,
6
and Inagaki. The thrust of Rambus’s arguments is addressed in the
Board’s recent ’171 Remand Decision, which involves similar claim terms
and the same prior art, as the Court noted in its Remand Order.
iAPX and Inagaki–Obviousness
In both cases, Rambus’s central arguments prior to its appeal in
Rambus-Rea were that iAPX does not disclose or render obvious a
synchronous “single” memory chip, and that a person having ordinary skill
in the art in 1990 would not have modified the iAPX memory module’s
memory control unit (MCU) to utilize both rising and falling edges of
external clock(s) to input or output data from the iAPX memory module
according to Inagaki’s teachings. (See App. Br. 1–15.) Despite focusing at
least half of its brief on this “single chip” argument, Rambus did not pursue

4
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
5
Electrical Specifications for iAPX 43204 Bus-Interface Unit (BIU) and
iAPX 43205 Memory Control Unit (MCU), Intel Corp. (1983). The parties
treat the Manual and Specification as describing the same iAPX system;
therefore, based on arguments of record, the two documents will be referred
to collectively as one “iAPX” document and part and parcel of the same
rejection. (See Rambus App. Br. 21.)
6
Budde et al., U.S. 4,480,307 (Oct. 30, 1984). Budde is essentially
cumulative to the teachings in the iAPX Manual and Specification, and
involves the same system.
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this argument before the Federal Circuit in Rambus-Rea. We adopt and
incorporate-by-reference our previous Decision in this proceeding to the
extent it does not conflict with Rambus-Rea, and the ’171 Remand Decision,
which each include a discussion of the single chip issue.
Rambus-Rea affirmed the Board’s anticipation holding in the ’171
proceeding that Inagaki anticipates claims 1, 2, 7, 8, 10, and 14 in the ’097
patent. See Rambus-Rea at 1254. In that case, the Board also had held that
claims 1–5, 7, 8, 10–12, 14, 26, 28–32, 34 and 35 of the ’097 patent would
have been obvious based on the iAPX Manual,
7
the iAPX Specification,
8

and Inagaki. See Rambus-Rea at 1254. (In other words, the prior art
involved in both cases is the same.) Rambus-Rea vacated-in-part and
remanded a portion of that obviousness decision, “the Board’s decision that
claims 3–5, 11, 12, 26, 28–32, and 35 are unpatentable” because of
procedural and other errors committed by the Board in its prior decision,
including the failure to designate our decision in that case a new ground of
rejection. Rambus-Rea, 731 F.3d at 1258.
Rambus-Rea determined that the Board committed procedural error
because it “supplied its own reasons to combine iAPX and Inagaki,” thereby
depriving Rambus “of . . . due process rights.” Id. at 1256. Accordingly,
Rambus-Rea cited the Board’s procedure for instituting a new ground of
rejection. Id. (citing 37 C.F.R. § 41.77(b)). In response, this Decision

7
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
(attached as Exhibit 3 to NVIDIA’s Respondent Brief).
8
Electrical Specifications for iAPX 43204 Bus-Interface Unit (BIU) and
iAPX 43205 Memory Control Unit (MCU) (March 1983) (attached as
Exhibit 7 to NVIDIA’s Respondent Brief).
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hereby is designated as a new ground of rejection to provide Rambus its due
process rights. This new Decision also addresses Rambus-Rea’s holding that
the “Board erroneously placed the burden on Rambus to prove that its claims
were not obvious,” id. at 1255, and that “the Board erred in its treatment of
objective evidence of nonobviousness,” id. at 1256.
9

The central thrust of Rambus-Rea is that the ’171 record did not
support the obviousness of modifying the iAPX system by using Inagaki’s
dual edge clocking scheme. Pursuant to the remand in both cases, the Board
hereby addresses the Examiner’s determination of obviousness. We adopt
and incorporate by reference the findings by the Examiner as to the
obviousness rejection of claims 1–3, 8, 10–16, 18, 23–27, 29, 30, 36–38.
(See Right of Appeal Notice “RAN” 48–71; 2
nd
Action Closing Prosecution
“ACP” 28–73, 393–113 (April. 4, 2011).) We adopt the Examiner’s
findings with a modification to address concerns expressed by Rambus-Rea
about the Examiner’s reason for combining iAPX and Inagaki. See Rambus-
Rea at 1256. We do not adopt the Examiner’s findings to the extent they
conflict with our independent reading of the iAPX Manual and Specification
or findings in Rambus-Rea. We also address the evidence cited by Rambus-

9
As to the former holding, the Board stated that “Rambus fail[ed] to present
evidence that skilled artisans would have been unable to modify” the iAPX
system. (See ’171 Bd. Dec. 23–24.) The Board made that and a similar
statement under the impression that Rambus had the burden to show error
and to show inoperability. Rambus-Rea held that these statements constitute
legal error for improperly shifting the burden to Rambus. Rambus-Rea, 731
F.3d at 1255. Therefore, the Board herein removes all such statements, as it
attempted to do in the ’171 Remand Decision.
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Rea regarding objective evidence of nonobviousness to the extent it may
pertain to the claims here. See Rambus-Rea at 1256–58.
In making findings here, we note that Rambus-Rea stated that “[w]hile
the Board’s findings may ultimately be correct, we will not affirm a Board
rejection, like this one, which essentially provides a new motivation to
combine the references.” Id. at 1256. “To be clear, we are not passing
judgment on the merits of the Board's findings regarding the motivation to
combine.” Id.
Rambus only presents independent patentability arguments for claims
1 and 3. See App. Br. 2–26. Accordingly, these claims primarily are
representative of the claims on appeal. We also address tangential
arguments made by Rambus concerning claims 2, 18, and 30.
Rambus-Rea Factual Findings
Rambus-Rea summarized some pertinent facts as follows:
The following facts regarding Inagaki and iAPX are not
in dispute. Inagaki discloses a memory system that transmits
one bit during each half-cycle of the external clock. . . . The
half-cycle system disclosed in Inagaki is a modification of a
conventional full-cycle system. . . . Inagaki achieves the half-
cycle functionality by generating two clock signals based on the
rising and falling edge of the external clock. . . . The two
internal clock signals, in turn, synchronize the transfer of data
during the two halves of the system clock cycle. . . .
The iAPX manual and specification disclose a system
that transfers data based on the rising or falling edges of two
system clocks. . . . The system, however, utilizes the full clock
cycle for each data transfer. . . . Thus, because the iAPX
system employs a full clock cycle to transfer data to the
memory device, the system cannot use both edges of the clock
signal to synchronize the transfer of data portions to memory.
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However, Inagaki discloses a mechanism for converting a
conventional full-cycle system into a half-cycle system.
Rambus-Rea, 731 F.3d at 1251.
Some of the Board’s factual findings follow and are letter-numbered,
for later reference in this Remand Decision, as follows:
iAPX Manual and the iAPX Specification
10

A1. Figure 1-2 of the iAPX Manual follows:

Figure 1-2 depicts a memory module comprising a memory storage
array and a MCU (Memory Control Unit).
In the memory module, “[t]he storage arrays will typically be
constructed with high-density dynamic RAM (DRAM) components.” The
MCU within that module requires a “modest amount of external logic . . . to
interface the MCU to the storage array RAMs - - for simple configurations,

10
The Examiner and Rambus rely on the iAPX Specification, which
describes the same system as the iAPX Manual. (See App. Br. 21–22.)
They are deemed to be part and parcel of a single disclosure. See Rambus-
Rea, 731 F.3d at 1251(“The iAPX manual and specification disclose . . . [the
iAPX system].”)
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as few as 12 external TTL packages are required.” (iAPX Man. 1-4.) As
Figure 1-2 shows, the system may include one or more memory modules.
The BIU (bus interface unit) works in conjunction with a GDP
(general data processor) in a processor module. (iAPX Man. 1-1 - 1-3;
Fig. 1-2.) “The BIU is also responsible for arbitrating the usage of the
memory bus.” (iAPX 1-3.) It also “decides which memory bus(es) will be
used to form the [memory bus] access.” (Id.)
A2. The memory module constitutes “a memory confinement area.”
(iAPX Manual 1-8, 3-2.) The MCU “interfaces memory storage arrays to
the memory bus.” (Id. at 1-4.)
A3. A component level constitutes the lowest level of hardware in the
system, an example of which is a RAM chip. A module comprises a group
of interconnected components. (Id. at 2-1.)
A4. The iAPX system allows for “Modular System Expansion.”
(iAPX Spec. INTRO-7.) The presence or absence of any module does not
prevent communication between any other modules. (iAPX Man. at 2-6.)
The system isolates errors within each confinement area. (Id.)
The “Modular System Expansion” involves “three degrees of freedom
when designing, and later, expanding, an iAPX 432 system: Fault
Tolerance, Resource, Performance.” (iAPX Spec. INTRO-7.)
The iAPX Specification provides the following diagram to illustrate
the flexibility that system designers may exploit:
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(Id.) The diagram above indicates that minimal or no fault tolerance (which
includes some error correction), and virtually any number of memory
devices and processors, including one, may be employed: “The BIU and
MCU allow the iAPX 432 hardare to modularly and transparently extend the
processing power (from 1 to 63 modules of processors or memories), bus
bandwidth (1 to 8 backplane buses), and fault-tolerant capablities of the
system.” (iAPX Man. 1-2.)
Several functions, including error correction functions, are optional:
“Functional Redundancy Checking (FRC) . . . is an optional mechanism.”
(Id. at 1-11.) Many other functions are deemed “optional capabilities.” A
“register holds a set of bits that enable many of the optional capabilities in
the MCU and BIU components.” (Id. at 10-1.) Examples of optional
functions to disable: “Disable SLAD Bus FRC Detection,” “Disable MACD
Bus FRC Detection,” and “Disable ECC Error Reporting.” (Id. at 10-2.)
Errors are “detected and localized to a confinement area. . . . and
reported to all of the modules in the system.” (Id. at 1-6.) Error reporting
occurs on buses that are separate from the data buses. (Id. at 1-11, 1-12.)
Errors are constrained to memory confinement areas (i.e., modules). (Id. at
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1-6, 1-11, 1-12.) Normal data, address, and control information is “checked
by a pair of parity bits that are interlaced among the signals that they check.”
(Id. at 1-11.)
A-5. A block diagram of a simple, single memory module, iAPX
system, appears below:

(iAPX Spec., BIU-20.) The figure shows the MACD Memory Bus, at issue
here, connected to the BIU and the memory module, which includes the
MCU (MACD interface) and the memory array, or DRAMs.
A-6. A diagram of the two clock (CLKA and CLKB) waveforms that
drive the MCU memory module and BIU above, appears next:
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(iAPX Spec., MCU-39.) As seen above, the two clocks differ in phase by
90 degrees. Each of these two clocks has rising and falling edges that
govern the timing of a variety of transactions of the multiple bus iAPX
system. (See, e.g., iAPX Spec., MCU-36, BIU-38 (listing the various
transactions timed to the falling and rising edges of the two clocks, CLKA,
CLB).)
For example, the MCU and the BIU output data onto the MACD
“Memory Bus” at rising CLKB edges. (iAPX Spec., MCU-13, MCU-36,
BIU-38.) Both devices, the MCU and the BIU, input data or other signals
from the MACD bus on rising CLKA edges. The BIU also drives and
receives data from the processor on the ACD bus. (See MCU-36; BIU-38.)
Single Chip and Controller
Rambus disagrees with the Examiner’s finding that the iAPX memory
module reads on the claimed “synchronous memory device” because it is not
a single chip. (Rambus Appeal Br. 3–4 (footnote omitted, citing Murphy
Decl. ¶¶ 21, 68–80.) Subsequent to the filing of Rambus’s Briefs, the
Federal Circuit decided against Rambus regarding this same claim term in
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claim 18 of related U.S. Patent No. 6,034,918 to Rambus (“’918 patent”). In
re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) (holding that the claimed
“synchronous memory device” is not limited to a single chip, and the iAPX
Manual anticipates claim 18 there, affirming the Board’s decision in Ex
parte Rambus, Appeal No. 2011-011178 (BPAI 2011) (Reexamination
Control No. 90/010,420)). Rambus’s arguments essentially reduce to the
single chip argument, which In re Rambus dismissed as incorrect based on
similar arguments, evidence, and prosecution history. (See Rambus Appeal
Brief 2–16.) The patent involved in In re Rambus claims continuity to the
same application (App. No. 07/510,898) as the ’937 patent.
11
See Gemalto
S.A. v. HTC Corp., 734 F.3d 1364, 1371 (Fed. Cir. 2014) (applying same
claim construction to patents deriving from common application).
Rambus did not pursue this single chip argument before the Federal
Circuit in Rambus-Rea. If Rambus pursues the argument, to the extent In re
Rambus does not control the issue for some reason, we hereby adopt and
incorporate by reference our previous Decision in this case, which addresses
this issue under the heading of “Single Chip.”
12
We also adopt and

11
See Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1084-1086,
1091-1092 (Fed. Cir. 2003)(noting that the written descriptions of each of
four related Rambus patents, 5,954,804; 5,953,263; 6,034,918; and
6,032,214, are substantially identical to the written description of the
07/510,898 application to which they, and the ’937 patent here, each claim
continuity).
12
We effectively strike and do not incorporate the following sentence on
page 15 of the prior Decision as misleading or inaccurate: “While entirely
unnecessary to the holding, claim 18 in the ’937 patent shows that even
Rambus considers the term ‘memory device’ to be a generic term which
includes a “memory controller device” and thereby embraces at least three

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incorporate by reference or ’171 Remand Decision at pages 13–15, which
similarly addresses the same issue under the heading of “Single Chip
Argument.”
As In re Rambus decided, the “synchronous memory device” recited
in claim 18 there reads on the iAPX “memory module,” and the “bus
controller” reads on the iAPX BIU. (See A1-A3 (factual findings from the
iAPX Manual).)
Claim 18 from the ‘918 patent at issue in In re Rambus follows:
18. A method of operation of a synchronous memory device,
wherein the memory device includes a plurality of memory
cells, the method of operation of the memory device comprises:
receiving an external clock signal;
receiving first block size information from a bus
controller, wherein the first block size information defines a
first amount of data to be output by the memory device onto a
bus in response to a read request;
receiving a first read

request from the bus controller; and
outputting the first amount of data corresponding to the
first block size information, in response to the first read request,
onto the bus synchronously with respect to the external clock
signal.

(See In re Rambus at 44; Farmwald et al., U.S. 6,034,918 (Mar. 7, 2000).)

Claim 1 here recites a “method of controlling,” but does not recite a
“bus controller” as claim 18 in In re Rambus does. Claims 18 and 30 here

species: memory chip devices, memory stick devices, and “memory
controller device[s].” Although it is correct that a memory device includes
control functions and a memory control unit (MCU), as In re Rambus holds,
claim 18 recites a separate memory controller and memory device (which
itself may include some memory control functionality).
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recite a “controller device” and a “memory controller device.” According to
the logic and holding of In re Rambus, which coalesces with the Examiner’s
findings, the iAPX Manual discloses the method of controlling and
controllers recited here, with the controllers reading on at least the iAPX
BIU (bus interface unit), or, the BIU and the processor as a controller
module. (See A5.)
Similar to the holding and findings in In re Rambus, the Examiner
finds the MCU to be a synchronous interface to memory module arrays in
the iAPX memory module; therefore, the iAPX memory module constitutes
the memory device recited in the claims on appeal. (See A1; RAN 53–54.)
The Examiner also finds data to be sent synchronously with respect to rising
clock edges. (Id.)
Rambus’s argument, that the iAPX “asynchronous DRAM devices do
not receive a clock signal and are incapable of sampling an operation code or
outputting data in response to an operation code,” is a form of the single chip
argument dismissed by In re Rambus. (App. Br. 2.) In other words,
Rambus’s argument focuses on what each DRAM chip in the iAPX memory
module receives, and does not dispute that the MCU interface, which is part
of the memory module/device, receives the clock signal. (See A1, A5.)
Apart from the single chip issue, Rambus does not contest the
Examiner’s finding that the iAPX memory module and BIU/processor
controller module satisfies the other limitations of claim 1 including,
external synchronous clock signals CLKA or CLKB, operation codes
(within packets on the iAPX MACD bus), and outputting and sampling data
in response thereto. (See App. Br. 2; RAN 98–99; ACP 95–97; Non-Final
Office Action 29 (August 5, 2010).)
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Rambus does not present separate patentability arguments with
respect to claims 18 and 30, which recite, respectively, “[a] controller device
for controlling, the controller device for controlling,” and “[a] method of
operation of a memory controller device.” Addressing how the iAPX
memory module constitutes a memory device, and the method of controlling
or the controller in claims of claims 1, 18, and 30, the Examiner finds that
the iAPX BIU is an external controller that sends and receives data packets,
and an operation code, synchronously to and from the memory module’s
MCU. (See, e.g., Non-Final Office Action “NFOA” 28–45 (Aug. 5, 2010);
A1, A5 (showing a GDP processor and BIU as a processor module); ACP
97, 102–105, 108–110.) The Examiner also finds that BIU pins
corresponding to MACD0 through MACD15 constitute or imply “input
receiver circuitry” on the controller recited in claim 18. (See NFOA 37
(citing to the BIU and/or processor as a controller that sends operations
codes and memory access to the memory device MCU); ACP 102–105,
108–110.)
In other words, the Examiner generally reads the controller limitations
onto devices or functions issued “external from the memory module of iAPX
Manual” (RAN 51)––devices such as the iAPX BIU or the GDP processor,
or the module including both, which control error correction and data flow to
and from the memory modules. This comports with In re Rambus’s holding
that the BIU constitutes a controller. See In re Rambus at 50–51 (holding
the iAPX BIU is an external bus controller; (accord supra A1, A2, A4, A5,
(the iAPX BIU and GDP is a controller module); ACP 95–97, 102–105,
108–110). As noted, apart from advancing the single chip argument,
Rambus does not dispute the Examiner’s findings.
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Although Rambus maintains that iAPX does not disclose “issuing a
first operation code to a memory device,” as claim 1 recites and as claim 30
similarly recites, and “output driver circuitry to provide an operation code to
the memory device,” as claim 18 recites (Rambus App. Br. 15), Rambus
reasons that “the bus interface unit [BIU] provides what is alleged to be [the
claimed] information to the memory control unit [MCU], which as discussed
above, is a memory controller, not a ‘memory device’, or part of a ‘memory
device.’” (Id. at 15–16 (emphases added).) These arguments constitute
another form of the single chip argument dismissed by In re Rambus. As
explained above, the iAPX MCU is part of the memory module/device in
iAPX (i.e., the memory device of the claims). Rambus also maintains, in a
similar unpersuasive argument, that “the same [single chip] reasoning
applies to, for example, the ‘block size information’ recited in claim 2.” (Id.
at 16 (citing Murphy Decl. ¶¶ 61, 64).)
Rambus also argues that “[t]he memory control unit [(MCU)] also
performs functions that are associated with controllers, not memory devices,
such as fault tolerance, error checking, bus arbitration, and request queuing.”
(See App. Br. 15.) As indicated supra, In re Rambus considers and
dismisses similar arguments, which amount to another form of the single
chip argument. For example, Rambus argued to the Federal Circuit in In re
Rambus that “[a] person of ordinary skill would understand a memory
controller to perform functions such as ‘fault tolerance, error checking, bus
arbitration, and address queuing.’” (Rambus’s In re Rambus Appeal Brief
at 25.)
In re Rambus also agreed with the PTO’s characterization regarding
the similar interface functionality of the iAPX MCU and claimed memory
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device, i.e., the ’918 patent’s memory device “provide[s] at least the control
functionality necessary to enable the . . . [device] to interface with the rest of
the system, similar to how the MCU controls the array in the iAPX
Manual.” 694 F.3d at 49 (emphasis added). The Federal Circuit also noted
that Rambus referred to a BIU as a memory controller in its argument to the
Federal Circuit: “Rambus’s ‘argument for allowance [over Jackson] hinged
on the BIU—a memory controller— not being part of the claimed memory
device.’ Appellant's Br. 45 (emphasis in original).” In re Rambus, 694 F.3d
at 49 (quoting Rambus’s Appellant’s Brief in In re Rambus).
Rambus acknowledged the Board’s decision in Ex parte Rambus
(affirmed by In re Rambus), and characterizes it as follows: “In that
decision, the Board affirmed the Office’s overly broad construction of
‘memory device.’ Rambus is appealing that decision.” (Rambus App. Br. 3,
n. 3.) This statement implies that In re Rambus controls; the iAPX Manual
discloses the controller and memory device limitations of the claims here.
Rambus does not guide the Board with a principled argument for
distinguishing over the holding in In re Rambus. In particular, Rambus does
not distinguish the common terms “synchronous memory device” or
“controller,” as described in the common predecessor application to the ’918
patent and the ’937 Patent.
Considering the holding of In re Rambus, which controls the “single
chip” and “controller” limitations of the claims, in light of the Examiner’s
independent findings and findings in our prior Decision, Rambus does not
show error in the Examiner’s finding that the iAPX memory module
constitutes a memory device as recited in the claims.

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II. Dual Clock Edges or DDR (Double Data Rate)
Background
As indicated above, representative claim 1 in the ’937 Patent mirrors
claims 1 and 2 in the ’097 patent held to be anticipated by Inagaki in
Rambus-Rea. At issue for the alternative obviousness rejection involving
the combined teachings of iAPX and Inagaki, claim 1 requires data sampling
on rising and falling clock edges, or dual edges of an external clock to
double the data rate (DDR): “sampling the first portion of data
synchronously with respect to a rising edge transition of an external clock
signal; and sampling the second portion of data synchronously with respect
to a falling edge transition of the external clock signal.”
Prior to Rambus-Rea, Rambus argued in that proceeding, as in this
proceeding, that using Inagaki’s clocking scheme in the iAPX system would
not have been obvious because Inagaki uses shift registers and a non-
periodic pulse, as opposed to an external clock. (Rambus App. Br. 18.)
The anticipation holding of Rambus-Rea with respect to claims 1 and 2 (and
other claims) in that case addresses and dismisses Rambus’s argument that
Inagaki does not disclose a periodic external clock: “The Board held that the
‘external clock signal’ only requires the clock to be periodic during the data
input phases, as opposed to being periodic for all system operations. . . .
[W]e conclude that the Board properly construed the term ‘external clock
signal.’” Rambus-Rea at 1252–1253.

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Inagaki’s Teachings
I1. Inagaki describes increasing data transfer rates in “block access
memory” devices: “the demand is increasing to have higher speeds even for
MOS RAM.” (Inagaki 2.) As further background, Inagaki explains that
conventional methods to increase data transfer rates in RAMs [random
access memories] included increasing the “bit width (a multi-bit structure),”
which adds to the cost of packaging, by “increas[ing] the number of pins,” or
“increas[ing] the data transfer rate.” (Id.) Adding memory device pins
(which increases bus width) also prevents integration due to the increased
size. (Id.)
Inagaki’s solution doubles the data rate by using the rising and falling
edges of an external clock (i.e., without increasing the clock rate, data bus
width, or pin count): “The rise and fall of external clock φ are detected, and
clocks φ1 and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the
shift register. . . . In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed.” (Id. at 4.)
I2. Inagaki’s system performs “data input or output every half-cycle
based on an external clock.” (Id. at 2.)
I3. Inagaki improves upon conventional methods in terms of speed as
follows: “In order to overcome this problem, the present invention presents
block access memory that transfers data with a speed that is twice the
conventional speed, by performing I/O [input/output] of data on every half-
cycle of the external clock that drives the I/O shift register.” (Id. at 3.)
I4. Inagaki also specifically refers to synchronous operation: “Clock
φ1 is generated synchronously with the external clock φ.” (Id. at 5.)

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Employing Inagaki’s Dual Edge
Clocking Concept in the iAPX System
Combining iAPX and Inagaki
Rambus directs attention to claims 1 and 3. As Rambus-Rea and our
prior decisions discuss, the Examiner relies on Inagaki to suggest modifying
the iAPX system to include providing first and second data portions on
rising and falling clock edges, often referred to as DDR (double data rate).
(See RAN 56–64.) Following the holding and logic of In re Rambus, a
“synchronous memory device” reads on the iAPX memory module and the
controller or method of controlling reads on the BIU (or processor module).
The iAPX memory module includes a memory control unit (MCU) and
numerous DRAM chips. (See supra A1-A3 (factual findings from the iAPX
Manual).) The MCU (and the BIU) receives two clock signals, CLKA and
CLKB, to control data and other signals. (See A5–A6.)
Rambus primarily argues that it would not have been obvious to
modify the iAPX system so that it uses DDR as Inagaki teaches. (See App.
Br. 18–23.) There is no dispute that this DDR technique was well-known, as
Inagaki proves and as Rambus-Rea held (for example, by holding that
Inagaki anticipates ’097 patent claims 1 and 2).
Rambus asserts that a DDR modification to the iAPX system would
have been too complex or would have rendered the iAPX system inoperable.
To support these theories, Rambus alleges that the buffer direction control
required in the iAPX system precludes DDR. (Rambus Reb. Br. 9.)
Rambus also alleges that the iAPX timing system shows that data on the
MACD bus, output by the MCU must be held for at least one full CLKB
cycle by the BIU in iAPX. (See App. Br. 20–22 Reb. Br. 8.) According to
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Rambus, using DDR also would corrupt the data for various reasons. (See
App. Br. at 25–28; Supp. Murphy Decl. ¶ 113.) Rambus also asserts that
secondary considerations show unobviousness. (See App. Br. at 25–28.)
Rambus made the same arguments in its Federal Circuit appeal brief
in Rambus-Rea, correctly noting that “iAPX discloses using the rising and
falling edges of both of its clock signals for purposes other than double data
rate (only one edge of one clock signal is used for data transfer.)” (Rambus-
Rea Fed. App. Br. 33.) There is not dispute that the iAPX system uses two
clocks, CLKA and CLKB. (A6.)
Buffer Directional Control
Alleging inoperability of the Examiner’s proposed DDR modification,
Rambus argues that “[s]everal pieces of information are carried on both edges
of both [iAPX] clocks, including buffer directional control.” (Rambus-Rea
Fed. App. Br. 34 (emphasis added).) According to Rambus, this buffer control
renders “both edges of both clocks . . . necessary for the operation of the iAPX,
[and] they cannot be used to add [DDR].” (Rambus-Rea Fed. App. Br. 34.)
The record does not support Rambus’s arguments. Contrary to
Rambus’s representation in Rambus-Rea, clock edges do not “carr[y]” any
information. Rather, the clock edges trigger actions or data transfers that carry
information. The iAPX Manual explicitly shows that a clock edge triggers
more than one action on multiple buses. For example, the rising edge of CLKA
triggers several different inputs to and/or outputs from different pins on the
MCU: MACD15, CTL2, CHK1, MBOUT, INIT, ABCHK. (See iAPX Spec.,
MCU-36, A-6.) The clocks also trigger multiple actions in the BIU and on
different buses. (See BIU-38 (ACD and MACD bus).) The Examiner similarly
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finds that the “iAPX Specification discloses . . . various inputs and outputs that
occur during different transitions of the clock.” (RAN 59.)
Rambus also maintains that “if both rising and falling edges of CLKB
were modified to be used for data transfer instead of directional control, the
memory control unit would not be able to reconfigure its actions from reading
data to writing data or “vice versa.” (Fed. Br. 34.) According to Rambus,
“‘buffer directional control’ occurs between data transfers and is used to
configure the memory control unit to either receive data or output data.” (Id.)
First, these arguments imply incorrectly that CLKB is used for buffer
directional control. To the contrary, CLKA triggers MBOUT for directional
control. (See MCU-36.)13 Second, contrary to the argument, as noted above,
the clock edges do not carry information; therefore, each clock edge can be
used to trigger more than one function.
Third, the arguments incorrectly imply that buffer directional control
must occur between every data transfer. In the ’171 proceeding, Mr. Murphy
states that the iAPX system (as disclosed in Budde) “provides for buffer
directional control between each data transfer.” (’171 Murphy Supp. Decl.
¶¶ 23.) Rambus’s position is misleading, because the record does not support
the notion that buffer directional control must be asserted between each data
transfer––even if it “provides for” it when necessary. No directional control
assertions occur for data transfers in one direction––the transfers at issue here:

13
Rambus does not explain how CLKB controls buffer directional control.
MCU-13 states that some waveform diagrams incorrectly show clock
triggers on the wrong clock edge: “The MCU actually sources MACD
information on the rising edge of CLKB.” (MCU-13.) Therefore, MCU-36,
which verifies that MCU sources data on the rising CLKB edge and CLKA
triggers MBOUT, controls on this record (as does BIU-38).
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The iAPX Specification discloses that an “MBOUT signal controls the
direction of external buffers for the MACD, CHK, and CTL signals. When
MBOUT is asserted, it indicates that external buffers must be directed to carry
information outbound from the component [i.e., the BIU or MCU] to the
memory bus.” (iAPX Spec., BIU-5; see also BIU-17.) The phrase “when
MBOUT is asserted” shows that it is not asserted at every CLKA signal.
Logically, as iAPX discloses, “MBOUT remains asserted” when data flows in
one direction, such as a write for “two double-bytes.” (iAPX Spec., BIU-19;
see also BIU-16 (MBOUT asserted in cycle 5 in a 4Byte Memory Read).)
The Examiner made similar findings, addressing Rambus’s arguments
and Mr. Murphy on this point. (See ACP 58–62.) The Examiner concludes by
adopting Requester’s position and concluding: “The fact that the MBOUT
signal remains asserted is depicted in the timing diagrams at pages BIU-18 and
BIU-20. Therefore, Rambus’s assumption that the buffer direction control
must transition between each data transfer is false.” (ACP 62.) The Examiner
also finds that MBOUT (and arbitration) is asserted on different data lines (not
the MACD bus) and used to “merely set up the subsequent transmission of read
data”––in this case, two bytes of data without an intervening MBOUT signal.
(See ACP 60 (adopting NVIDIA’s showings, citing BIU-18).) The Examiner
concludes that buffer control triggered by CLKA would not render the system
inoperable if both edges of CLKB were employed to transfer data. (See ACP
59–62.) Mr. Murphy does not contradict these findings persuasively or discuss
MBOUT.
Rambus did not challenge the buffer directional control findings in its
Appeal Brief, but raised the issue in its Rebuttal Brief (Reb. Br. 9) and in its
Federal Circuit Brief in the ’171 proceeding, to allege inoperability. Such
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arguments are untimely and typically deemed waived. In the alternative, we
address them here in the event they somehow become an issue again.
Similar to the findings above, but in another context, the examiner in the
’171 proceeding finds that an operation code “instructs the memory device to
input the amount of data . . . from the MACD bus.” (’171 RAN 53.) The
examiner also finds, with respect to claim 4, there, that the “LLLL field
indicates the number of bytes of memory data to be transferred by a memory
device.” (’171 RAN 58.) The examiner similarly finds that the MCU accepts
variable length data requests. (’171 RAN 66 (citing iAPX Man. at 1-4).)
These findings further support the findings here that each CLKA does
not trigger a different direction between data blocks that have variable lengths,
because each long block flows in one direction on the MACD bus––without an
unnecessary buffer direction signal between each data byte of the block. The
record shows, as the Examiner finds, that MBOUT simply directs a
component’s buffer to change the data transfer direction at a CLKA edge. (See
iAPX Spec., MCU-5, 27, 36, BUI-5, 17, 18.) Therefore, contrary to Rambus’s
arguments, buffer direction control is not required each CLKB cycle. It follows
that using DDR in the iAPX system would not corrupt data simply because
buffer directional control is not asserted at each CLKB cycle.
Moreover, a block data direction signal triggered by any clock is so
trivial that Inagaki does not discuss it. As the Examiner finds, Inagaki provides
read/writes for a block data memory device at twice the conventional speed,
suggesting the modification in iAPX. (See ACP 53–55; RAN 52–53, 57; I1–
I3.) Inagaki constitutes further evidence, supplementing iAPX, that a data
direction signal logically is not required to be sent between rising or falling
clock edges.

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iAPX Flexibility
The evidence shows that eliminating some functions in iAPX to create
a simpler iAPX 432 system would have been obvious. The iAPX
Specification discloses that the system offers “expansion flexibility” and
“three degrees of freedom when designing, and later, expanding, an iAPX
432 system: Fault Tolerance, Resource, Performance.” (iAPX Spec.,
INTRO-7; accord A4.) Many functions are optional and can be disabled,
especially in a single module system. (See A4.) Inagaki teaches, and iAPX
at least suggests, that all the iAPX functions need not transpire in a simple
single memory module using one clock or two clocks.
14
(See A4.)
For example, the iAPX Specification provides the following diagram
to show the flexibility in the system:

(Id.) The diagram shows that fault tolerance can be zero or high, as
required. Flexibility specifically includes one memory module: “The BIU

14
No functions need to be eliminated under two proposed modifications that
employ both iAPX clocks, especially in simple single module systems
contemplated by iAPX and disclosed by Inagaki. Although, as noted further
below, there is nothing to arbitrate and no error reporting when there is only
one memory module, suggesting these functions are not necessary.
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and MCU allow the iAPX 432 hardware to modularly and transparently
extend the processing power (from 1 to 63 modules of processors or
memories, bus bandwidth (1 to 8 backplane buses), and fault-tolerant
capablities of the system.” ( iAPX Manual, 1-2; accord A1, A4.)
Therefore, the record shows that the iAPX system can be modified
essentially to be as simple as Inagaki’s system––with a single memory
module and BIU/processor and a single backplane bus between the BIU and
MCU (i.e., the MACD bus, see A5). As the chart and disclosures imply or
suggest, all iAPX functions are not necessary, especially for a single
memory module and single BIU system. For example, the iAPX system
implies or suggests that arbitration between modules or error messaging
between modules does not transpire with one only one module in the system.
(See A4.) For example, the BIU “arbitrate[s] the usage of the memory bus.”
(iAPX Man. 1-3.) In one example, two processors/BIUs arbitrate for the
same memory module. (iAPX Spec., BIU-36.) This implies, logically, that
one processor/BIU need not arbitrate for MACD memory bus usage with a
single memory module. Simply, there is nothing to arbitrate in a single
processor and single module system.
Similarly, a single memory module system does not report an error to
other nonexistent modules. (See A4.) As another example, multiple access
read or writes, with interleaving, would not be required for a single module.
(See iAPX Spec., BIU-25 (showing two modules for multiple access).)
Inagaki does not employ, or discuss, arbitration, multiple access, and error
checking or reporting in its simple system, further showing that system
designers knew these functions were unneeded in simple systems (or that
they involve trivial modifications that do not warrant discussion). The
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claims do not require any of these functions. Even if an iAPX designer
would have desired some error correction in a flexible single module APX
system, iAPX provides for that as part of the normal data flow pursuant to
the normal clock edges: normal data, address, and control information are
“checked by a pair of parity bits that are interlaced among the signals that
they check.” (iAPX Manual, 1-11.)
Shift Registers
Rambus also maintains that using Inagaki’s clocking scheme in the
iAPX system would not have been obvious because Inagaki uses shift
registers, the iAPX system uses dual edges of two clocks for other specific
functions, the clock is not periodic, the clock is not external, and Inagaki had
other concerns. (See Reb. Br. 5–7; App. Br. 17–21.) These arguments
reduce to the unpersuasive assertion that the two systems must be bodily
incorporated. See In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) (“[I]t is
not necessary that the inventions of the references be physically combinable
to render obvious the invention under review.”); In re Nievelt, 482 F.2d 965,
968 (CCPA 1973) (“Combining the teachings of references does not involve
an ability to combine their specific structures”).
Moreover, Rambus-Rea held that Inagaki anticipates claim 1 in that
case, which essentially recites using an external DDR clock to control a
synchronous memory device, contrary to Rambus’s assertions. Ordinarily
skilled artisans would have recognized that Inagaki teaches that data bus
systems, especially flexible systems like iAPX, can provide data on a bus
using DDR in order to transfer data at twice the normal speed without
increasing the clock rate or the pin count. (See I1–I3.) “The Examiner notes
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that Inagaki supports the fact that it was well known to transfer data on the
rise and fall of a clock signal.” (RAN 99.)
Rambus’s allegation that Inagaki’s shift registers render unobvious
using DDR in the iAPX system ignores the agreed-upon fact that the iAPX
system already employs dual clock edges to control multiple buses without
using shift registers. Therefore, contrary to Rambus’s assertions, artisans of
ordinary skill would have understood how to implement the known DDR
feature to maximize speed, whether shift registers were employed or not. In
other words, as the Examiner reasons, the fact that iAPX uses rising and
falling edges of two clocks to transfer all manner of data or signals means
that iAPX already has the circuitry available to send/receive data on both
edges without a shift register. (See RAN 57.)
Motivation/Rationale/Simplicity/Skill Level
As stated, Inagaki provides good reasons to modify a system to use
both clock edges: Inagaki’s system allows the BIU and MCU to “operate at
twice their specified speed”(RAN 57), “rather than speed[ing] up the clock
or increase[ing] the pin count to improve bandwidth” (RAN 99 (citing
Inagaki 2); I1–13)). “[I]f a technique has been used to improve one device,
and a person of ordinary skill would recognize that it would improve similar
devices in the same way, using the technique is obvious unless its
application is beyond his or her skill.” KSR Int’l Co. v. Teleflex, Inc., 550
U.S. 398, 417 (2007) (citation omitted).) The record shows that using the
technique is not beyond the skill level involved here.
Inagaki’s teachings, and the iAPX use of dual edges, evidence a
reasonable expectation of success in using dual clock edges on data for
increased speed. Increased speed and compactness by reducing bus width
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and corresponding pin number while saving cost, without changing the clock
speed, as Inagaki specifically teaches (see I1–I3), constitute universal
motivators. Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H.
Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit
motivation to combine exists … when the ‘improvement’ is technology-
independent and the combination of references results in a product or
process that is more desirable, for example because it is stronger, cheaper,
cleaner, faster, lighter, smaller, more durable, or more efficient.”)
Despite Rambus’s related arguments that the proposed modification
would have rendered the iAPX system nonfunctional, the Supreme Court
stated that “the interaction of multiple components means that changing one
component often requires the others to be modified as well.” KSR, 550 U.S.
at 424. In other words, as KSR implies, making other required modifications
to increase the data speed by using both clock edges, as Inagaki teaches (I1–
I3), does not defeat obviousness or show inoperability.
Exploiting the flexibility in the iAPX system to create a simple single
module system, with a single bus, as a standard option, would have been
obvious in order to create a fast, simple system. (See A4; I1–I3.) Rambus’s
evidence also shows that skilled artisans knew how to modify the use of both
clocks in iAPX system. For example, Mr. Murphy testifies that Budde
employs the iAPX system, and that in Budde, “MACD[15:0] is driven and
sampled with CLKB rising.” (’171 Murphy Decl. ¶ 127; accord Budde, col.
7, ll. 16–17.) On the other hand, the iAPX Specification shows that, unlike
in Budde, the iAPX MACD data bus is sampled (by the MCU and BIU) on
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rising CLKA edges, and like Budde, driven with CLKB rising (driven by the
MCU and BIU). (See iAPX Spec. MCU-36, BIU-38).
15
The iAPX system
is designed to be altered (A4), and Budde shows designers exploited that
flexibility and altered the clocking scheme.
In addition to these designer implemented changes to the clock
system, according to the iAPX Specification, the system allows designers to
vary the clock pulse width and the clock cycle time across a wide range.
(See iAPX Spec., BIU– 40.) The Examiner made similar findings: “While
the adoption of dual-edge clocking would have required changes . . . such
changes would clearly have been within the skill of a person having ordinary
skill in 1990.” (RAN 63.) The record, including the iAPX Manual, Inagaki,
and articles cited by Rambus, shows that artisans in the field of memory
systems were skilled at a relatively high level in the field of memory systems
and devices. Mr. Murphy testifies that a skilled artisan would have had a
BSEE degree and 3–5 years of experience in designing memory circuits
Rambus such as DRAMs. (Murphy Decl. ¶ 4.)
Rambus essentially argues that such ordinarily skilled artisans could
not have simplified or altered the iAPX system that was designed to be
altered and flexible. Budde and the iAPX Manual contradict this argument.
The flexibility provides for reducing the number of modules to one memory
module (out of 63), as noted. (See A-4; iAPX Manual 1-2 (“A system with
one processor and one memory may be built with a single memory bus.”).)

15
Rambus agrees that the iAPX system functions as noted: “The data is
output on the MACD bus based on the rising edge of CLKB and sampled
based on the rising edge of CLKA.” (Reb. Br. 12; accord A6.)

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Reducing the number to one memory module on a single memory bus
eliminates the need to arbitrate and report errors between modules, as iAPX
and Inagaki each suggest, as discussed above. (See A4.)
Moreover, Mr. Murphy admits that the iAPX designers “knew they
could use both edges of a clock signal–but chose not to,” but maintains this
knowledge shows a teaching away from “the [modification] proposed by the
Office.” (’171 Murphy Supp. ¶ 23 (emphasis added).) Mr. Murphy’s
statement contradicts Rambus’s argument that the use of DDR would create
a nonfunctional device. Skilled artisans knew how to send data on both
clock edges (i.e., employ DDR), as Inagaki proves and Mr. Murphy verifies.
This statement also contradicts other unsupported testimony by Mr. Murphy,
such as “[t]rying to force the circuitry to go twice as fast would have caused
the system to fail.” (Murphy Supp. Decl. ¶ 10.) Mr. Murphy fails to provide
evidence as to why a circuit that accepts or handles multiple clock edges and
has variable speed capability would fail when the clock speed itself does not
change.
In any event, a decision not to use both CLKB edges for data transfer
does not teach away from using them for that purpose. Skilled artisans
would have recognized that the iAPX system does not need two clocks as
Inagaki teaches. The two iAPX clocks provide for expansion of multiple
module systems with further flexibility for fault tolerance and multiple
buses, which suggests no need for two clocks in a single memory module
system. (See A4.) See In re Sovish, 769 F.2d 738, 743 (Fed. Cir. 1985)
(“This argument presumes stupidity rather than skill.”); In re Kuhle 526 F.2d
553, 555 (CCPA 1975) (deleting a prior art “switch member (and other
elements) . . . thereby deleting their function, was an obvious expedient.”);
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In re Larson, 340 F.2d 965, 969 (CCPA 1965) (obvious to eliminate “a great
deal of additional framework,” including an additional axle, which “serve[] a
particular purpose in that it increases the cargo carrying capacity,” if the
structure and its function are not desired.)
Single Clock
A single clock for a single memory module, as Inagaki teaches, would
create a “cleaner” iAPX memory device for handling data transfers at twice
the normal rate without changing the clock speed or increasing the pin count.
Making a device “cleaner” (i.e., simpler) constitutes a universal motivator
under Dystar. Inagaki also implies that memory devices function without
arbitration, error correction, or two external clocks, and the iAPX system
similarly teaches simple and flexible single memory device systems that do
not require all disclosed error correction reporting and other functions.
Claims 1, 3, 18, and 30, do not have significant interrelated features
other than those required to sample or transfer data. The obviousness
inquiry must focus on the claim breadth. Given the claim breadth, skilled
artisans could have modified the iAPX system in view of Inagaki’s clocking
scheme. Some of the functions either could have been dropped, or triggered
on a different clock edge and retained, because each edge can govern more
than one control signal, as explained above and further below. (See iAPX
Spec., BIU-38, MCU-36, listing multiple actions triggered by the two clock
edges of CLKA and CLKB.)
Device Limitations
Despite Rambus’s arguments about existing device limitations based
on speed (see Supp. Murphy Decl. ¶¶ 9–10 discussing 10 MHz operation),
faster memory devices than those disclosed in the iAPX system would have
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been available at the time of the invention, in 1990. In addition, as noted
above, Mr. Murphy does not support, with probative evidence, the argument
that an MCU or BIU could not have handled both CLKB edges to transfer
data. The argument does not acknowledge that circuits in the MCU and BIU
handle the speed of intervening edges of CLKA and CLKB to handle
various signals and data. As Rambus notes, the BIU samples data on a
falling CLKA edge after the MCU outputs it on a rising CLKB edge. (Reb.
Br. 9.) Further, the clock speed would not increase under the modification:
instead of using a 20 MHz clock, both edges of CLKB would be used, at
10MHz.
As the Examiner finds, “[r]ather than speed up the clock or increase
the pin count to improve bandwidth (Inagaki at 2), Inagaki provides an
alternate solution wherein ‘the present invention presents block access
memory that transfers data with a speed that is twice the conventional speed,
by performing I/O at every half-cycle of the external clock.’” (RAN 99–100
(quoting Inagaki at 2).) Therefore, Rambus’s argument bolsters
obviousness, because as Inagaki suggests, any data rate, including the iAPX
data rate, doubles without increasing the (10MHz) clock speed, simply by
using both CLKB (or CLKA) edges to transfer data.
Clock as Trigger
Even if, somehow, the iAPX MCU could not have handled both
CLKB edges for data transfers, Inagaki suggests a simple clock triggering
(generating) solution. The iAPX clocks must be generated. The iAPX
system could have benefitted, at the time of the invention, from a slower
clock to generate or trigger the existing clock timing, as Inagaki suggests.
(See I1-I3; BIU-41.) Inagaki discloses a generating clock φ at Figure 4 for
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creating faster clocks φ1 and φ2. It would have been obvious to use a slower
clock’s rising and falling edges (e.g., clock φ) to trigger (generate) the
specific timing for CLKA and CLKB in iAPX as Inagaki suggests. In
Rambus-Rea, the court similarly found that Inagaki discloses a clock that
generates two faster clocks: “Inagaki achieves the half-cycle functionality
by generating two clock signals based on the rising and falling edge of the
external clock. . . . The two internal clock signals, in turn, synchronize the
transfer of data during the two halves of the system clock cycle.” Rambus-
Rea at 1251.
16
Under this triggering modification, the external clock’s rising
and falling edges would correspond to the claimed rising and falling edges,
and correspond to the existing rising edges of faster CLKB and/or CLKA.
In response to this position, Rambus argues that Inagaki does not
“explain how it is determined when φ1 should transition from high to low.”
(Reb. Br. 10; see note 19.) Despite this argument, Figure 4 of Inagaki shows
it transitions in relation to φ2 . Inagaki need not disclose how to keep the
clocks in their disclosed relationship to enable that relationship. The record

16
This modification would allow all CLKA and CLKB functions to be
retained without any modification except using a clock φ as a trigger to
CLKA and CLKB. In Inagaki, as the examiner recognizes, a slower external
clock φ has rising and falling edges corresponding to and triggering faster
clocks φ1 and φ2, suggesting a similar external clock to trigger the iAPX
CLKA or CLKB. (See e.g. Inagaki Fig. 4; I3, I4; ’171 RAN 37.) Inagaki
and iAPX both employ multiple clocks, suggesting such a combination.
The iAPX Specification heuristically illustrates this concept (which Inagaki
teaches as noted) by showing a slower “INIT” appearing to act as a clock
trigger signal with falling and rising edges corresponding to the faster CLKA
rising edges. (See BIU-41.)

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indicates that artisans of ordinary skill would have been able to understand
Inagaki’s clocking scheme. Inagaki’s clocking scheme is presumed enabled.
The iAPX Timing
Setting aside the simple triggering alternative, and addressing the
Examiner’s clock modification, Rambus argues, to support its inoperability
allegation, that the iAPX system requires holding BIU data on the MACD
bus over successive rising edges of CLKB, thereby precluding data transfers
on the falling edge between the two rising edges. (See App. Br. 21–22, Reb.
Br. 8.) Rambus maintains that the parameter TCD specifies how long it takes
MACD data “to actually show up” after a rising CLKB edge. (See App. Br.
22.) Rambus also maintains that the parameter TDH “shows how long the
data must be held after the next rising edge of CLKB to ensure proper
reception by the receiving device.” (Id.)
To illustrate its argument, Rambus attached the following slide in its
Rambus-Rea brief (A1710) (and employs a similar annotated figure in its
Appeal and Rebuttal Brief (App. Br. 22, Reb. Br. 8.)):
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According to Rambus, this timing diagram signifies what happens to
MACD data (shaded in the annotated chart). (See Office Action “OA” 21
(May 4, 2011 (citing MCU-38, MCU-41); App. Br. 22; RAN 61.) Rambus
also maintains that this annotated timing diagram corresponds roughly to
another timing diagram in the iAPX Specification for the MCU and MACD
outputs. (OA 21, iAPX Spec. MCU-36, MCU-38, MCU-41.)
17

Rambus’s reliance on the diagram is not clear, because regarding
claim 1, the Examiner reads the iAPX MCU as outputting data to a receiving
device such as the BIU. (See RAN 98–99.) Therefore, Rambus’s reliance
on the BIU output diagram confuses the issue. (See App. Br. 22.)

17
Apparently, according to Rambus, in the BIU-43 chart, the “ACD” data is
a misprint and should be MACD data. The Examiner accepts this. (See
RAN 61.)
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In any case, Rambus seems to argue that the diagram shows that the
BIU, which also samples data from the transmitting MCU, must hold data
for longer than 100nsec (the 10 MHz time period) in order to properly
receive it. (See id.) “Thus, while the data is output on the MACD bus based
on the rising edge of CLKB and sampled on the rising edge of CLKA, the
Bus Interface Unit is required to hold the data for a period of time past the
next rising edge of CLKB.” (Id.) This is confounding, because as the
statement acknowledges, the receiving device, in this case the BIU,
“sample[s data] based on the rising edge of CLKA.” (App. Br. 22.)
Because the BIU samples data on the rising CLKA edge, no logical reason,
other than conjecture based on an inapplicable BIU output diagram, supports
the argument that the BIU must hold data that it samples on a CLKA edge
until the next rising CLKB edge.
18
Nevertheless, according to Rambus, the
device hold time, TDH, shows that MACD data must be held by the BIU on

18
A modified Table from the iAPX Specification follows, and shows BIU
input and output CLKB and CLKA timing:

(iAPX Spec. BIU-38 (modified version by Board showing only ACD and
MACD).)
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the MACD bus for “approximately one cycle of CLKB,” thereby precluding
DDR, which would result in “corrupted data transfers.” (App. Br. 22.)
The iAPX Specification MACD BIU Input Timing Specification
diagram follows and shows that TDH specifies some type of delay when the
BIU receives data after the rising CLKA edge:

The diagram implies a delay of TDH of MACD data after the BIU
inputs data after a rising CLKA edge––not after a rising CLKB edge, as
Rambus argues.
19
(The BIU holds ACD input data after a rising CLKB
edge, not MACD input data).
20

A parallel diagram shows a similar delay with respect to input data of
the MCU.

19
It is not entirely clear why the diagram shows “MAC[D]” data for only
half a clock cycle.
20
Rambus’s annotated diagram chart above apparently signifies a hold time
for ACD data by a BIU receiving device, in that case, perhaps another BIU,
although it is not clear––because the diagram portrays BIU output timing
according to the legend. In any event, according to the iAPX Clock Edge
Table, a BIU receives ACD (not MACD) data on a rising CLKB edge.
(iAPX Spec. BIU-38, note 18.)

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(iAPX Spec. MCU-40). The timing diagram implies that the MCU samples
“MAC[D] (15-0)” data during a rising CLKA edge, which apparently, and
according to Rambus’s assertions, it must hold for a minimum amount of
time, TDH, to properly receive it (i.e., according to Rambus’s parallel
arguments). (See Reb. Br. 8; App. Br. 22.) In other words, after sending data
on a rising CLKB edge, the next rising CLKB edge occurs after the
intervening rising CLKA edge, and after TDH expires––after the MCU or
BIU samples the MACD data. (See A6.) Rambus appears to agree that
sampling occurs within three quarters of a CLKB cycle: “[t]he rising edge of
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CLKA is about three quarters of a clock after the falling edge of CLKB,
thereby showing . . . quarter-cycle granularity.” (Reb. Br. 9.)
The following MCU output timing diagram shows the relationship
between the two clocks (and output MACD data from the MCU after the
rising CLKB edge):

(MCU-41.) Note that this MACD Output Timing Specification for the MCU
does not show the sampling parameter TDH. (See id.)
The Examiner finds, and Rambus agrees, that “the data must be held
for approximately one complete cycle.” (RAN 62.)
21
The above diagrams
appear to show that MACD data transitions each clock period; however, this
does not mean the data must be held for a full clock cycle. Apparently, the
data may be held so that when some of the held data changes during a long
word or block transfer at each successive CLKB rising edge, minimal

21
The Examiner often repeats Rambus’s arguments, and it is not clear if the
Examiner agrees that the BIU “is required to hold the data for a period of
time past the next rising edge of CLKB,” or the Examiner merely repeats
Rambus’s position. (See RAN 62.) In any case, the Examiner concludes
that it would have been obvious to modify the iAPX system to double the
data speed or bandwidth.
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voltage changes would be required––only the data actually changing would
be altered, with other unchanged data lines staying the same. However, this
does not mean that the data must remain because of physical constraints on
devices, as Rambus argues. Logically, and as the record implies, transmitted
data must remain on the MACD bus until a device samples and holds it, but
then, it may or may not remain until the next clock trigger outputs more
data.
Moreover, if the MACD data is held for longer than a CLKB cycle by
adding TDH at the end of each cycle as Rambus argues, the system would not
transfer data at 10 MHz, which Rambus and Mr. Murphy assert is the
disclosed iAPX preferred data rate and clock rate. (See App. Br. 25 (arguing
that the iAPX cannot “support data transfers at 20MHz instead of the 10
MHz rate for which the system is designed”); Murphy Decl. ¶ 111 (“iAPX
teaches that the frequency of CLKA and CLKB is up to 10 MHz.”).)
Supporting the analysis by the Board, Rambus agrees that the MCU
and the BIU capture (sample) MACD data on the rising edge of the CLKA
cycle. The Examiner also agrees. (See RAN 62.) In summary, MCU
sampling occurs between rising CLKB edges––i.e., before a full CLKB cycle
transpires. Therefore, the THD parameter does not force the BIU to hold the
data received by the BIU (or the MCU) past the second rising CLKB edge.
(See MCU-36; BIU-38; BIU-43; Reb. Br. 9.)
Stated differently, if the data stays on the MACD bus after it is
sampled, that is not a system constraint––rather, it is by design. In
summary, the BIU/MCU writes data to the MCU/BIU on the MACD bus
during rising CLKB edges, and the MCU/BIU each sample the data on rising
CLKA edges. (See A5-A7; App. Br. 23.) This means that the BIU or MCU
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samples MACD data before the full CLKB cycle transpires (i.e., on the
rising CLKA edge in the middle of the CLKB cycle).
After that, the data need not be held necessarily, and would not be
held for THD as explained above. (As indicated above, a subset of the
parallel MACD data lines for a given long block plausibly may be (but are
not required to be) held until the BIU outputs new data for a long block––
because it is plausible that the iAPX system alters only the data line voltage
that subset of data that changes in successive bytes. (See RAN 59; iAPX
Spec., BIU-21, BIU-38, MCU-36, MCU-17, MCU-23 (showing different
bytes per clock cycle),
22
iAPX Man. 1–5 (variable length data of 1–16
bytes).)
Even if some constraints exist, Inagaki provides a reason for outputting
data on both rising and falling CLKB edges––to increase data transfer speed
without using a faster clock. The iAPX clock pulse widths (t1, t2, t3, t4), TDH,
and other values have disclosed ranges or minimums, implying that any
constraints may be accommodated by ordinarily skilled memory designers, as
the Examiner reasons. (See iAPX Spec., BIU-40; RAN 63 (supporting the
reasoning by finding that iAPX discloses that some data is “present on the bus
for only a half a clock cycle in order to provide stable data”).)
Rambus also argued in Rambus-Rea that the Examiner erred by
reasoning that both CLKB edges could have been modified to trigger other
actions, because, according to Rambus, that reasoning is based on the

22
As noted above, at least some of the figures involve “functional diagrams”
that depict CLKA for purposes of explanation, and iAPX explains that “[t]he
MCU actually sources MACD information on the rising edge of CLKB.”
(iAPX Spec., MCU-13.)
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Examiner’s erroneous finding that a CLKB rising edge is not used for
anything specific. See Rambus-Rea, 731 F.3d at 1254 (discussing
Examiner’s and Board’s fact finding about the rising CLKB edge). As
explained in the ’171 Remand Decision, the Examiner essentially relies on
the MACD bus, and asserts that the rising CLKB edge is not used for
anything on that bus. We refer to our ’171 Remand Decision to the extent
that becomes an issue here. In other words, CLKB is not used to trigger
anything on the relevant bus, MACD. But, even if it is, it can be used to
trigger any number of timing events.
Simple Modifications
According to the above timing discussion, iAPX and Inagaki suggest
two simple modifications that employ both iAPX clocks. In a first
modification, in a single MCU/BIU system, with an output by the MCU on a
rising CLKB edge, the same rising CLKB edge can be used to trigger
sampling that data by the BIU, as Inagaki and iAPX each suggest. The next
falling CLKB edge can be used to trigger the output of more BIU data, and
trigger sampling thereof by the MCU, as Inagaki also suggests, thereby
satisfying the DDR function recited in the claims.
23

23
According to Rambus and the discussion above, there would be a small
delay of TCD before the data appears on the line after which it must stay for
the minimum of TDH, for proper reception. Inagaki implies or suggests that
notwithstanding these small delays that are inherent in any device or
clocking scheme, receiving and transmitting data on the same clock edge
was routine. Also, in the iAPX system, the BIU inputs and outputs data on
the ACD bus on rising and falling CLKB edges. (BIU-38.) The BIU and
another processor connect to the ACD bus, suggesting that these devices
may use the same clock edges to input and output data. (See A4, BIU-20;

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Under this timing modification, CLKA could be used to time all of its
remaining disclosed functions (i.e., except sampling MACD data, which
would not be required). Recall that the iAPX system is flexible and
contemplates single module systems, and Budde employs the rising CLKB
edge differently than the iAPX system, showing that system designers knew
how to modify the use of the clock edges to time desired events in the
flexible system. The modification involves rearranging timing events,
something well within the realm of an ordinarily skilled artisan, adept at
modifying flexible systems, like the iAPX system, and relatively simple
systems, like the Inagaki system.
A second modification that also involves both clocks also involves a
mere rearrangement of timing, especially for small, single module, single
memory bus, systems. As explained above, the iAPX system employs the
rising CLKA edge to cause data sampling by the MCU or BIU on the
MACD bus. In light of the reason (speed, reduction of data lines) for using
DDR provided by Inagaki, and the flexibility of iAPX, ordinarily skilled
artisans would have recognized that the BIU could have used the falling and
rising CLKA edges to sample (input) data that the MCU outputs, under this
modification, on rising and falling CLKB edges. Therefore, in another
relatively minor modification to the iAPX timing scheme using both clocks,
the MCU can send data onto the MACD bus on a rising CLKB edge, the

A5.) Transmission delays are relative to transmission line lengths. One
module and one processer, disclosed by iAPX, obviously can be connected
by a bus with a length that could have been adjusted to accommodate for
known parameters such as TDH and TCD, by ordinarily skilled artisans, as the
Examiner essentially reasons. (See RAN 63–64.)
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BIU can sample that data on a falling CLKA edge, the MCU can send more
data to the MACD bus on a rising CLKB edge, and the BIU can sample that
data on the falling CLKA edge, and so on. (See iAPX Spec., BIU-38, BIU-
40, MCU-41.) (With respect to claim 30, the roles of the BIU and MCU
would reverse so that the BIU controller transmits to the MCU memory
device.)
This latter modification would not be impacted by TDH and TCD or
other constraints specified by Rambus (even if they must be considered by
an ordinarily skilled artisan). Under each alternative modification, Inagaki
suggests the fastest speed relative to a set clock speed or data bus width,
regardless of the rise times or data hold times, because speed ultimately is
triggered and governed by the two closest edges of any set of clock pulses.
In this case, if intervening sampling by CLKA is required, using both CLKB
edges provides the fastest speed possible for a given clock speed or bus
width. (See I1–I3; A4.) If one clock is employed, using both CLKB edges
provides the fastest possible speed.
With the exception of the proposed triggering alternative, the
proposed modifications effectively double the iAPX data rate from 10MHz
to 20MHz, without changing the clock speed. Even if some timing
constraints exist as Rambus argues, ordinarily skilled artisans also would
have recognized a trade-off, using a slower clock to accommodate any such
constraints, for example, an 8 MHz clock, and effectively creating 16MHz
data speeds. The record does not show that any appreciable constraints exist
for systems within the claim breadth in light of the skill involved, i.e., small
systems with short conductor lengths that have one or two memory modules,
like that of Inagaki or those suggested by iAPX.
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Other Arguments
Rambus’s remaining arguments are not persuasive. For example,
Rambus argues under a section heading “iAPX Does Not Disclose Other
Features Recited in the Claims,” that, with respect to claim 2, iAPX does not
disclose “block size information,” because “[t]he actual memory devices in
the storage array of iAPX never receive any block size information.” (App.
Br. 2.) This constitutes another form of the “single chip” argument, under
which Rambus assumes incorrectly that a “memory device” does not read on
the iAPX memory module. See In re Rambus, and Rambus-Rea (holding
otherwise). Rambus does not contest the Examiner’s finding that the MCU
in the iAPX memory module (i.e., a memory device) receives the block size
information. (RAN 76.) In addition, In re Rambus holds that iAPX
discloses block size information.
24

Claim 3
Rambus argues that the rejection of claim 3 should be reversed
because the “s” value relied upon by the Examiner is not the “programmed
amount of time” to determine when data is output on the MACD bus in the
iAPX system. (App. Br. 24.) Claim 3 recites “[t]he method of claim 1
wherein, in response to the first operation code, the first portion of data is
output after a programmed amount of time transpires.”

24
Anticipated claim 18 in related Rambus patent, U.S. Patent No. 6,034,918,
recites “[a] method of operation of a synchronous memory device . . .
outputting the first amount of data corresponding to the first block size
information.” In re Rambus, 694 F.3d at 43. The court found the claim
anticipated by the iAPX Manual. Id.at 51. Therefore, iAPX discloses block
size information.
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Rambus characterizes the issue as follows:
The Examiner agrees that the “s” value of iAPX does not
determine when data is actually output onto the MACD bus.
(RAN at 65.) However, the Examiner asserts that “[t]he claim
language reads on a scenario in which data is output anytime
after a programmed amount of time transpires” and “the claim
does not require the output to be responsive to the programmed
amount of time.” (Id.)
(Rambus App. Br. 23.)
Rambus’s contentions imply that Rambus agrees with the Examiner’s
reasoning that claim 3 literally reads on the iAPX system, because “in
response to the operation code, data is output . . . after a programmed
amount of time expires.” See id. (emphasis by Board). In other words, in
response to the operation code, claim 3 requires data to be “output after a
programmed amount of time transpires.” Rambus does not dispute that
sometime after the programed amount of time, s, the memory device MCU
outputs the first portion of data. (See Rambus Appeal Br. 23.) As the
Examiner reasons, claim 3 does not specify a certain amount of time or even
require the output to be responsive to the programmed time. (See RAN 65.)
Rambus focuses on the ’937 Specification, but that focus does not
show that any claim term carries a special meaning or that the Specification
somehow imparts a limitation that overcomes the modified iAPX system.
(See Rambus App. Br. 24.) Rambus’s citations show that claim 3 is broader
than the disclosure. Rambus relies on the following disclosures in the ’937
Patent:
“After a specified access time the slave(s) respond by returning
one or more bytes (8 bits) of data or by storing information
made available from the bus. More than one access time can be
provided to allow different types of responses to occur at
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different times.”. . . “To reduce the complexity of the slaves, a
slave should preferably respond to a request in a specified time.
. . . The time for this bus access phase is known to all devices
on the bus-each master being responsible for making sure that
the bus will be free when the bus access begins.”. . .
(See Rambus App. Br. 22–23 (quoting the `937 patent, emphasis supplied,
citations omitted).)
Rambus’s arguments imply that it relies on a preferred embodiment
that is not claimed––“a slave should preferably respond to a request in a
specified time”––i.e., immediately after the programmed amount of time
expires. However, claim 3 does not recite that “the first portion of the data
is output [immediately after] a programmed amount of time.” Similarly, it
does not recite that “the first portion of the data is output [in response] to a
programmed amount of time,” as the Examiner determined.
In In re Rambus, 753 F.3d 1253, 1258 (Fed. Cir. 2014) (“Rambus II”),
reversing the Board (which had reversed the examiner), the court construed
a more limited claim term in a related Rambus patent: “a value that is
representative of an amount of time to transpire after which the memory
device outputs the first amount of data.” Rambus II held that “[a] value
cannot ‘represent’ an ‘amount’ of time if there are additional factors, wholly
unrepresented by that value, that necessarily impact, or represent, the
‘amount of time.’” Id.
In this case, similar to Rambus II, Rambus argues that other
parameters, besides s, impact the timing. (App. Br. 23.) Nevertheless, the
Examiner distinguished the Rambus II claim term (that another Rambus
patent claim recites) from the instant situation: “[C]laim [3] does not require
the time to be representative of a number of clock cycles to transpire before
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data is output. In iAPX the ‘s’ value . . . does impose a delay that will
[cause] data to be output at a later time than it would if there was no delay.”
(ACP 63.)
Rambus does not dispute this finding or rationale by the Examiner.
Extending the recent reasoning in Rambus II may render the rejection of
claim 3 a close call. For example, we possibly could construe claim 3 as
requiring the memory device to respond to an operation code that has some
relationship to the programmed amount of time. However, Rambus
pointedly does not argue that the “programmed amount of time” in claim 3 is
dependent on the operation code. We hesitate to construe the claim in a
fashion that Rambus does not argue.
Further, claim 18 has parallel language that indicates that the
operation code is independent of what it triggers, i.e., synchronous outputs
governed by an independent clock. Claim 18 recites “in response to the
operation code, the memory device outputs first and second portions of data
synchronously with respect to a rising edge transition of an external clock
signal and a second portion of data synchronously with respect to a falling
edge transition.” In other words, the operation code instructs the device to
output data. After that, independent parameters control when the data is
output in claims 3 and 18.
The added limitations of claim 3 read on the iAPX system. “[I]n
response to the iAPX operation code, data is output [by the MCU] . . . after a
programmed amount of time [s] expires.” Rambus does not show error in
the Examiner’s determination.

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Summary
Rambus’s arguments and secondary considerations of non-
obviousness, considered together, do not outweigh the Examiner’s showing
of obviousness, including responses to the secondary considerations. (See
RAN 66–72.) Based on the foregoing discussion and the discussion below
regarding secondary considerations, Rambus has not shown error in the
Examiner’s decision to reject claims 1–3, 8, 10–16, 18, 23–30, 36–38, and
40. As such, it is not necessary to reach the Budde based rejection. Cf. In re
Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness
after finding anticipation).
Secondary Considerations
Objective Evidence of Nonobviousness
1. Background
Rambus alleges secondary considerations of licensing, long-felt need,
failure of others, skepticism, commercial success, and praise by others, as
rebuttal to the obviousness finding by the Examiner regarding the claims in
general. (App. Br. 24–30.) Rambus focuses on claim 1, with a single
argument directed to claim 3, implying that claim 1 and perhaps claim 3 are
coextensive with the asserted evidence of nonobviousness. (App. Br. 24).
See Brown & Williamson Tobacco Corp. v. Philip Morris Inc., 229 F.3d
1120, 1130 (Fed.Cir.2000) (stating the presumption that commercial success
is due to the patented invention applies “if the marketed product embodies
the claimed features, and is coextensive with them”) (emphasis added).
According to the finding above, Inagaki anticipates claim 1. Even if
Inagaki does not anticipate claim 1, Rambus relies on the operation code
recited in that claim, a feature that Inagaki and the iAPX Manual discloses.
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Rambus maintains that “the alleged operation codes are provided to the
memory control unit” and “are not sent to the memory devices in the storage
array.” App. Br. 23. This argument shows that Rambus relies on the “single
chip” theory to show a nexus to its secondary evidence of nonobviousness.
(See App. Br. 23.) The claims do not require a single chip memory devices,
as In re Rambus and Rambus-Rea make clear. Rambus has failed to meet its
burden of showing nexus to a single chip memory device that produces the
touted speeds that Rambus argues creates success, praise, solves a long-term
problem, or has any other indicia of nonobviousness.
In a typical ex parte case (see note 1) “[o]nce a prima facie case of
obviousness has been established, the burden shifts to the applicant to come
forward with evidence of nonobviousness to overcome the prima facie
case.” In re Huang, 100 F.3d 135, 139 (Fed. Cir. 1996). “[T]he PTO must
rely upon the applicant to provide hard evidence of commercial success.”
Id. at 140 (Concluding that “Huang simply has not carried his burden to
prove that a nexus existed between any commercial success and the novel
features claimed in the application.”)
In Rambus-Rea, the court directed the Board to “to determine if
Rambus’s objective evidence on nonobviousness pertains to the Rambus
device or simply to the dual-edge functionality [DDR] disclosed in Inagaki.”
731 F.3d at 1258. In other words, Rambus-Rea directs the Board to make
new evidentiary findings and designate the Decision as a new ground.
Rambus-Rea indicated that the Board’s requirement that the claims
must recite a set speed to show that the objective evidence is reasonably
commensurate in scope with the claims was too strict on that record.
Rambus-Rea reasoned that “we do not require a patentee to produce
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objective evidence of nonobviousness for every potential embodiment of the
claim.” Id. at 1257.
The court reasoned as follows:
Moreover, Rambus’s evidence shows beyond dispute that the
claimed dual-edge data transfer functionality is what enabled
the praised high-speed transfer of data. A Byte Magazine
article explained that, “by using both edges of a 250–MHz
clock,” Rambus's memory chips “will deliver a tenfold increase
in component throughput.” J.A. 2623. The Electronic
Engineering Times likewise described the dual-edge
functionality as “designed to burst the bottleneck between
processors and DRAMs in desktop systems.” J.A. 2624–25.
The Board did not point to any contrary evidence, and we have
not found any in the record.
Id. at 1257 (emphasis added).
Rambus-Rea indicates that Rambus may be able to rely on Rambus’s
DDR concept to show unobviousness, because the Board “did not point to
contrary evidence” that Rambus’s DDR concept does not “enable[]” the
touted tenfold speed increase that bursts the memory speed bottleneck. See
id. at 1257.
Inagaki anticipates claims 1, 2, 7, 8, 10, and 14 in the related ’097
patent involved in Rambus-Rea. See 731 F.3d at 1254. That holding means
Inagaki’s DDR concept includes Rambus’s DDR concept to the extent it is
recited in claims held anticipated by Rambus-Rea. Those claims are similar
to claims 1 and 3 at issue here, as discussed above, the only claims to which
Rambus directs attention regarding its allegations of secondary
considerations. Rambus-Rea’s rationale also indicates that Rambus may be
able to rely on “the claimed dual-edge transfer [DDR] functionality,” as it is
recited in the remanded claims, because certain magazine articles showed
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that that feature solved a long-felt need and evidenced industry praise. See
id. at 1256-1257 (citing an article in Microprocessor Report). The court
reiterated that “the Board did not address any of this evidence.” See id. at
1257
Accordingly, on remand, we address the evidence as it relates to
claims 1 and 3 to determine whether or not the claimed DDR functionality
inherently creates or enables the touted ten-fold (or enhanced, e.g., five-fold,
seven-fold, etc.) speed increase to solve the bottleneck problem, or shows
unobviousness based on commercial success or other indicia of
unobviousness argued.
2. Rambus’s Contentions
In its Federal Appeal Brief, Rambus argues that “[w]ith respect to the
claims not ‘recit[ing] a specific clock speed,’ synchronous DRAMs
employing a dual-edge/double-data-rate [DDR] feature were shown to
enable speeds ten times faster than the prior-art asynchronous DRAMs.”
(Fed. App. Br. 61 (emphasis added).) The claims are not directed to a single
chip DDR memory devices (such as a DRAM). Rambus appears to argue
that the claims solve the prior art speed problem, because a DDR DRAM
“enables” high speeds. However, the record fails to support inherent or
enabled speeds, and even if it does, Rambus also acknowledges that long-felt
need evidence is negated when the claims also cover devices that do not
solve the speed problem. See id. (citing Therasense, Inc. V. Becton,
Dickinson & Co., 593 F.3d 1325, 1336 (Fed. Cir. 2010) (“finding no long-
felt need because the claims were broad enough to cover devices that did not
solve the problem”) (emphasis added, quoting Rambus’s characterization of
the case). In other words, Rambus acknowledges that if the claims “cover
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devices that did not solve the problem,” then the claims are not reasonably in
scope with the proffered objective evidence.
There is no question that the claims cover devices that do not solve
any speed problem. Rambus also implicitly acknowledges that Rambus-
Rea’s anticipation (by Inagaki) holding changes the analysis in terms of
nexus: “By the Board’s logic, the PTO could always make an alternative
anticipation rejection and dismiss all evidence of long-felt need based on the
putative anticipation rejection.” (Fed. App. Br. 61 (emphasis added).)
3. Claims 1–3
Method claims 1–3 recite no hardware, circuitry, function, or structure
that supports or requires high speed operation. The claims recite “memory
cells” in a “memory device.”
Rambus argues that claim 1 includes an operation code, which
addresses a long-felt need for higher memory performance. (See App. Br.
23.) As discussed above, Inagaki anticipates claim 2 in ’097 patent, which
includes an operation code, according to Rambus-Rea. According to the
’937 Patent Specification, “an op code (operation code) specifies the type of
access,” and includes merely a “single Read/Write switch” to specify a read
or write. (’937 Patent, col. 9, ll. 50–56.) Therefore, the record indicates that
an operation code could not have solved a speed problem that claim 1
embraces. The breadth of the operation code in claim 1 shows that speed
does not increase necessarily from issuing a read or write command. Inagaki
and iAPX show that such a code does not increase speed necessarily (let
alone the ten-fold limits touted by Rambus).
In urging secondary considerations, Rambus argues that the alleged
iAPX operation codes are provided to the MCU. See App. Br. 23 (citing
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Murphy Decl. ¶ 25). This “single chip” argument lacks a nexus to the
evidence. Claim 1 embraces providing an operation code to the MCU,
further showing that the operation code does not contribute to speed or
enhance performance in the broad claims at issue here.
Claim 2 recites providing block size information, but Rambus does
not point specifically to claim 2 as having a nexus to any evidence of
unobviousness. As discussed in the ’171 Remand Decision, the recited
memory device only requires one data pin, and block data may include a
block of, for example, two bits, which may be written sequentially into or
out of a single pin in a memory device, as opposed to several pins that
correspond to several parallel data lines. Rambus has waived any argument
with respect to claim 2 in this proceeding. To the extent waiver does not
apply, we adopt and incorporate by reference the discussion of block size in
the ’171 Remand Decision.
An Initial Decision from the Federal Trade Commission (“FTC”),
25

cited by Rambus to the Federal Circuit in Rambus-Rea, 731 F.3d at 1257
(citing J.A. 2099), further corroborates this claim construction. The FTC
summarizes part of the testimony by one of Rambus’s inventors, Dr.
Horowitz:
88. One of the ways that RDRAM technology achieves a high-
speed data transfer over the narrow bus is through
“multiplexing,” which means that the bus can carry different

25
See Initial Decision at the United States of America Federal Trade
Commission, Office of Administrative Law Judges, In re Matter of Rambus
Inc., No. 9302 (Feb. 23, 2004) (Chief ALJ S. J. McGuire) avail. at
http://www.ftc.gov/sites/default/files/documents/cases/2004/02/040223initia
ldecision.pdf. (attached as App. Br. Ex. G-3.)
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pieces of information at different points in time. (Horowitz, Tr.
8620-21). This aspect of the RDRAM interface protocol means
that over several clock cycles the bus can carry a combination
of address and control and data signals on one or more of the
same bus lines. (Horowitz, Tr. 8620-21; see Rhoden, Tr. 402-
03).
(FTC 19 (emphasis added).)
The FTC findings and Mr. Murphy corroborate that the claims cover
memory devices with “one or more” data bus lines (and one or more
memory device data pins). Mr. Murphy states that “other amounts of data
per pin” can be “selected based on the needs of the system or application.”
(Murphy Decl. ¶ 24.)
The FTC also noted that Rambus described a feature known as
“variable block size,” as innovative:
57. As another example of an innovation related to the protocol,
Drs. Farmwald and Horowitz allowed the response to a request
to include a variable amount of data, a feature known as
“variable block size” or “variable burst length.” (Farmwald, Tr.
8116- 8146; Horowitz Tr. 8512; RX 82 at 9).
(FTC 15.)
Although the FTC and Mr. Murphy describe a “variable” block size
feature as innovative (see Murphy Decl. ¶ 24, claims 1–3 do not recite a
“variable block size.” Claims 1–3 do not recite a bus, a plurality of bus
lines, or a set number of data pins. Sequential transmission over a single
data line does not alter the data bit rate or the data byte rate, which is touted
as fast, as explained further below.
Sending block size information that defines an output data size does
not result, necessarily, in increased speed. Even if claim 2 is interpreted as
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requiring a “variable block size” or output data, the claims are broad enough
to cover a combination of the disclosed example of information about a
block size of zero, as a “special command” that does not transfer data, and a
block size of one, and/or a block size of two bits, on a single bit line. See
’937 Patent, col. 11, 39–47.
Finally, Rambus does not dispute the Examiner’s finding that the
iAPX MCU sends and receives variable size block (long) words. (ACP 98
(citing iAPX F-3).) Inagaki also discloses “block access memory that
transfers data with a speed that is twice the conventional speed.” (I2.)
Rambus cannot rely on these known features, especially when they do not
contribute to the touted speed in relation to the prior art, to show a nexus to
the claims. See J.T. Eaton & Co. v. Atl. Paste & Glue Co., 106 F.3d 1563,
1571 (Fed.Cir.1997) (“asserted commercial success of the product must be
due to the merits of the claimed invention beyond what was readily
available in the prior art”)(emphasis added); Ayst Techs., Inc. v. Emtrak,
Inc., 544 F.3d 1310, 1316 (Fed. Cir. 2008) (“even though commercial
embodiments . . . have enjoyed commercial success, Asyst’s failure to link
that commercial success to the features of its invention that were not
disclosed in Hesser undermines the probative force of the evidence
pertaining to the success of Asyst's and Jenoptik's products.”)
Claim 3 depends from claim 1 and essentially requires a delayed
programmed output response, as discussed above. A single memory device
system and a single controller system, with a memory device having a
delayed response, actually slows the system throughput. Even if several
devices exist, employing a delayed response, without more, does not enable
more speed. The programmed delay, without more, inhibits throughput by
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increasing latency, as Rambus acknowledges. (See App. Br. 26.) Rambus
fails to establish nexus, because it fails to recite the features it describes as
required to increase throughput––controllers and memory devices that must
be aware of the “known delay.” (See id.)
4. Praise for a DDR Memory Device
DDR in synchronous memory devices or, in general, devices, cannot
be the object of praise that shows unobviousness, because Inagaki discloses
DDR in a memory RAM device, and anticipates claims 1 and 2 in the ’097
Patent, which are similar to argued claims 1 and 3 here. Rambus does not
assert that DDR in a controller, or another device, was novel or unobvious.
Rambus did not assert that it invented DDR in a device. Whether or not
Inagaki anticipates claims here, the DDR scheme was well-known. In
another proceeding, the Board quoted Mr. Murphy as declaring that the
clocking scheme “is often referred to as ‘dual edge clocking’ and allows for
data transfer at twice the rate of the external clock signal.” See Micron v.
Rambus, Dec. 22 (95/001,109 & 95/001,155) (PTAB Oct. 31, 2012)
(quoting Murphy Dec. ¶ 26, May 13, 2009, filed Oct. 7, 2010), dismissed, In
re Rambus, 2014-1064 (Fed. Cir. Apr. 19, 2014). Under Eaton, Rambus has
the burden of showing nexus by linking its evidence “beyond what was
readily available in the prior art.” 106 F.3d at 1571.
5. Inherent Speed-–Nexus-–Unclaimed Chip Interface and Other
Unclaimed Features
On nexus, Rambus-Rea, 731 F.3d at 1258 directs the Board to “be
careful to parse the evidence that relates only to the prior art [DDR]
functionality and the evidence that touted Rambus’s patented design as a
whole.” Rambus’s disclosed design, as a whole, prominently includes the
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chip interface on a single chip and its attendant functional hardware, which
is touted, but is not claimed. Without the chip interface, the touted speeds of
250–500Mhz are not enabled, much less inherent, in claims 1 and 3.
26
Moreover, claim 1 does not actually recite DDR, or require or enable
enhance speed, because the rising and falling clock edges need not be in the
same clock period. Claim 13 of the ’937 Patent verifies this, by requiring
the rising and falling edges to “transpire in the same clock cycle of the
external clock signal.” Therefore, claim 13 only doubles the data rate, thus
the term, DDR. Claim 1 does not even require DDR.
Even if the system uses DDR (both rising and falling edges in a single
clock cycle), the claims do not enable the touted high (250–500 MHz)
speeds. As the ’937 Patent states, “[h]igh bus bandwidth is achieved by
running the bus at a very high clock rate (hundreds of MHz).” (’937 Patent,
col. 4, ll. 36–36.)
Inagaki, the ’937 Patent, and other evidence, including statements by
Rambus, verify that a high speed clock is required, or, if not a clock, at the
least, a high speed interface required to handle such a fast clock and the
DDR functionality. Inagaki discloses DDR memory devices, and anticipates
all of the patented design recited in claims 1 and 2 in the ’097 patent.
Claims 1 and 3 here fail to add to the speed capability, as a matter of
structure, or function, in any appreciable manner advanced by Rambus on
this record. Although the DDR functionality may be necessary, it is

26
Articles generally tout a ten-fold speed of 500MHz, with at least one
discussing five- to ten-fold speed increases. (See PTO Fed. Br. 49–50
(summarizing articles; App. Br. App. L.)
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insufficient to enable, by itself, the touted speeds of 250–500 MHz, or to
handle a 250 MHz (or less) clock to create that touted speeds using DDR. If
it were, Inagaki’s device also would be five to ten times faster than prior art
memory devices, because it uses the claimed DDR functionality, as the
anticipation holding in Rambus-Rea proves.
Further, according to the ’937 Patent, unclaimed memory interface
features in a single chip “must be added” to obtain the speed: “New bus
interface circuits must be added and the internals of prior art DRAM devices
need to be modified so they can provide and accept data to and from the bus
at the peak data rate of the bus. This requires changes to the column access
circuitry in the DRAM . . . .” (’937 patent, col. 4, ll. 27–31.)
The ’937 Patent discloses fast (e.g., 500 MHz), single chip, DDR
DRAM devices, which require a fast (e.g., 250 MHz) clock, and other
features, to obtain that speed:
High bus bandwidth is achieved by running the bus at a
very high clock rate (hundreds of MHz). This high clock rate is
made possible by the constrained environment of the bus. . . .
For a data rate of 500 MHz, the maximum bus propagation
time is less than 1 ns (the physical bus length is about 10 cm).

(’937 Patent, col. 4, ll. 36–43 (emphasis added).) Similarly, to enable the
high speed, i.e., “to operate at a 2 ns data rate [i.e., 500 MHz,], the transit
time on the bus should preferably be kept under 1ns[ec] . . . . Thus, the bus
lines must be kept quite short, under about 8 cm for maximum performance.
Lower performance systems may have much longer lines, e.g., a 4ns bus
may have 24 cm lines (3ns transit time, 1ns setup and hold time).” (Id. at
col. 18, ll. 9–16 (emphasis added).)
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The claims at issue do not specify any chip interface, bus, or bus
length. As part of what “must be added” to memory device chip interfaces
to handle the “very high clock rate made possible” by short propagation
lengths (10cm), Figure 10 discloses the sole embodiment of part of this
required “new bus interface circuit[]” in the modified DRAM: “a set of
input receivers 71, 72 . . . and circuitry to use the internal clock 73 and
internal clock complement 74 to drive the input interface.” (’097 patent, col.
21, ll. 46–50.) Further, “each device pin, and thus each bus line, is
connected to two clocked receivers, one to sample the even cycle inputs, the
other to sample the odd cycle inputs.” (Id. at col. 21, ll. 51–55.) In addition,
the interface must control skew: “One important part of the input/output
circuitry generates an internal device clock based on early and late bus
clock. Controlling clock skew (the difference in clock timing between
devices) is important in a system running with 2 ns cycles . . . .” (Id. at col.
22, ll. 50–54.) (Note that a 500 MHz frequency corresponds to a 2 nsec or
“2 ns cycle[]”time period.)
Rambus’s related patent, U.S Patent No. 5,513,327 (Apr. 30, 1996),
specifically claims these first and second input receivers, and an internal
clock, and latch circuitry, to handle DDR, in a “DRAM.” See id., claim 1.
The ’937 Patent recites broader claims, without DRAMs, the internal clock,
the receiver clock circuitry, or latch or skew correction circuitry, and relies
on the ’327 patent for continuity. Although claim 18 here recites “output
driver circuitry to provide an operation code to the memory device,” it is not
in a DRAM, it is in a “controller device,” and it generically recites driver
circuitry, and lacks the specific latch circuitry of claim 1 in the ’327 Patent.
Moreover, the Examiner confirmed claims 19–22, which depend from claim
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18 and recite first and second latch circuitry, or a delay lock loop circuit, as
part of the controller device. At least these features are required to support
the touted speed according to the evidence of record.
The ’937 patent also implies that a “number” of other changes over
“conventional DRAMS” contribute to speed or efficiency––such as
“registers,” to “store control information,” “device identification” and
“address” information. (See id. at col. 4, ll. 22–25.)
Rambus’s argument in its Federal Circuit brief about the
“synchronous DRAM[],” quoted above, Dr. Horowitz’s discussion of the
“RDRAM interface,” below, magazine articles, and the claims in the earlier
’327 patent, all show agreement with, and bolster, the findings. As noted,
Rambus alleges that a modified DRAM chip, using DDR, solves the speed
problem. Claims 1 and 3 do not require a DDR DRAM, or RDRAM, or any
single chip DDR memory device, inherently or otherwise.
Contrary to its assertions to the Federal Circuit about inherency and
tenfold speed based on DDR, Rambus admitted to the Board that DDR only
“allowed data to be transferred at twice the rate of the external clock signal,
thus improving the speed of data transfer for a particular clock frequency,”
and Rambus called this a “[s]ignificant performance improvement[].” (See
Micron Tech., Inc. v. Rambus, Inc. BPAI 2012-001976, Rambus App. Br. 22
(95/001,128 & 95/001,026) (BPAI Sept. 23, 2010) (emphasis added).)
Rambus-Rea directs the Board’s attention to a Microprocessor Report:
article:
For example, an article in the Microprocessor Report stated that
Rambus “ha[d] unveiled its radical new processor-to-memory
interface and DRAM architecture, which promise to create the
most significant change in processor/memory system
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architecture since the introduction of the DRAM two decades
ago.” J.A. 2633. The article explains that the technology
“operat[es] with a 250–MHz clock and transfer[s] a byte of data
on each clock edge,” an approach that was “somewhat counter-
intuitive.”
Rambus-Rea, 731 F.3d at 1257.
Rambus-Rea also directs attention to similar articles. See id. As the
quote and virtually all, if not all, the articles show, in line with the ’937
Patent disclosure, the touted speeds of 250–500 MHz require a “radical”
chip interface change with the ability to handle fast (e.g., 125–250 MHz
clocks). That is, the memory chip requires “a significant change in . . .
architecture,” and/or “a radical new . . . interface,” in a DRAM (or other chip
perhaps): i.e., chip interface circuitry having the necessary structure ability
to handle a high speed (e.g., 125–250 MHz) external clock. (See App. Br.,
Ex. L, R39356-60, Microprocessor Report article.)
The Microprocessor Report article explains that “[t]he high clock rate
is made possible by a combination of special CMOS interface circuits,
careful circuit board layout, short trace lengths, RAM packages with low
parasitic capacitance and inductance, and low voltage swings.” (App. Br.,
Ex. L. R39357 (emphasis added).) Claims 1 and 3 do not recite this
“combination,” which includes the “special CMOS interface circuits,” which
makes speed “possible.”
The same article refers to “[l]ogic designs for the Rambus master and
slave interfaces, to be incorporated into processors for interface ASICs and
DRAMs.” (App. Br., Ex. L., R 39356 (emphasis added).) “In addition to the
Rambus Channel interface, the major difference between a standard DRAM
and an RDRAM is the way the sense amplifiers are used.” (App. Br., Ex. L.
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R 39357.) Again, claims 1 and 3 do not require the interface, a DRAM,
short traces, low parasitic capacitance, and other noted features.
Rambus-Rea also cites an Electronic Engineering Times (“EET”)
article for “describ[ing] the dual edge functionality as ‘designed to burst the
bottleneck between processors and DRAMs in desktop systems.’” Rambus-
Rea, 731 F.3d at 1257.
27
The system includes “a unique 500-MHz, 9-bit
data channel designed to burst the bottleneck between processors and
DRAMs in desktop systems.” (Id.) (App. Br., Ex. L, R39847 (the EET
article).) The DDR concept, by itself, does not burst the bottleneck. Rather,
the 500MHz, 9-bit DRAMs, with the chip interface circuitry, at the least, are
required. The 500 MHz speed requires the 250 MHz clock, which requires
the interface to handle that. A “key part” requires the “high-speed bus [to
be] . . . synchronized to a 250MHz clock.” (Id. at R39348.) The EET article
describes an “RDRAM,” which refers to the interface features as discussed,
including, at least, the disclosed receiver circuitry that “must” be included to
handle fast clocks in a single modified DRAM chip.
The EET article touts other related features. “To achieve this speed,
the bus employs low-voltage, CMOS drivers and receivers . . . .” (Id.) Also,
“the Rambus channel moves bytes over 9 data wires, synchronized to a 250
MHz clock.” (Id.) “The combination of sense-amp caching and a
500Mbyte/second bus provides enormous theoretical bandwidth between the
DRAM memory array and a processor.” (Id.) “The DRAM produces an

27
The EET article is listed as R39347–R38348 in Rambus App. Br. Ex. L
(Ron Wilson and David Lammers, “Rambus Lets Loose fast DRAM
channel,” Electronic Engineering Times, Iss. 684, Mar. 16, 1992).
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entire row of data . . . at its sense amps.” (Id.) None of the described
features, the DRAMs, low voltage CMOS drivers and receivers, the high
speed bus, the nine data wires, 250MHz (or similar speed) clock interface
circuitry, the sense-amp caching, or other touted features, are recited in
claims 1 and 3.
Rambus-Rea also cites to a Byte Magazine article that shows that “‘by
using both edges of a 250-MHz clock,’ Rambus's memory chips ‘will deliver
a tenfold increase in component throughput.’ J.A. 2623.” Rambus-Rea, 731
F.3d at 1257. This also shows that, at a minimum, the 250 MHz clock
DRAM receiver interface, to handle the “250-MHz clock,” is required to
create the touted ten-fold increase.
Stated differently, the DDR (double data rate) function itself cannot
deliver a ten-fold increase: DDR, as the name implies, only doubles the
speed––assuming of course that both clock edges are used each clock
period––a feature not required by claim 1. At the least, the chip interface,
touted in the articles, and disclosed in the ’097 patent, must be present to
enable the ten-fold speed increase. Multiplying the five-fold increase, which
the unclaimed DRAM interface circuit (and, inter alia, short bus lengths,
etc.) provide, by the predictable two-fold claimed DDR function, results in
the touted ten-fold increase.
Another article cited by Rambus, Semiconductor Currents, verifies
this, and states that “Rambus Slashes memory bottleneck with 500 Mbytes/s
memory bus,” and states that transfers on both clock edges “doubl[es] the
bandwidth to 500 Mbytes/s.” (App. Br., Ex. L, R39362 (emphasis added).)
This corroborates the findings of record that other disclosed, but unclaimed,
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hardware elements, including the chip “interface” to handle the 250 MHz
clock, are necessary to obtain the remaining five-fold (out of ten-fold) factor.
Rambus’s Appeal Brief Exhibit L consists of several other articles that
generically tout the 500MHz speed and many other unclaimed features,
including the Rambus DRAM chip interface. For example, the San
Francisco Chronicle article generically discusses Rambus technology such
as the “so-called new interface for DRAMs that is both simpler and faster
than earlier designs,” and touts the tenfold speed of 500MHz. This article
does not mention DDR. Rambus appears to be the source of the article.
(App. Br., Ex. L, R39338.)
Another article, Semiconductor Currents, states that “Rambus Slashes
memory bottleneck with 500 Mbytes/s memory bus.” The article states that
“the bus only requires CMOS at each end! No fancy/costly BiCOMS, or
other bipolar wizadry.” (App. Br., Ex. L, R39362.) The article also notes
that transfers on both clock edges “doubl[es] the bandwidth to 500
Mbytes/s.” (Id. (emphasis added).) This also shows that DDR only doubles
the speed. The article states that the “Rambus concept consists of a Rambus
master, either included on-chip in the CPU . . . driving a 9-bit, 250 MHz bus
to Rambus slaves.” (Id.) This Rambus concept requires the fast clocks on a
9-bit bus, and the DRAM slave interface to handle that, which does not
pertain to the claims at issue here.
Further corroborating the article evidence, the ’937 Patent describes a
litany of other significant features that implicate commercial embodiments
and support either bit or byte speed. Unclaimed, but disclosed, features
include eight data lines, single memory devices, small DRAM sizes with
minimal bus loading, a narrow bus, multiplexed bus architecture and device
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interfaces, packetized control, unique device identifiers, time access and
arbitration schemes, controlled-impedance, double terminated lines, reduced
power, and memory devices having all the functionality of prior art circuit
boards. (See ’097 Patent, Abstract, col. 3, ll. 23–48; col. 4, ll. 22–57; col. 7,
ll. 8–31; col. 9, ll. 39–65; col. 12, ll. 45–58; col. 14, ll. 47–65; Murphy Decl.
¶ 31 (touting how the “inventions disclosed” increased “DRAM
performance”), ¶ 32 (describing how Drs. Farmwald and Horowitz included
complex delay lock circuitry in a DRAM memory device).
As another example of an unclaimed, but touted feature in the chip
interface supporting speed, Dr. Horowitz obtained praise for “a number of
phase-locked loop circuits” and for other “ideas he pioneered.” (See Ex. J,
IEEE Horowitz release (touting “significant[] increase [in] the bandwidth of
the access to DRAM circuits” up “to several gigabits/second.”) The IEEE
release includes praise because of changes in “the way an entire industry
thinks about memory interfaces.” It touts his work “on interface circuits.” It
does not mention DDR. (See also App. Br., Ex. E-5, Farmwald Testimony,
277–279 (touting 8 bit wide DRAMs at 500MHz).
28

Rambus points to similar evidence by Dr. Horowitz, who also
indicates that at least part of any success was due to other unclaimed
features. The inventor declared that “it was felt that . . . one could not put a

28
Rambus also cites to Dr. Farmwald’s testimony to show a solution to a
long-felt need, but Dr. Farmwald does not even discuss DDR at the cited
passages. He only generally discusses building a 500MHz, 8 data bit wide,
single DRAM chip (i.e., 8 data pins), without any specifics, as a general
trade-off based on cost, and solution to future speed problems in the mid-
1990s. (See App. Br. Ex. E-5, 277–280.) The claims do not require speed,
a DRAM, or 8 data pins.
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phase locked loop or delay locked loop on the DRAM itself” and that others
expressed “disbelief” about a 500 [MHz] DRAM rate.” (App. Br. 24
(emphasis added, citing FTC 22 ¶ 105.) This alleged disbelief or skepticism
points to unclaimed features: a PLL on the DRAM itself (the single chip
interface) and the unclaimed interface features necessary to create 500 MHz
speed.
Under Ormco,Corp. v. Align Tech., Inc., 463 F.3d 1299, 1311–12
(Fed. Cir. 2006), Rambus’s evidence does not establish a nexus, because it
relies on, at the least, an unclaimed chip interface on a DRAM, or some
other single chip memory device, with specifically required receiver
features, to inherently provide unclaimed speed (setting aside the short bus
length and the PLL): “[I]f the commercial success is due to an unclaimed
feature of the device, the commercial success is irrelevant. So too if the
feature that creates the commercial success was known in the prior art, the
success is not pertinent.” Id. at 1312 (footnotes and citations omitted). The
DDR feature “is not pertinent,” because it is in the prior art, i.e., Inagaki.
The features required to handle the highly-touted remainder of speed, the
factor of roughly two-and-a-half to five, involves unclaimed features, at a
minimum, the unclaimed chip interface on a single chip, with its dual
receivers (that may require clock skew correction circuitry) to handle the
high speed clocks (e.g., 125–250 MHz). The record also shows that the high
speed requires short bus distances, delay or phase locked loop interface
circuits for skew correction, and other receiver features. Rambus has not
met the burden of showing nexus for the claims at issue.
6. Counterintuitive-Nexus
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In 1982, Inagaki’s method, using DDR, increased the speed of prior
art “conventional” devices from “about 100nsec” (10MHz), to “twice the
conventional speed,” or 50nsec (effectively 20 MHz). (See Inagaki 3.) In
1990, Rambus touted a ten-fold increase over those speeds––speeds of about
2nsec (500 MHz), by using DDR on a 250 MHz clock). (See ’937 Patent,
col. 18, l. 1; col. 21, ll. 55–58; col. 22, ll. 50–56.)
Rambus-Rea also states that “[t]he [Microprocessor Report] article
explains that the technology “operat[es] with a 250-MHz clock and
transfer[s] a byte of data on each clock edge,” an approach that was
“somewhat counter-intuitive.” Rambus-Rea, 731 F.3d at 1257. Rambus-Rea
indicates the Board erred in finding of lack of nexus, because this quotation
shows a nexus by praising the claimed DDR feature. See id. The DDR
feature, at least for a single bit on a single pin, is in the prior art, as Inagaki
shows, and does not show a nexus to claims that do not recite a set number
of data pins or bus lines, or implicitly require such a number.
The praise, as noted in the article, and as discussed above, touts
several unclaimed features, the “special CMOS interface circuits,” “logic
designs,” and a “combination” of features that make “possible” the “high
clock rate”: “The high clock rate is made possible by a combination of
special CMOS interface circuits, careful circuit board layout, short trace
length RAM packages with low parasitic capacitance and inductance, and
low voltage swings.” (App.Br., Ex. L, R39357.)
According to the article, a counter-intuitive feature focuses on
obtaining fast speed by using a “narrow bus”:
The Rambus approach is somewhat counter-intuitive, in
that it achieves its high bandwidth through fast data rates
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rather than wide buses. One benefit is that a minimum system
can use a single Rambus memory device, regardless of the
system’s word width. The narrow bus also minimizes the
number of pins and amount of board area required.
(App. Br., Ex. L, R39356.)
Setting aside the focus on the unclaimed “single Rambus memory
device,” and focusing on the “narrow bus,” Inagaki already taught that a
major beneficial aspect of DDR is that it increases data speed for a given
clock speed or a given number of data lines (and corresponding memory
device data pins). (See I1, Inagaki 2–3.) Inagaki specifically disparages the
prior art method of “increas[ing] the number of pins,” because that makes it
“impossible to increase the integration on a board.” (Inagaki, 2; accord I1.)
In other words, Inagaki addresses part of the speed problem that
otherwise requires an increased pin count (i.e., an increased data bus width)
by using DDR on a relatively narrow bus. (See also I1–I3.) The
Microprocessor Report describes as counterintuitive the same DDR concept
that Inagaki described about 8 years prior to the priority date involved here.
Essentially, Inagaki teaches minimizing the number of data lines or pins by
using both clock edges (i.e., narrowing the bus). (See I1–I3.) Therefore, it
was not counter-intuitive at the time of the invention to reduce the pin count
or narrow the bus width, and increase the data rate, by simply using DDR in
a memory device, because Inagaki already did that.
Even if the article somehow praises the use of DDR on a byte, i.e., for
two bits of data on either a single data line or on unclaimed parallel bus
lines, this does not show nexus. The non-novel DDR feature, precluded by
Inagaki as a basis of praise or commercial success, at the least, includes the
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synchronous transfer to or output from a memory chip device of successive
bits of data (a byte) on a data line using DDR. See Tokai Corp. v. Easton
Enters., Inc., 632 F.3d 1358, 1369 (Fed.Cir.2011) (“If commercial success is
due to an element in the prior art, no nexus exists.”). Even if the use of
DDR on two data lines (i.e., a data byte on parallel lines in a narrow bus of
two) attached to two pins in a memory device was not in the prior art (i.e.,
Inagaki), unless that feature inherently produces the speed or other features
touted in the articles, it fails to solve the bottleneck problem and runs afoul
of Therasense, which Rambus cites, as noted above and further below. As
explained, DDR only doubles the data rate (data rate includes bit rate and/or
byte rate), and DDR, by itself, does not enable the touted speed, much less
inherently require it.
Moreover, as set forth above, claims 1–3 do not require a data byte
transfer on parallel lines (i.e., at least two bits per clock edge). Hence, any
praise to a DDR byte transfer, even if it relates to parallel data lines, relates
to an unclaimed feature. The claims at issue here do not recite multiple data
lines or multiple pins on the memory device, and therefore do not require “a
byte of data on each clock edge,” which the article addresses. Ultimately,
the praise either goes to unclaimed features related to a transfer of a byte of
data on successive clock edges of a 250 MHz clock that triggers multiple
data lines simultaneously (albeit, a small set thereof on a narrow bus), or it
goes to the DDR feature in the prior art that Inagaki discloses.
Further, as the Examiner found per the rejection of the claims, and as
In re Rambus implies, iAPX discloses byte transfers on parallel lines
triggered by a single clock edge to a synchronous memory module (having
aggregated memory chips controlled by the MCU). Inagaki discloses that
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prior art memory device chips were employed in parallel to “increase the
MOS RAM bit width (a multi-bit structure) to increase the data transfer
rate.” (Inagaki 2.) Therefore, skilled artisans would have recognized that
the Inagaki DDR concept applies to multi-bit width structures (even if a
specific embodiment therein is limited to a single data pin), and is not
limited to using DDR on a single data pin, given further that Inagaki
disparages “increasing” “a multi-bit” pin width. (See id.; I1.) In general,
Inagaki’s “invention presents block access memory that transfers data with a
speed that is twice the conventional speed.” (Inagaki 3.) That generic
teaching, for data, is not limited to DDR on a single data line or pin, even if
Inagaki’s disclosed or preferred embodiments may be so limited.
Moreover, the difference between what the iAPX system does and
what claims 1 and 3 recite relates materially only to Inagaki’s DDR. See
Ayst, 544 F.3d at 1310 (“While the evidence shows that the overall system
drew praise as a solution to a felt need, there was no evidence that the
success of the commercial embodiment of the . . . patent was attributable to
the substitution of a multiplexer for a bus, which was the only material
difference between Hesser and the patented invention.”) Similarly, the
totality of record evidence shows that substituting Inagaki’s DDR function
for iAPX’s similar clock function, the only “material difference between
[iAPX] and the patented invention,” would not have drawn the praise or
success, or solved the bottleneck problem. The DDR simply would have
doubled the iAPX data speed, in a predictable manner––i.e., as Inagaki
specifically predicts.

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7. Related Rambus Proceedings Show Speed Related to Other
Features
The Federal Circuit recognizes the importance of speed in Rambus
devices, and notes the additional use of a multiplexed bus in related Rambus
patents. See Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081,1095
(Fed. Cir. 2003) (“The present invention is designed to provide a high speed,
multiplexed bus”) (internal quotations and citations omitted, emphasis
added).) In another case involving a related Rambus patent, the Federal
Circuit determined that access-time registers in DRAM memory devices to
store delay values helped to solve the memory bottleneck problem. See
Rambus v. Rea, 527 Fed.Appx. 902, 903–05 (Fed. Circ. 2013)
(unpublished).
As the Federal Circuit cases show, different inventive aspects, which
are not claimed here, contribute to the touted speed functionality. In
addition to the multiplexed bus and access-time registers noted by the
Federal Circuit, Rambus argued about other speed inducing features in
related proceedings.
In another related reexamination proceeding, PTAB Appeal No. 2012-
001639, Rambus argues that “the success was because of the claimed
features such as the claimed operation code including precharge
information.” See Micron v. Rambus, Rambus Reh’g. Req. 30 (95/001,109
& 95/001,155) (PTAB Oct. 31, 2012) (emphasis added) dismissed, In re
Rambus, Appeal No. 2014-1064 (Fed. Cir. Apr. 19, 2014). Claims 1 and 3
do not recite the touted precharge feature advanced in that proceeding as
providing success.

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8. Licensing
Rambus-Rea found error in the Board’s reasoning that competitors
typically take licenses for reasons unrelated to obviousness, and found
factually that the limited record suggested otherwise. Rambus-Rea found,
on the limited record, that Rambus’s licenses “linked its commercial success
to the claimed dual-edge data transfer functionality.” Id. at 1257.
Ordinarily, “[t]he mere existence . . . of licenses is insufficient to
overcome the conclusion of obviousness.” Sibia Neurosciences, Inc. v.
Cadus Pharm Corp., 225 F3d. 1349, 1358 (Fed. Cir. 2000) (“three licenses .
. . of the ’629 patent, all of which were part of larger licensing packages,”
does not show nexus); see also Pentec, Inc. v. Graphic Controls Corp., 776
F.2d 309, 316 (Fed. Cir. 1985); EWP Corp. v. Reliance UniversaI Inc., 755
F.2d 898, 907-09 (Fed. Cir. 1985); Iron Grip Barbell Co., Inc. v. USA
Sports, Inc., 392 F.3d 1317, 1324 (Fed. Cir. 2004).
In Iron Grip, 392 F.3d at 1324, the court noted that competitors may
simply take a license “‘because it is often “cheaper to take licenses than to
defend infringement suits.’” Id. (quoting EWP Corp. v. Reliance Universal
Inc., 755 F.2d 898, 908 (Fed.Cir.1985).). The court held that “two . . . taken
in settlement of litigation” fails to show nexus and that “the existence of
licenses is of little significance.” Id. In In re GPAC Inc., 57 F.3d 1573,
1580 (Fed.Cir.1995), the court found that “in affidavits reciting the license
history of the ’111 patent, GPAC did not establish which claims(s) of the
patent the licensing program incorporates, GPAC has not shown that
licensing of Natele’s invention arose out of recognition and acceptance of
the subject matter claimed.”
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Based on Rambus’s arguments and citations to the Federal Circuit, for
nexus, Rambus-Rea relied partially on the EET article discussed above that
Rambus attached in Appendix L of its Appeal Brief to the Board. Rambus
did not cite that article to the Board in its Appeal or Reply Brief to establish
licensing. (See App. Br. 24 (discussing licensing).) Rambus does not
specify claims to show nexus in an affidavit (or otherwise) as GPAC
requires.
The EET article, discussed at Rambus-Rea, 731 F.3d at 1257, states
that “the other key part of the Rambus idea is the memory bus” that “moves
one byte on each clock edge.” Rambus-Rea links this statement with another
statement in the article that three (Japanese) companies had paid “substantial
license fees to participate in the technology.” Rambus-Rea also found that
nothing in the record showed that “the commercial value of the licenses
stemmed from other licensed Rambus patents.” Id. Rambus-Rea also
indicated that another reference, the FTC Initial Decision described above,
evidences licenses by Hitatchi, Ltd., Oki Electric Industry Co., Lucky
Goldstar, and Intel Corp. Id. at 1257.
Rambus did not rely specifically on the FTC Initial Decision in this
proceeding to show licensing or commercial success. In the related ’171
proceeding, Rambus mentions certain companies as “[o]ther licensees,” and
implies they may have “licensed the technology disclosed in the Farmwald
Family” of patents. (See ‘171 App. Br. 29.) However, Rambus fails to
name a specific company that has a license to any specific claim in the ’937
Patent. (See App. Br. 24.)
The Board herein points to other counter evidence as Rambus-Rea
directs. The ’937 Patent did not issue until October 16, 2001. Therefore, the
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record does not show how Rambus could have licensed any patent claims to
the three Japanese companies in 1992 when the EET article was published.
As discussed above, Rambus’s related patent, U.S Patent No. 5,513,327,
specifically claims first and second input receivers, and an internal clock, to
handle DDR, in a “DRAM.” Even though the ’327 patent also issued after
1992 (i.e., in 1996), the record also shows that Rambus licensed “trade
secrets.” (FTC 21.) Perhaps this DDR subject matter specifically claimed
later in the ’327 patent was a trade secret in 1992, and the subject of
licensing. Rambus fails to identify clearly the subject of licensing and fails
to satisfy its burden of showing nexus to commercial success.
Rambus specifically describes multiple patents involved in the
licensing: “For instance, in addition to the significant sales of products
embodying the claimed inventions, the Farmwald Family, which includes
the ’097 patent, has numerous licenses.” (‘171 App. Br. 29 (emphasis
added).) This ambiguous statement only shows that the Farmwald Family is
the subject of licenses. Rambus describes “numerous patents in the
Farmwald Family.” Id. (emphasis added). Rambus also explains that
“Samsung, which has requested reexamination of numerous patents in the
Farmwald Family, took a five-year license under the Farmwald Family as
applied to synchronous DRAM devices in October 2000, and recently took
another license to the Farmwald Family, among other patents.” Id.
(emphasis added). Rambus’s further admission that Samsung took licenses,
and also challenged numerous patents in the same Farmwald Family, shows
that licensees (e.g., Samsung) knew there were different types of Farmwald
Family licenses and patents, and implies that Samsung had different reasons
either to challenge the patents or to take licenses. Rambus does not specify
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what any of the alleged licenses include, by declaration or even argument.
Rambus has not met its burden under Iron Grip and GPAC of showing
nexus, including whether or not the three Japanese companies mentioned,
paid for a license to the ’937 patent.
The EET article cited in Rambus-Rea is a report about a “Rambus
announcement.” (EET, see R39347, Ex. L, App. Br.) In other words,
Rambus, again, is a source of the article. The article states that “[t]he
announcement included not only Rambus’s unique channel, but plans for
Rambus-specific DRAMs, ASICs and microprocessors from Fujitsu Ltd.,
NEC Corp., and Toshiba Corp. The three Japanese companies have worked
closely with the startup, and have paid substantial license fees to participate
in the technology.” Id. These companies, who worked with Rambus,
“desperately want[ed] a way to differentiate themselves from the commodity
DRAM market.” (Id. at R39348 (emphasis added).) The EET article states
that “reports have put the license fee as high as $2.5 million each.” Id.
The EET article does not state whence the “reports” came, only that
Rambus is its source. The article does not tie a license to any particular
patent claim, or even a patent. It appears that microprocessor and ASIC
inventions also may have been involved, in addition to DRAMs. The article
states a reason for the licenses, the companies were “desperat[e]” to stay in
the DRAM market.
Even if the third-hand reports, including reports by Rambus, can be
credited, paying $2.5 million to stay in the DRAM market, by companies
desperate to stay in the market for the most popular chip known, DRAM,
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indicates that the licenses may have been due to the popularity of DRAM
chips, which the claims cover, but do not require.
29
See In re DBC, 545 F.3d
1373, 1384 (Fed. Cir. 2008) (“Nor is there any evidence that sales of
XanGo
TM
juice were not merely attributable to the increasing popularity of
mangosteen fruit or the effectiveness of the marketing efforts employed.)
Under DBC, Rambus has the burden to explain the typical value of a license
in the DRAM market, and compare that to any license it may have sold for
the ’937 Patent. See id. (“Based on this increasing popularity, [the Board]
observed that there was no evidence comparing the growth in sales of
XanGo™ to the growth in sales of mangosteen juice in general.”) In DBC,
evidence showed gross sales of $130 million, here the license fee, at most,
involves $2.5 million and desperate DRAM partners in a popular DRAM
market (assuming arguendo that the fee was paid for the ’937 Patent––no
persuasive evidence or even argument shows or alleges this however).
The EET article also states that “Fujitsu plans an ASIC
implementation of the Rambus master later this year.” (App. Br., Ex. L.,
R39348.) It also states that Fujitsu plans to implement a Rambus DRAM in
the form of “a unique plastic package that mounts astride the Rambus strip
line.” (Id.) NEC “will develop a system based on the Rambus architecture.”
(Id.) The Rambus master, the ASIC implementation, the plastic package,
and the system point to other unclaimed Rambus inventions. On its face, it
does not appear from the article that the described methods or devices there

29
See Wicklund et al., U.S. 5159,676, col. 1, ll. 36-37 (Oct. 27, 1992) (“At
the present time, the most popular form of read/write memory is the
semiconductor DRAM . . . .); see also FTC, 16 findings (finding 66,
discussing the “large size of the DRAM market”).
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were the subject of any alleged licenses that are tied to any specific claim in
the ’937 Patent.
Even if the article somehow implicates Rambus patents with DDR,
many of Rambus’s Farmwald Family patents involve the DDR functionality,
including the’097 patent at issue in Rambus-Rea. (Rambus had filed 80
patent applications by 1994, as discussed further below.) One example
includes the U.S Patent No. 5,513,327, with narrow DDR DRAM claims, as
noted above. Still other reexaminations involve DDR, including the
reexamination that discusses precharge cited above. In most, if not all, the
myriad of cases appealed to the Board, Rambus submitted virtually the same
secondary considerations of nonobviousness as submitted here.
Rambus-Rea points to Rambus “licenses from Hitatchi, Ltd., Oki
Electric Industry Co., Lucky Goldstar, and Intel Corp. J.A.2099.” Rambus-
Rea, 731 F.3d at 1257 (citing the FTC Initial Decision). The cited page, in
the FTC Initial Decision, does not show what patent is involved in any
licenses. It states that the licenses were obtained “by June 1992.” (FTC 21.)
The page states that Rambus “had entered into license contracts that
compelled Rambus partners to use Rambus technology patents and trade
secrets only for use in RDRAM-compatible chips.” (Id. (emphasis added).)
It also mentions “technology license agreements” with the three Japanese
companies discussed in the EET article: NEC Corp. (“NEC”), Toshiba Corp.
(“Toshiba”), and Fujitsu Laboratories, Ltd. (“Fujitsu”). It states that
“Rambus had filed for, but not yet obtained, a base patent on its
technology.” (FTC 21.)
In other words, the licenses include “trade secrets” and “Rambus
technology patents” that had not yet issued in 1992, the date of the EET
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article. Further, by August, 1996 Rambus had filed 80 patent applications
and 16 patents had issued. (FTC 37.) According further to the FTC
findings: “Rambus has obtained patent claims that cover programmable
CAS latency, variable burst length, dual-edge clocking, and on-chip DLL as
those features are used in SDRAMs and/or DDR SDRAMs. . . . Rambus has
asserted claims covering these four features against SDRAMs and DDR
SDRAMs.” (FTC 37.)
Four years after the article about licensing, in 1996, Rambus had
obtained licenses for trade secrets, and had patent claims covering a wide
variety of broad inventions, which involved modified DRAMs. Rambus
does not even state, let alone show, who licensed the ’937 Patent claims or
why they did it.
With further regard to licenses, the FTC discusses Rambus’s strategy:
72. As a 1989 draft business plan explained, Farmwald
and Horowitz hoped to establish a de facto standard by offering
all interested DRAM and central processing unit (“CPU”)
vendors a sufficiently low licensing fee (2%) that it will not be
worth their time and effort to attempt to circumvent or violate
the patents.” (RX 15 at 9).
(FTC 17 (emphasis added).)
This “sufficiently low licensing fee” contradicts the characterization
of the “reported” “significant” fees of $2.5 million, otherwise touted in the
EET article involving Rambus press announcements. Rambus’s business
plan also provides a reason for a competitor to obtain a license unrelated to
obviousness: “it would not be worth their time and effort to circumvent the
patent.” (Id. at 16.) Other reasons appear in the FTC record: Rambus’s
market strategy was to convince chip makers that the Rambus technology
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would become a standard, and that “charg[ing] lower royalties . . . [would]
foster acceptance.” (Id. at 18.)
The FTC further found the following related Rambus licensing
strategy:
67. To become and remain a viable company, it intended to
charge low single digit royalties, which it believed to be fair in
light of the importance of Rambus’s intellectual property
contribution to the product and the large size of the DRAM
market. (Farmwald, Tr. 8128; Cf (1282 at 5).
(Id. at 17 (emphasis added).)
The “large size of the DRAM market,” the popularity of DRAMs, the
low licensing fees, such fees set to avoid litigation, and the desperate DRAM
partners, each constitute valid reasons to license the technology, apart from
obviousness. The claims do not recite DRAMs or modified DRAMs.
The FTC also found that “[p]art of [Rambus’s] early strategy . . . was
to pursue an application for ‘a basic, broad patent filed in all major
industrial nations’ and thereafter ‘follow up with additional patents on
inventions created during the development of the technology.’” (Id. at 16.)
On this record, providing inexpensive licenses to broad patent claims and
trade secrets to desperate partners in a large DRAM market, rebuts any
indication of a nexus and fails to show unobviousness. The record does not
show a nexus between the remanded claims and any alleged license.
9. Multiple Inventions––FTC
Corroborating the Boards findings, the FTC also describes the
following multiple inventions and Rambus’s strategy for marketing:
62. Rambus’s founders intended to improve memory
performance through multiple inventions based on
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modifications of standard DRAMs (see CX 533 at 2), which
could be used separately or in combination(s). The greatest
performance gains would be realized by using these inventions
in combination. Rambus DRAM or “RDRAM” is the name for
the “revolutionary DRAM architecture and high speed chip-to-
chip data transfer technology” that incorporates several of
Rambus s inventions, including its proprietary bus technology.
(RX 81 at 3). Each of the various generations of RDRAM are
manufactured in accordance with specifications established
through a collaboration among Rambus and its DRAM partners.
(Farmwald Tr. 8149, 8241).
(Id. at 16 (emphasis added).)
The FTC findings largely coalesce with and serve to summarize
similar findings on this record:

86. The RDRAM technology in the early 1990’s included
numerous inventions relating to the bus, the interface between
the bus and computer chips, and the DRAM. The 1992
Corporate Backgrounder makes clear that the Rambus “solution
is comprised of three main elements: the Rambus Channel, the
Rambus Interface, and the RDRAM.” (RX 81 at 6). The
Rambus Channel refers to the bus, while the Rambus Interface
and RDRAM refer to other Rambus innovations separate from
the bus. (RX 81 at 7). Each of these elements contain a number
of independent inventions. (RX 81 at 8- 11).

87. RDRAM narrow bus technology contemplates the use of
circuitry on the chips at either end of the bus connection to
optimize the signals flowing across the connection. (Horowitz,
Tr. 8488-90). This circuitry contains high-level logic which
implements a protocol for the chip-to-chip information transfer.
(Horowitz, Tr. 8489-90).

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88. One of the ways that RDRAM technology achieves a high-
speed data transfer over the narrow bus is through
“multiplexing,” which means that the bus can carry different
pieces of information at different points in time. (Horowitz,
Tr. 8620-21). This aspect of the RDRAM interface protocol
means that over several clock cycles the bus can carry a
combination of address and control and data signals on one or
more of the same bus lines. (Horowitz, Tr. 8620-21; see
Rhoden, Tr. 402-03).
(Id. at 19.)
Hence, according to the FTC, Rambus’s main inventions each contain
a number of different inventions. The FTC’s description of the “Memory
Interface Protocol” follows:
54. With respect to the design of the protocol, additional
optimizations developed for high speed operation included
returning a variable amount of data in response to a request
rather than a single bit of data and by putting registers and
associated control circuitry directly on the DRAM. (Farmwald,
Tr. 8115; Horowitz, Tr. 8489-90).

55. With respect to the protocol, Drs. Farmwald and Horowitz
again came up with various innovations. As one example, they
decided to put registers on the DRAM to make the interface
more efficient. (Farmwald, Tr. 8115- 16; Horowitz, Tr. 8506).
These registers would be programmed with parameters, such as
the address range that a particular DRAM would respond
to or the access time of the DRAM. (Horowitz, Tr. 8507, 8509-
10).

56. Drs. Farmwald and Horowitz wanted to make the access
time variable for two reasons. First, if the bus were improved
so that it could operate at a faster clock frequency, the access
time of the DRAM could be adjusted so that it would operate
with that faster clock. Second, a variable access time would
allow the access times of all the DRAMs in a system to be
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adjusted to have the same access time. (Horowitz, Tr. 8510-
11).
(Id. at 15.)
The FTC noted “four . . . technological features,” including DDR
clock circuitry, and DLL (delay-locked loop) on-chip––in the DRAM
interface, as part of the combined features for operating at 500 MHz:
111. The May 7, 1990 technical description described all four
of the technological features at issue in this case. (Horowitz,
Tr. 8525-29).

112. For example, the technical description described dual-
edge clocking in a figure with two input receivers, one clocked
by a signal designated “CLK” (clock) and the other clocked by
the complement of CLK (clock bar), a signal that is zero when
clock is one and vice versa. (R 63 at 10; Horowitz, Tr. 8525-
26). This means that one receiver samples an input when the
clock goes high (the rising edge of the clock) and the other
when the clock goes low (the falling edge). (Horowitz,
Tr. 8526).

113. The May 7, 1990 technical description also described a
delay-locked loop on the DRAM (on-chip DLL feature).
(Horowitz, Tr. 8527-28). A figure in the technical description
shows two delay locked loops generating the internal clocks for
Rambus s design. (RX 63 at 14; Horowitz, Tr. 8527).

(Id. at 23 (emphasis added).)

138. [According to a public document by Rambus] . . . [t]he
technology descriptions included the use of dual-edge clocking:
“(a)n innovative electrical interface permits the Rambus
Channel to operate at 500 Megabytes/second by using both
edges of a 250 clock.” (RX 81 at 8). Moreover, the technology
descriptions explicitly state that Rambus used the on-chip
PLL/DLL technology: “(c)lock skew and capacitive loading are
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minimized by a phase lock loop circuit on board both the
master and the RDRA.” (R 81 at 8).

(Id. at 26 (emphasis added).)
The FTC findings also point to a Rambus 1992 marketing brochure
that states that the “heart of (the Rambus) Interface is high performance PLL
(phase-locked-loop) circuitry which provides the clocks for transmitting and
receiving Rambus Channel data.” (Id. at 27.) Another article cited by the
FTC states that the “Rambus Channel is a 500-Mbyte/s interface, operating
with a 250-MH clock and transferring a byte of data on each clock edge”
and that a “phase-locked loop on each Rambus device limits clock skew
within the chip.” (Id.)
These FTC facts coalesce with the record here. The record shows that
Rambus, which appears to be a successful and innovative company, touted
many of its inventions, which, in 1996, involved over 80 patents, some of
which may have involved DDR DRAMs, although licensing appears also to
have included trade secrets. The record shows that a combination of
unclaimed features is required to support the touted speeds, primarily, the
interface circuitry in a DRAM chip. For example, paragraph 112 of the FTC
Initial Decision supports the Board’s finding above and indicates that the
DRAM chip interface at least needs to have “two input receivers” to support
the DDR. Paragraphs 113 and 138 show that some type of delay lock or
phase lock loop, to correct skew in high speed clocks, implements DDR at
500 MHz. Paragraphs 54–57 imply the requirement of at least four different
facets to support or enhance speed touted in different articles.
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10. Multiple Inventions Disclosed -Murphy Declaration
Mr. Murphy bolsters the voluminous record that shows that that many
unclaimed features were involved in any touted success, praise or other
indicia, and that the synchronous chip interface supported speed––i.e., not
just DDR. For example, Mr. Murphy declares that “one object of the
invention is to ‘use a new bus interface built into semiconductor devices to
support high-speed access to large blocks of data from a single memory
device by an external user of the data, such as a microprocessor, in an
efficient and cost-effective manner.’” (’171 Murphy Decl. ¶ 32 (quoting
original patent application for the ’097 patent, “the ’898 App.,” citation
omitted).) Mr. Murphy describes how the disclosed invention employs two
clocked input receivers in a chip interface to perform the DDR function:
“[E]ach device pin, and thus each bus line, is connected to two clocked
receivers, one to sample the even cycle inputs, the other to sample the odd
cycle inputs.” (Id. at ¶ 55; see also Murphy Decl. ¶ 43 (describing DLL and
two-clock disclosed system) ¶ 51 (describing two clocked input receivers to
enhance performance). Mr. Murphy explains that a Delay Locked Loop
(DLL) in the interface “achieves better performance” in the system and
“improves timing margins.” (Id. at ¶ 29.)
Mr. Murphy also alleges that the “inventions disclosed” were “very
successful.” (Murphy Decl. ¶ 31 (emphasis added).) Mr. Murphy cites faster
memory, and states that other skilled artisans were unsuccessful “without
using the synchronous interface and related inventions disclosed in the ’898
application.” (Id. at ¶ 35 (emphasis added).) Mr. Murphy states that in
addition to the ’937 Patent disclosure, “other patents based on the ’898
application, have been instrumental in increasing . . . DRAM performance.”
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(Id. at ¶ 31.) Mr. Murphy states that another function improves speed:
“access time information” renders possible interleaving, thereby
“improv[ing] the speed and efficiency of the overall system.” (Id. at ¶ 28.)
Mr. Murphy also states that “precharge information” “allows for faster
memory access and reduces power consumption.” (Id. at ¶ 30.)
11. The Micron Website
Rambus-Rea directs the Board to respond to a Micron website: “A
press release issued by Micron Technology, Inc., a Rambus competitor,
referred to the dual-edge data transfer functionality as a ‘revolutionary and
pioneering technology’ that ‘vastly improv[ed]’ the performance of memory
chips. J.A. 1711. The Board did not address any of this evidence.” 731
F.3d at 1257 (quoting the website).
The Micron website now states, in part, the following:
When we introduced our DDR SDRAM, it was
revolutionary and pioneering technology. DDR allows
applications to transfer data on both the rising and falling edges
of a clock signal, doubling bandwidth and vastly improving
performance over SDR SDRAM. To achieve this functionality,
we use a 2n-prefetch architecture where the internal data bus is
double the size of the external data bus, so data capture can
happen two times each clock cycle.
See http://www.micron.com/products/dram/ddr-sdram (attached in
Appendix) (emphasis added).
In line with the findings above, this evidence shows that Micron
touted DDR functionality as revolutionary in a modified synchronous
DRAM––a single chip. The claims at issue do not require a single chip or a
modified single chip. As found above, Inagaki already used DDR in a
synchronous RAM. Whatever the website implies, it was not revolutionary
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to put a DDR feature in a generic synchronous memory device, as
anticipation by Inagaki in Rambus-Rea proves. Therefore, the website
amounts to sales puffery about Micron’s specific implementation of DDR in
a DRAM chip.
Moreover, “to achieve this [DDR] functionality,” Micron employs “a
2n-prefetch architecture where the internal data bus is double the size” of the
external data bus. See id. Micron’s website also notes speeds of up to
400MHz with clocks at 200MHz. Id. The website bolsters the findings
noted above that DDR, and especially DDR at high speeds, requires some
chip interface or hardware architecture to enable that functionality––i.e., 400
MHz speed in Micron’s chip using a 200MHz clock. See id.
The ’937 Patent claims at issue here do not recite anything like this
required chip hardware that the website describes as helping to enable the
touted speeds involving DDR. Micron’s website bolsters the finding of a
lack of nexus, because it, like Rambus’s other statements and the record
evidence about chip interface circuitry, shows that DDR at the touted speeds
requires specific interface hardware.
12. Reasonably Commensurate in Scope
In addition to showing nexus, Ramus must show that its evidence of
unobviousness is “reasonably commensurate” with the claim scope. On the
other hand, Rambus need not “produce objective evidence on
nonobviousness for every potential embodiment of the claim.” Rambus-Rea,
731 F.3d at 1257 (citing In re Kao, 639 F.3d 1057, 1068 (Fed. Cir. 2011).
As discussed above, Rambus-Rea indicated that, on the record before it,
Rambus’s evidence was reasonably commensurate in scope with the claims
because “the claimed dual-edge data transfer functionality is what enabled
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the praised high-speed transfer of data.” Id. Rambus-Rea reasoned that, on
the record before it, the Board “did not point to any contrary evidence.” Id.
Contrary evidentiary findings are discussed above and further below.
In summary to the above, anticipation by Inagaki, and the findings above,
show that a typical DDR memory device, without more, cannot enable the
high speeds touted. At a minimum, a single chip DRAM or other single
chip, with Rambus’s (or similar) modified interface circuitry, including at
least the receiver circuitry, must be recited in the claims at the least to enable
the touted speeds and praise, and to solve any bottleneck problem.
Skepticism or disbelief involves putting PLL or DLL circuits in the DRAM
interface to handle high speeds.
Similar to Therasense, in In re Tiffin, 448 F.2d 791 (CCPA 1971), the
court found that claims that are “too broad” fail to show that the claims are
reasonably commensurate with the scope of the objective evidence of non-
obviousness: “The solicitor's position is that the objective evidence of non-
obviousness is not commensurate with the scope of claims 1–3 and 10–16,
reciting ‘containers’ generally, but establishes non-obviousness only with
respect to “cups” and processes of making them. We agree.” Id. at 792.
By analogy, following Tiffin (and Therasense) means that even if
Rambus shows non-obviousness for the disclosed, but unclaimed five- to
ten-fold speed capability in a modified DRAM chip (analogous to a cup in
Tiffin), Rambus’s claim 1 and 3 are “too broad,” because they embrace
unmodified, slow, DDR multi-chip memory devices (analogous to a
container generally in Tiffin) that do not inherently require or even enable
fast speeds and did not solve any prior art problem. In a similar case, the
court held that evidence of commercial success of dockboards having a bead
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could not show success for claims that did not recite a bead. In re Law, 303
F.2d 951, 1162 (CCPA 1961) (“Thus, assuming the affidavits are a proper
showing of commercial success, they do not show commercial success of
dockboards covered by the appealed claims which are not limited to the bead
of claim 13.”)
Subsequent to Rambus-Rea, the Federal Circuit made a similar ruling
to that in Tiffin and Law. In MeadWestVaco Corp. v. Rexam Beauty and
Closures, Inc., 731 F.3d 1258 (Fed. Circ. 2013), the court held that a district
court erred by considering “secondary considerations of non-obvious [that]
involved only fragrance-specific uses, but the claims now at issue are not
fragrance-specific.” Id. at 1264 (emphasis added). The claims here
analogously are not “speed-specific,” but the relied-upon evidence is.
MeadWestVaco held error because the district court “credited
evidence advanced to show long-felt need and commercial success specific
to the perfume industry,” and the claims were not limited to fragrance-
specific dispensers. See id. (reasoning that “‘objective evidence of non-
obviousness must be commensurate in scope with the claims which the
evidence is offered to support’”)(quoting Ayst Techs., Inc. v. Emtrak, Inc.,
544 F.3d 1310, 1316 (Fed. Cir. 2008) (internal quote citation omitted).)
Similar to the broad memory device claims here, which do not
preclude or require fast speeds handled by a single chip (e.g., DRAM), the
broad claims at issue in MeadWestVaco did not preclude or require
fragrance-specific uses, the broad claims in Law did not preclude or require
beads, the broad claims in Tiffin did not preclude or require cups, and the
broad claims in Therasense did not preclude or require devices that solved
the short fill problem.
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Further, in MeadWestVaco, although the court did not discuss the
issue of inherency or enablement in terms of the relied upon objective
evidence of obviousness, the “dispenser assembly for dispensing a liquid”
recited in claim 15 necessarily could have carried (i.e., “enabled”) a
fragrance-specific liquid, because it recited a generic dispenser: “[S]ome of
the claims . . . are specific to fragrance dispensers and others are directed to
generic dispensers.” Id. at 1262. Therefore, it appears that the claimed
dispenser “enabled” the dispensing of fragrance-specific liquids, because it
could dispense generic liquids. Nevertheless, because the commercial
success and other evidence were “fragrance-specific,” claims 15 and 19 were
not commensurate in scope with the evidence: Claims 15 and 19 did not
require “fragrance-specific” dispensing. Id.
Here, claims 1 and 3 are not “speed-specific”; moreover, they do not
even enable the touted five- to ten-fold speed increase, unlike the enabling
dispenser claims in MeadWestVaco, which were too broad even though
enabling for all fragrances. Even though DDR enables twice the speed,
DDR is in the prior art of Inagaki, and claims 1 and 3 do not enable the
touted 250–500 MHz DRAM speeds. Under MeadWestVaco and
Therasense, simply allowing for fast speeds (like fragrance specific liquids)
is not enough, if the claims do not require the speed (or something close to
it). At the least, on this record, the claims must enable the touted speed, as
Rambus-Rea suggests, and they do not. Without a claimed receiver chip
interface (setting aside the required short bus lengths, and DLL or PLL), the
touted speeds are not enabled because DDR only doubles the speed, and the
touted speeds are not inherent. Nothing recited in the claims enables, let
alone requires, a five- to ten-fold speed increase.
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In summary, the claims here are broader relative to those deemed to
be too broad in MeadWestVaco. Rambus chose not to recite speed range
functionality or structure enabling or requiring that speed. A long line of
precedent dictates that Rambus, without reciting structure or functionality
enabling or pertaining to something close to the touted speed, cannot rely on
the evidence of unobviousness touting that speed.
Kao relies on Tiffin and provides further guidance:
Evidence of secondary considerations must be
reasonably commensurate with the scope of the claims. See In
re Tiffin, 448 F.2d 791 (CCPA 1971)); In re Hiniker, 150 F.3d
1362, 1369 (Fed.Cir.1998). This does not mean that an
applicant is required to test every embodiment within the scope
of his or her claims. If an applicant demonstrates that an
embodiment has an unexpected result and provides an adequate
basis to support the conclusion that other embodiments falling
within the claim will behave in the same manner, this will
generally establish that the evidence is commensurate with
scope of the claims.
Kao, 639 F.3d at 1068 (emphasis added).
Rambus has not produced a persuasive reason explaining why
memory devices falling in the broad claim scope, DDR devices with block
information or synchronous operation codes, which do not support the touted
speeds (because they lack receiver interface circuitry to enable the high
speeds), would be expected to be similar to any commercial device in terms
of success, praise, satisfaction of a long-felt need, or high-speed
functionality. This rationale coalesces with the holding in Therasense,
which downplays evidence if the claims “are broad enough to cover devices
that either do or do not solve the [relied upon] problem.” Therasense, 593
F.3d at 1336 (emphasis added).
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As Therasense reasons:
Because the claims are broad enough to cover devices
that either do or do not solve the “short fill” problem, Abbott's
objective evidence of non-obviousness fails because it is not
“commensurate in scope with the claims which the evidence is
offered to support.” In re Grasselli, 713 F.2d 731, 743
(Fed.Cir.1983); see also In re Kubin, 561 F.3d 1351, 1356
(Fed.Cir.2009) (“[T]he obviousness inquiry requires this court
to review the Board’s decision that the claimed sequence, not
appellants’ unclaimed cloning technique, is obvious in light of
the abundant prior art.” (emphases added)).
Id. (first sentence emphasis added).
Like Therasense, Kao implies a boundary for the breadth of a
reasonably commensurate claim: “As this court recently explained, ‘[i]t
seems unlikely that a company would sell a product containing multiple,
redundant embodiments of the patented invention. . . . Under the [Office’s]
logic, there would never be commercial success evidence for a claim that
covers more than one embodiment.’ In re Glatt Air Techniques, Inc., 630
F.3d 1026, 1030 (Fed.Cir.2011).” Kao, 639 F.3d at 1069.
Similar to the reasoning in Rambus-Rea, Kao also reasoned that “[t]he
Board’s refusal to credit the applicant’s evidence of commercial success
because it was not proven across the entire claimed range of dissolution rates
was improper.” Id. Kao also reasoned that an applicant “need not sell every
conceivable embodiment of the claims in order to rely upon evidence of
commercial success, so long as what was sold was within the scope of the
claims.” Id. (emphasis added).
However, Kao limits protection to “redundant embodiments” within a
claim scope, or embodiments that the applicant shows “behave in the same
manner,” to those that were sold. 639 F.3d at 1068. Rambus does not
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describe anything it sold, rather, Rambus licenses its technology, and fails to
provide a copy of any license or describe the specific terms thereof. In
context to the cited precedent, including Tiffin, Kao’s references to
“redundant embodiments,” “what was sold,” and the same behavior, imply
that a reasonably commensurate claim scope here would include single chip
embodiments having necessary DDR interface receiver circuits that
inherently provide high speed functionality. The central thrust of Rambus’s
arguments, since the appeals culminating in In re Rambus and to the present,
has been that the claims are directed at least to synchronous single chip
memory devices––i.e., devices having a Rambus chip interface designed to
handle high speeds. Much of Rambus’s secondary evidence, including any
licenses, praise, and solution to a long-felt speed problem, relates to specific
hardware interface circuitry in such a chip that at least enables, or
necessarily produces, high speed DDR. Rambus does not argue that its
licensees contemplated selling slow, DDR, multi-chip, memory device
embodiments, which conceptually fall in the claim scope, but that lack the
capability (i.e., the chip receiver interface) for higher speeds. Those would
not be “redundant embodiments.” Cf. Brown & Williamson Tobacco Corp..,
229 F.3d 1at 1130 (consider success “if the marketed product embodies the
claimed features, and is coextensive with them.”)
Showing success for a commercial embodiment, like a modified
DRAM capable of high speeds, within a claim scope that does not recite,
inherently require, or even enable the touted high speeds, is not sufficient to
rebut obviousness across the whole claim scope, because Kao did not
overrule Tiffin, Law, and Therasense. By further analogy, Tiffin’s
commercial cup embodiment was in the scope of the broad “container”
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claims. Nevertheless, the court held that evidence of successful “cup” sales
was not “commensurate in scope with the [container] claims which the [cup]
evidence is offered to support.” See Tiffin, 448 F.2d at 792.
In terms of Kao’s rationale, Tiffin’s broad containers were not
“redundant embodiments of the [cup] invention.” Analogously, a DDR-
modified iAPX memory module is not a redundant, or reasonably close,
embodiment to a touted interface-modified single chip DDR DRAM with
five- to ten-fold high speed capability, even though both fall within the claim
scope. Showing unobviousness for the latter disclosed, but unclaimed
device, does not show the unobviousness for the former. Focusing on what
the claims cover, Rambus does not supply a reason why a DDR-modified
iAPX module would have been expected to garner the praise, skepticism, or
commercial success, or would have been expected to solve the long-felt
need, or would have been expected to operate similarly to single chip
devices having interface receiver circuitry that the record shows must be
present to handle the DDR touted speeds.
Rambus’s evidence pertaining to skepticism about, praise for, and a
solution by, high speed DDR, interface-modified DRAMs, enabled to run on
125–250 MHz clocks, does not satisfy Therasense, Law, Tiffin, Kao, and
MeadWestVaco for claims 1 and 3 at issue here. Rambus’s analysis
essentially agrees with the Board’s: for evidence of praise to be reasonably
commensurate with the claim scope, the claims cannot cover devices that
both solve and do not solve the bottleneck problem. See Rambus Fed.
App.Br. 61 (citing Therasense, 593 F.3d at 1336 for the following
proposition: “finding no long-felt need because the claims were broad
enough to cover devices that did not solve the problem”)) (emphasis added,
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quoting Rambus’s characterization of the case). In any event, the method
claims here do not recite the necessary interface circuitry to enable, much
less require, the touted speed. Merely allowing for, or not precluding, speed,
does not enable the touted speeds, inherently require it, or create a
reasonably close embodiment within the claim scope.
13. Summary
Rambus’s evidence, including, inter alia, commercial success (i.e.,
licenses), praise, skepticism, and solution to a long-felt need, the memory
bottleneck problem, points to unclaimed features, including, at the least, an
interface-modified DDR DRAM chip having unclaimed interface features
required to enable or produce inherently the touted five-fold or ten-fold
speed increases necessary to solve any prior art problem. Rambus fails to
show a nexus to its evidence.
Claims 1 and 3 also cover embodiments that are not redundant to, or
reasonably coextensive with, Rambus’s disclosed, but unclaimed, modified-
interface, high-speed, DDR DRAM embodiments. Claims 1 and 3 cover
devices that both do and do not solve any bottleneck problem. Rambus’s
proffered unobviousness evidence does not satisfy Therasense, Tiffin, Law,
Kao, and MeadWestVaco.
Even if there is some nexus, weak secondary considerations generally
do not overcome a strong prima facie case of obviousness. See Media
Techs. Licensing, LLC v. Upper Deck Co., 596 F.3d 1334, 1339 (Fed. Cir.
2010) (“Even if [the patentee] could establish the required nexus, a highly
successful product alone would not overcome the strong showing of
obviousness.”). “The objective evidence of unobviousness is not evaluated
for its “separate knockdown ability” against the “stonewall” of the prima
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facie case, In re Rinehart, 531 F.2d 1048 (CCPA 1976), but is considered
together with all other evidence, in determining whether the invention as a
whole would have been obvious to a person of ordinary skill in the field of
the invention.” Applied Materials, Inc. v. Adv. Semiconductor Materials
Am., Inc., 98 F.3d 1563, 1570 (Fed. Cir. 1996).
Rambus’s proffered secondary considerations, considered together
with evidence of obviousness, shows that combining Inagaki’s DDR feature
with iAPX’s memory device system would have yielded the predictable
result of sending data using DDR to double data speed without increasing
the clock speed or number of data pins. Inagaki provides the same
motivation for using DDR that the Rambus inventors used to do the same
thing––double data speed in a similar memory device without increasing the
clock speed. The Rambus inventors did not invent using DDR in memory
devices, as anticipation by Inagaki in Rambus-Rea proves. Based on the
foregoing discussion, using the same, well-known, DDR concept, in another
memory device, the iAPX memory module, would have been obvious.
CONCLUSION
Rambus has not shown error in the Examiner’s decision to reject
claims 1–3, 8, 10–16, 18, 23–30, 36–38, and 40 for obviousness over iAPX
and Inagaki. Accordingly, that rejection is sustained. Based on this
decision, there is no need to consider the cumulative rejection over Budde
and Inagaki. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not
reaching obviousness after finding anticipation). The Examiner's decision to
confirm claims 4–7, 9, 17, 19–22, 31–35, and 39 also is sustained, pro
forma.
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This decision contains new grounds of rejection pursuant to 37 C.F.R.
§ 41.77(b) which provides that “[a]ny decision which includes a new ground
of rejection pursuant to this paragraph shall not be considered final for
judicial review.” Correspondingly, no portion of the decision is final for
purposes of judicial review. For further guidance on new grounds of
rejection, see 37 C.F.R. § 41.77(b)-(g). The decision may become final after
it has returned to the Board. 37 C.F.R. § 41.77(f).
37 C.F.R. § 41.77(b) also provides that the Patent Owner, WITHIN
ONE MONTH FROM THE DATE OF THE DECISION, must exercise one
of the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. The Patent Owner may file a response
requesting reopening of prosecution before the examiner. Such a response
must be either an amendment of the claims so rejected or new evidence
relating to the claims so rejected, or both.
(2) Request rehearing. The Patent Owner may request that the
proceeding be reheard under § 41.79 by the Board upon the same record.
Any request to reopen prosecution before the Examiner under 37
C.F.R. § 41.77(b)(1) shall be limited in scope to the “claims so rejected.”
Accordingly, a request to reopen prosecution is limited to issues raised by
the new ground(s) of rejection entered by the Board. A request to reopen
prosecution that includes issues other than those raised by the new ground(s)
is unlikely to be granted. Furthermore, should the Patent Owner seek to
substitute claims, there is a presumption that only one substitute claim would
be needed to replace a cancelled claim.
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Compliance with the page limits pursuant to 37 C.F.R. § 1.943(b), for
all patent owner responses, is required.
The Examiner, after the Board’s entry of a patent owner response and
requester comments, will issue a determination under 37 C.F.R. § 41.77(d)
as to whether the Board’s rejection is maintained or has been overcome.
The proceeding will then be returned to the Board together with any
comments and reply submitted by the owner and/or requester under
37 C.F.R. § 41.77(e) for reconsideration and issuance of a new decision by
the Board as provided by 37 C.F.R. § 41.77(f).

AFFIRMED

ack
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Patent Owner

PAUL M. ANDERSON, PLLC
P.O. BOX 160006
AUSTIN, TX 78716

Third Party

NOVAK DRUCE & QUIGG LLP
(NDQ REEXAMINATION GROUP)
1000 LOUISIANA STREET, FIFTY-THIRD FLOOR
HOUSTON, TX 77002

Appeal 2013-004540
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Patent 6,304,937 B1

APPENDIX