Ex Parte 6304937 et al

Patent Trial and Appeal Board

May 20, 2013

95001188 (P.T.A.B. May. 20, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,188 05/12/2009 6304937 9278.002.937 2299
86497 7590 05/20/2013
Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
05/20/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

RAMBUS INC.
Patent Owner, Appellant

v.

NVIDIA CORPORATION
Requester
____________

Appeal No. 2013-004540
Inter Partes Reexamination Control No. 95/001,188
United States Patent 6,304,937 B1
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appeal No. 2013-004540
Reexamination Control No. 95/001,188
Patent 6,304,937 B1

2

This merged proceeding arose out of a NVIDIA Corporation’s request
for inter partes reexamination of U.S. patent 6,304,937 B1 to Farmwald et
al., Method of Operation of a Memory Controller (issued Oct. 16, 2001, and
claiming priority to Apr. 18, 1990 based on a series of continuation
applications starting with application number 07/510,898) assigned to Patent
Owner Rambus).
The Examiner confirmed claims 4-7, 9, 17, 19-22, 31-35, and 39.
1

Requester NVIDIA originally cross-appealed that decision but subsequently
withdrew its cross-appeal. (See Notice of Withdrawal of Third-Party
Requester’s Appeal and Other Papers (Feb. 17, 2012).) Based on the
withdrawal, the Board declines to consider NVIDIA’s appeal. Appellant,
Patent Owner Rambus, appeals from the Examiner’s decision in the Right of
Appeal Notice (RAN) rejecting claims 1-3, 8, 10-16, 18, 23-30, 36-38, and
40. (See Rambus App. Br., Claims Appendix.)
We have jurisdiction under 35 U.S.C. §§ 134(b) and 315.
We AFFIRM the Examiner’s decision to confirm claims 4-7, 9, 17,
19-22, 31-35, and 39 and the decision to reject claims 1-3, 8, 10-16, 18, 23-
30, 36-38, and 40.

1
The Examiner’s failure to list claim 35 on the cover sheet of the Right of
Appeal Notice (“RAN”), and, like Rambus, listing claim 7 as both
confirmed and rejected, appear to be oversights. (See Rambus App. Br. viii).
According to the body of the RAN, the Examiner refused to adopt the
proposed rejections of claims 7 and 35, Rambus’s claims appendix does not
indicate an appeal of claims 7 and 35, and NVIDIA’s Cross-Appeal does
appeal those claims as confirmed. (See RAN 95, 127-129, 136, 139-140,
142, 174-175, 182, 185-186, 188-192; Rambus Appeal Br. viii, claims
appendix); NVIDIA’s Cross-Appeal ii-iii (withdrawn, but appealing
claims 7 and 35 as confirmed).)
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STATEMENT OF THE CASE
Rambus refers to several related judicial and other proceedings
including inter partes and ex parte reexaminations, International Trade
Commission proceedings, and Federal District Court and Circuit Court
proceedings in its opening Appeal Brief. (See Rambus App. Br. iii-vii.)
Exemplary claims 1 and 3 on appeal follow:
1. A method of controlling a synchronous memory
device, wherein the memory device includes a plurality of
memory cells, the method of controlling the memory device
comprises:
issuing a first operation code to the memory
device, wherein in response to the first
operation code, the memory device outputs
first and second portions of data;
sampling the first portion of data synchronously
with respect to a rising edge transition of an
external clock signal; and
sampling the second portion of data synchronously
with respect to a falling edge transition of
the external clock signal.
3. The method of claim 1 wherein, in response to the first
operation code, the first portion of data is output after a
programmed amount of time transpires.
RAMBUS’s APPEAL
Appellant Rambus appeals the rejection of claims 1-3, 8, 10-16, 18,
23-27, 29, 30, 36-38, and 40 based on the iAPX Manual
2
and the iAPX
Specification,
3
or Budde,
4
and Inagaki.
5
The thrust of Rambus’s numerous

2
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
3
Electrical Specifications for iAPX 43204 Bus-Interface Unit (BIU) and
iAPX 43205 Memory Control Unit (MCU), Intel Corp. (1983). The parties
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arguments is addressed in related reexamination appeals, PTAB 2012-
001976, PTAB 2012-001917, and BPAI 2011-008431, which involve
similar claim terms and the same prior art. For example, the Board held a
method claim 22 in the PTAB `1917 decision having a similar claim scope
to claim 1 here obvious over the combination of iAPX and Inagaki. Rambus
has appealed that decision to the Federal Circuit. A careful review of
Rambus’s arguments and evidence and the Examiner’s findings, shows that
Rambus has not shown that the Examiner erred here. As noted, the
arguments presented here are similar to the arguments presented in
BPAI 2011-008431, PTAB 2012-001917, and PTAB 2012-001976. Those
decisions are adopted and incorporated herein by reference.
6

Rambus’s central arguments are that iAPX does not disclose or render
obvious a synchronous memory chip, and that a person having ordinary skill
in the art in 1990 would not have modified the Memory Control Unit (MCU)
in the iAPX system to utilize both rising and falling edges of the external
clock(s) to output data from the iAPX memory device according to Inagaki’s
teachings.

treat the Manual and Specification as describing the same iAPX system;
therefore, based on arguments of record, the two documents will be referred
to collectively as one “iAPX” document and part and parcel of the same
rejection. (See Rambus App. Br. 21.)
4
Budde et al., U.S. 4,480,307 (Oct. 30, 1984).
5
Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record).
6
Rambus did not appeal the BPAI 2011-008431 decision which reaches a
similar outcome to this decision for claim 14 of similar scope, albeit, with
claim 14 directed to a write operation. After the Board’s decision, the PTO
issued an Inter Partes Reexamination Certificate for U.S. 6,128,184
cancelling claims 1-23 and confirming claims 24-29.
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I. Single Chip
Background
Rambus argues that the iAPX memory module, as disclosed in iAPX,
cannot be a memory device because it is not a single chip. Rambus does not
present separate patentability arguments for the claims on appeal with
respect to the “single chip” issue and primarily focuses on independent
claim 1.
The iAPX Manual discusses the memory module as follows:
The iAPX Manual
A1. Figure 1-2 of the iAPX Manual follows:

Figure 1-2 depicts a memory module comprising a memory storage
array and a MCU (Memory Control Unit). (iAPX Manual 1-3.)
“The storage arrays will typically be constructed with high-density
dynamic RAM (DRAM) components.” The MCU requires a “modest
amount of external logic . . . to interface the MCU to the storage array
RAMs - - for simple configurations, as few as 12 external TTL packages are
required.” (Id. at 1-4.)
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A2. The memory module constitutes a “memory confinement area.”
(iAPX Manual 1-8, 3-2.) The MCU “interfaces memory storage arrays to
the memory bus.” (Id. at 1-4.)
A3. A component level constitutes the lowest level of hardware in the
system, an example of which is a RAM chip. A module comprises a group
of interconnected components. (Id. at 2-1.) The presence or absence of any
module does not prevent communication between any other modules. (Id. at
2-6.)
A4. Another module, which includes a BIU (bus interface unit) and a
processor, is external to the memory modules on a memory bus and serves to
control the memory modules and bus (see A1 supra): “[E]ach processor [or
GDP] and its associated BIUs form a module.” (Id. at 1-3; Fig. 1-2.) “The
master processor and its associated BIUs generate memory bus requests.”
(Id. at 1-8.) “The BIU is also responsible for arbitrating the usage of the
memory bus.” (Id. at 1-3.) The BIU also checks for error by using parity
checking and stops memory requests if errors occur. (See iAPX 1-7, 1-8.)
For example, “[n]o information (control, address, or data) can leave a GDP
confinement area without first being checked for correctness by one of the
BIUs in the module.” (Id. at 1-7.) The BIU also “accepts the access request
from an iAPX 432 processor and, based on the physical address, it decides
which memory control bus(es) will be used to control the access.” (Id. at 1-
3.) The GDP creates a read request and its BIU sends a corresponding
memory address and the request to the addressed memory module which
responds to the request. (See id. at 1-9.)

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Analysis
Rambus disagrees with the Examiner’s finding that the iAPX memory
module reads on the claimed “synchronous memory device” as follows:
Based on the `937 specification and claims, the
prosecution history of related patents, and extrinsic evidence, a
memory device is properly construed as a chip, i.e., an
integrated circuit constructed on a single monolithic substrate,
in which information can be stored and retrieved
electronically.

A “synchronous memory device” is properly
construed as a memory device that receives an external clock
signal which governs the timing of a response to a transaction
request. One of ordinary skill in the art would not consider a
memory control unit to be part of a memory device, but would
instead understand it to be a separate device. Likewise, one of
ordinary skill in the art would not consider a storage array
containing multiple DRAM devices and interface circuitry to be
a single memory device or part of a memory device, but would
instead understand each DRAM device in the array to be a
memory device. Moreover, one of ordinary skill in the art
would not consider the combination of a memory control unit,
multiple memory devices, interface circuitry, and a bus and
various lines to be a “memory device.” (See Murphy Decl.
¶¶ 21, 68-80.)
(Rambus Appeal Br. 3-4 (footnote omitted).)
Subsequent to the filing of Rambus’s Appeal Brief and Rebuttal Brief,
the Federal Circuit decided against Rambus regarding this same claim term
in a related patent to Rambus – claim 18 discussed further below. In re
Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) (holding that the claimed
“synchronous memory device” is not limited to a single chip so that the
iAPX Manual anticipates the sole claim at issue there, affirming the Board’s
decision in BPAI 2011-011178, Reexamination Control No. 90/010,420).
Each of Rambus’s arguments essentially reduce to the single chip argument
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dismissed by In re Rambus as incorrect based on similar arguments,
evidence, and prosecution history. (See Rambus Appeal Brief 2-16.)
The `937 patent involved here and the `918 patent involved in In re
Rambus claim continuity back to the same application.
7
The Board decision,
BPAI 2010-011178, which In Re Rambus affirms, also considered the same
or similar arguments, evidence, and prosecution history.
As In re Rambus also decided, the “synchronous memory device”
recited in claim 18 there reads on the iAPX, “memory module.” As
indicated supra, the iAPX “memory module” includes a memory control
unit (MCU) and numerous DRAM chips. (See A1-A3 (factual findings from
the iAPX Manual).)
Claim 18 from the ‘918 patent at issue in In re Rambus follows:
18. A method of operation of a synchronous memory device,
wherein the memory device includes a plurality of memory
cells, the method of operation of the memory device comprises:
receiving an external clock signal;
receiving first block size information from a bus
controller, wherein the first block size information defines a
first amount of data to be output by the memory device onto a
bus in response to a read request;
receiving a first read

request from the bus controller; and
outputting the first amount of data corresponding to the
first block size information, in response to the first read request,

7
See Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1084-1086,
1091-1092 (Fed. Cir. 2003)(also addressing, inter alia, claim 18 in the
‘918 patent, and finding that the written descriptions of each of four related
Rambus patents, 5,954,804; 5,953,263; 6,034,918; and 6,032,214, are
substantially identical to the written description of the 07/510,898
application to which they, and the `937 patent here, each claim continuity).
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onto the bus synchronously with respect to the external clock
signal.
8

(See In re Rambus at 44; Farmwald et al., U.S. 6,034,918 (Mar. 7, 2000).)

Claim 18 in In re Rambus and claim 1 here each recite the operation
of a “synchronous memory device.” Claim 1 here does not recite a “bus
controller” as claim 18 does. In any event, Rambus does not argue that the
“synchronous memory device” recited in claim 1 here differs from the same
claim term involved in its ‘918 patent.
As noted, in addition to considering similar arguments and evidence,
In re Rambus and the Board also addressed Rambus’s similar prosecution
history arguments. (See Rambus App. Br. 9-11.) For example, the Board
reasoned in its underlying decision that Rambus appealed in In re Rambus as
follows:
Appellant's assertion that Jackson's separate BIU performs the
required claim functions argued (Reply Br. 17) only bolsters the
Examiner's rationale that a complete memory module which has
within it an on-board memory controller (as opposed to an
external or off-board BIU) and performs controller functions
within the module as a unit constitutes a memory device. In
other words, unlike the BIU and array in Jackson, but like the
memory device in the ‘918 patent, the iAPX memory module is
confined to its own area, and receives commands from an
external processor (i.e., the BIU (M2) and also does not impact
communication to the other devices of the system if removed.
(See BPAI 2010-011178 decision at 28 (emphasis added); accord supra
A1-A4 (factual findings from the iAPX Manual).)

8
This claim is also discussed in Rambus Inc. v. Infineon Technologies AG,
318 F.3d 1081, 1091-1092 (Fed. Cir. 2003).
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In BPAI 2011-008431 (reexam. control nos. 95/000183 &
95/001,112) and in BPAI 2010-011178 (reexam. control no. 90/010420), the
Board also addressed Rambus’s similar prosecution history arguments
regarding related Rambus patent’s having a common ancestor application,
and prior art patents to Jackson and Weymouth. Those discussions and
findings are also incorporated herein by reference. For example, the
BPAI `1178 decision notes that Rambus’s prosecution history arguments
refer to “‘memory devices or memory modules’” in Jackson, effectively
equating the two. (See BPAI 2010-011178 decision at 27; accord RAN 41.)
Rambus’s prosecution arguments here significantly omit the
examiner’s reasons for allowance, and also, other arguments Rambus made
during prosecution of its related `804 patent and the `918 patent involved in
the decisions mentioned supra. For example, as the BPAI `8431 decision
explains, “whatever Rambus argued during prosecution [of the `804 patent],
these examiner’s amendments made after Rambus’s arguments signify that
the examiner was not persuaded by Rambus’s prosecution arguments, but
rather, allowed the claims for reasons related to the examiner’s
amendments.” (See BPAI 2011-008431 at 25.)
The Federal Circuit also addressed and dismissed Rambus’s
prosecution history arguments and held that the iAPX memory module
constitutes a “synchronous memory device” as recited in claim 18 at issue
there:
The Board accepted Rambus's characterization of the
iAPX Manual's module as “contain[ing] at least 12 TTL
packaged chips, a memory controller chip, and several DRAM
chips” without further comment on the examiner's control
function analysis. Board Op. at 12. Correctly construed, the
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“memory device” described in claim 18 of the ′918 Patent can
contain more than one chip and may contain a controller that
provides the logic necessary for the memory device to receive
and output specific data, but that controller does not function
like a CPU. Rambus agreed at oral argument that the MCU in
the memory module of the iAPX Manual provided the
necessary logic, but tried to distinguish the MCU because it
“does more than that.” Oral Arg. at 15:22–15:35. But as the
examiner recognized, it is the bus controller (i.e., the “BIU”) of
the iAPX that is akin to the BIU that Rambus distinguished
during prosecution, not the local “MCU” that is within iAPX's
“memory module.” There is no suggestion that the BIU of the
iAPX is within the memory module, rather it is clearly outside
of the memory module, thus satisfying the requirement that the
memory module receive a request from a bus controller. By not
restricting a memory device to a single chip or otherwise
restricting the necessary interface control logic function within
the claims, there is simply no principled way to distinguish the
iAPX Manual's memory module, which contains several chips
and a controller that provides the logic for those chips to
function, from the ‘918 Patent’s device. Thus, substantial
evidence supports the Board's conclusion that the iAPX memory
module reads directly on the `918 Patent’s memory device.
See In re Rambus at 50-51 (emphasis added).
Rambus’s truncated argument, that the iAPX “asynchronous DRAM
devices do not receive a clock signal and are incapable of sampling an
operation code or outputting data in response to an operation code,” focuses
on the incorrect single chip argument dismissed by In re Rambus. (Rambus
App. Br. 2.) In other words, Rambus focuses on what the DRAMs, as
opposed to the MCU interface, receive(s). Rambus does not contest the
Examiner’s finding that the iAPX Manual’s memory module satisfies the
limitations of claim 1 including, receiving external synchronous clock
signals CLKA or CLKB, sampling operation codes (within packets on the
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iAPX MACD bus), and outputting data in response thereto. (See App. Br. 2;
RAN 98-99; Non Final Office Action 29 (August 5, 2010).)
Rambus similarly argues, in truncated arguments, that iAPX does not
disclose other claim features, such as “issuing a first operation code to a
memory device” as claim 1 recites and as claim 30 similarly recites, and
“output driver circuitry to provide an operation code to the memory device,”
as claim 18 recites. (Rambus App. Br. 15.) Again, Rambus’s arguments are
premised on the incorrect single chip argument dismissed by In re Rambus
and fail to show error in the Examiner’s findings. That is, Rambus reasons
that “the bus interface unit [BIU] provides what is alleged to be that
information to the memory control unit [MCU], which as discussed above, is
a memory controller, not a ‘memory device,’ or part of ‘a memory device.’”
(Id. at 15-16.) Rambus also maintains, in a similar truncated and
unpersuasive argument, that “the same reasoning applies to, for example, the
‘block size information’ recited in claim 2.” (Id. at 16 (citing Murphy Decl.
¶¶ 61, 64).)
Rambus also argues that “[t]he memory control unit also performs
functions that are associated with controllers, not memory devices, such as
fault tolerance, error checking, bus arbitration, and request queuing.” (See
Rambus App. Br. 15.) As indicated supra, In re Rambus considers and
dismisses similar arguments, which amount to another form of the single
chip argument. For example, Rambus argued to the Federal Circuit in In re
Rambus that “[a] person of ordinary skill would understand a memory
controller to perform functions such as ‘fault tolerance, error checking, bus
arbitration, and address queuing.’” (Rambus’s In re Rambus Appeal Brief
at 25.)
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In re Rambus also agreed with the PTO’s characterization regarding
the similar interface functionality of the iAPX MCU and claimed memory
device, i.e., the `918 patent’s memory device “provide[s] at least the control
functionality necessary to enable the . . . [device] to interface with the rest of
the system, similar to how the MCU controls the array in the iAPX
Manual.” 694 F.3d at 49 (emphasis added). In re Rambus also reasons as
follows:
Finally, Rambus admits that a key part of the `918 Patent’s
invention was a device with “‘all the functionality’ of prior art
memory boards.” Appellant's Br. 39…. The memory device
must have some functionality—specifically the data receiving
and outputting functions described in claim 18. Thus,
consistent with the specification, prosecution history, and the
Micron district court's construction, we construe a “memory
device” as a component of a memory subsystem, not limited to
a single chip, where the device may have a controller that, at
least, provides the logic necessary to receive and output
specific data, but does not perform the control function of a
CPU or bus controller.

In re Rambus at 50 (emphasis added).
Not surprisingly, like the admission by Rambus quoted above, the
`937 patent, a progeny of a common application with the `918 patent,
identically states that “each memory device is a complete, independent
memory sub-system with all the functionality of a prior art memory board in
a conventional backplane-bus computer system.” (`937 patent, col. 7, ll. 19-
22.) This disclosure shows that memory devices include some control
functionality as In re Rambus reasons. However, Rambus argues, without
explanation, that this disclosure somehow implies that a memory device is
limited to a single memory chip. (App. Br. 5.) The Federal Circuit
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disagrees, as noted supra, characterizing the same or similar statement as an
admission, not a distinction.
Rambus also argues that other claims in other patents reciting an
external memory controller and a memory device preclude the Examiner’s
reading here. (See Rambus App. Br. 11-12) In re Rambus considered and
dismisses similar arguments. See In re Rambus at 48-49. In a related
argument, Rambus also argues that Rambus, during prosecution of the
`918 patent, “noted that . . . the bus interface unit,” like that disclosed in the
prior art patent to Jackson and in the iAPX Manual, “performed the same
functions that the Examiner now alleges are performed by the memory
control unit in iAPX and Budde,” and that the “Office subsequently allowed
the pending claims.” (See Rambus App. Br. 9-10.)
To the contrary, similar to the claims reciting a controller which
Rambus relies on for a supposed distinction, claim 18 in In re Rambus also
recites an external bus controller and a memory device, but the Federal
Circuit still determined that a memory device is not limited to a single chip
and can include the control functions of the iAPX memory control unit
(MCU). Rambus’s prosecution history argument also mischaracterizes the
record of the `918 patent as the Federal Circuit’s reasoning shows. In other
words, the Federal Circuit noted that Rambus referred to a BIU as a memory
controller in its argument to the Federal Circuit: “Rambus’s ‘argument for
allowance [over Jackson] hinged on the BIU—a memory controller— not
being part of the claimed memory device.’ Appellant's Br. 45 (emphasis in
original).” 694 F.3d at 49 (quoting Rambus’s Appellant’s Brief in In re
Rambus). Also, the `937 patent effectively equates external bus and
memory controllers as masters by referring to “master or bus controller
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devices, such as CPUs, Direct Memory Access devices (DMAs).” The
`937 patent distinguishes such masters from “slave devices” such as
“memory devices” wherein “a slave device responds to control signals; a
master sends control signals.” (`937 patent, col. 6, ll. 14-19.)
Rambus also points to disclosures in the `937 patent about reduced
power consumption, findings in related district court litigation, and other
disclosures, as tending to show a memory device is limited to a single chip.
(See, e.g., Rambus App. Br. 3-5.) Similar evidence was involved in the
noted prior decisions and in In re Rambus. In other words, the iAPX
memory module cannot be distinguished based on its power consumption or
size. The claims at issue here simply do not recite reduced power, a single
chip, or such other disclosures which, at best, point to a preferred
embodiment.
Rambus also presents arguments related to a disclosed memory stick
as claimed in claim 4 and as disclosed at Figure 9 of the `937 patent.
(Rambus App. Br. 6.) Claim 4 is not on appeal. Also, In re Rambus
involves similar arguments and evidence. (See In re Rambus at 47
(discussing memory stick).)
Rambus does not present separate arguments with respect to claims 18
and 30, which recite, respectively, “[a] controller device for controlling, the
controller device for controlling,” and “[a] method of operation of a memory
controller device” (emphasis added). While entirely unnecessary to the
holding, claim 18 in the `937 patent shows that even Rambus considers the
term “memory device” to be a generic term which includes a “memory
controller device” and thereby embraces at least three species: memory chip
devices, memory stick devices, and “memory controller device[s].” In any
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event, assuming arguendo that a “memory controller device” is required to
satisfy the preamble of claim 30, the Examiner reads that and the similar
controller recited in claim 18 onto devices “external from the memory
module of iAPX Manual” (RAN 51), in other words, devices such as the
iAPX BIU or the GDP processor, or the module including both, which
control error correction and data flow to and from the memory modules. See
In re Rambus (holding the BIU is an external bus controller). (See also
supra A1, A4 from the iAPX Manual.)
Rambus acknowledges the Board’s `918 decision, i.e., BPAI 2010-
011178 affirmed by In re Rambus, and characterizes it as follows: “In that
decision, the Board affirmed the Office’s overly broad construction of
‘memory device.’ Rambus is appealing that decision.” (Rambus App. Br. 3,
n. 3.) Rambus does not explain why a decision here should be different
from that Board `918 decision. Rather, after a thorough review of Rambus’s
arguments and evidence and the voluminous record, the Board concludes
that Rambus simply does not guide the Board with a principled argument for
distinguishing over the disputed claim term here from the holding in In re
Rambus which affirms the Board’s `918 decision. In particular, Rambus
does not distinguish the common term “synchronous memory device,” a
slave device, at issue in both cases, and as described in the same common
application to the `918 patent and the `937 patent.

II. Dual Clock Edges
Background
Representative claim 1 also requires data sampling on rising and
falling clock edges, or dual edges of an external clock: “sampling the first
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portion of data synchronously with respect to a rising edge transition of an
external clock signal; and sampling the second portion of data
synchronously with respect to a falling edge transition of the external clock
signal.” Claim 1 does not specify how the “sampling” occurs, but claim 1
does not preclude the recited “sampling” from occurring either internally to
the memory device prior to the recited “outputs,” or the recited “sampling”
can further define the clock edges upon which the “memory device outputs
first and second portions of data.”
Rambus’s primary argument, like that in the BPAI `8431,
PTAB `1917, and PTAB `1976 appeals, raises the issue of whether the
Examiner erred in determining that modifying the iAPX MCU to sample
first and second portions of data on rising and falling clock edges of an
external clock, according to Inagaki’s teachings, would have been obvious.
(See App. Br. 16-23.) Rambus attempts to show unobviousness by
maintaining that Inagaki does not disclose a clock and by maintaining
inoperability allegedly because the iAPX timing system shows that data on
the MACD bus which is output from the MCU must be held for at least one
full CLKB cycle. (See App. Br. 18, 22.) Rambus also asserts that secondary
considerations show unobviousness.
Inagaki’s Teachings
I1. Inagaki discloses a method for increasing data rates in block
access memory. As background, Inagaki teaches that conventional methods
to increase data transfer rates in RAMs involved increasing the data bus
width, which adds cost of packaging and pin count, or to increase the data
transfer rate by other methods. (See Inagaki 2.) Inagaki’s solution is to use
dual edges of a clock as quoted as follows.
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I2. “The rise and fall of external clock φ are detected, and clocks φ1
and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift
register. . . . In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed.” (Id. at 4.)
I3 “[T]he present invention presents block access memory that
transfers data with a speed that is twice the conventional speed, by
performing I/O [input/output] of data on every half-cycle of the external
clock that drives the I/O shift register.” (Id. at 3.)
I4. Inagaki refers to “an internal timing generator circuit that controls
the memory cells, read circuit, row and column decoders, data input buffer,
I/O shift register, and data output buffer, wherein; the I/O shift register
performs data input or output every half-cycle based on an external clock.”
(Id. at 3.)
I5. Inagaki also specifically refers to synchronous operation: “Clock
φ1 is generated synchronously with the external clock φ.” (Id. at 5.)
Analysis
Rambus first maintains that using Inagaki’s clocking scheme in the
iAPX system would not have been obvious because Inagaki uses shift
registers and a non-periodic pulse, as opposed to an external clock.
(Rambus App. Br. 18.) Rambus acknowledges that the iAPX system uses
dual edges of two external clocks, CLKA, and CLKB, for other specific
functions. (Id. at 21.) Rambus’s arguments unpersuasively attack the
references separately and assert that the two systems must be bodily
incorporated. See In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) (“[I]t is
not necessary that the inventions of the references be physically combinable
to render obvious the invention under review.”); In re Nievelt, 482 F.2d 965,
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968 (CCPA 1973) (“Combining the teachings of references does not involve
an ability to combine their specific structures”).
In other words, even if Inagaki does not disclose a clock that runs at
all times or only runs while data is being transmitted as Rambus argues (see
Rambus App. Br. 16-17), Inagaki at least uses both rising and falling edges
of a timing reference with a memory device to output data therefrom, and
iAPX uses different external clock edges for the same reason. (See I1-I4;
iAPX Specification at MCU-13, MCU-36; BIU-38; App. Br. 22.) Inagaki’s
teachings apply to timing device edges. Skilled artisans would have been
able to employ such a simple dual edge concept for a similar system using
the memory module of iAPX in order to transfer different portions of data on
both clock edges. As the Examiner reasons, “the BIU of the iAPX system is
fully capable of inputting/outputting data on both the rise and fall of the
CLKB.” (See RAN 63.)
Moreover, contrary to Rambus’s related assertion that Inagaki does
not disclose an “external clock” (Rambus App. Br. 16), Inagaki repeatedly
refers to an “external clock,” and the clock is periodic at least while it
operates (I2-I4): “The rise and fall of external clock φ are detected, and
clocks φ1 and φ2 are generated. . . . . In this way, since one bit is output on
each half-cycle, the operating speed is twice that of the conventional speed.”
(Inagaki at 4 (emphasis added).) A “cycle” and “clock” signify a periodic
signal. Inagaki’s system performs “data input or output every half-cycle
based on an external clock.” (Id. at 2; accord I1-I4).)
In other words, Inagaki discloses periodic clock pulses, contrary to
Mr. Murphy’s and Rambus’s contentions describing them as non-periodic
pulses. (See Rambus App. Br. 16-20 (citing Murphy Decl.).) The “clocks
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φ1 and φ2 drive shift pulses” and are generated by the rising and falling edges
of an external clock. (See I2.) The clocks form part of the “internal timing
generator circuit that controls the memory cells, read circuit, row and
column decoders, data input buffer, I/O shift register, and data output
buffer.” (See I4 (emphasis added).) Inagaki also refers to synchronous
operations (I5), contrary to Rambus’s other related assertions.
Inagaki’s references to external clocks, timing, synchronous
operation, and to “twice that of the conventional speed” (I2), point skilled
artisans to and embrace the well-known, conventional, computer clock – in
other words, the same type of external computer clock generically claimed
in the `937 patent.
9
See In re Paulson, 30 F.3d 1475, 1480-81 (Fed. Cir.
1994) (“a prior art reference must be ‘considered together with the
knowledge of one of ordinary skill in the pertinent art’,” and where the skill
level was “‘quite advanced’ . . . ‘one of ordinary skill certainly was capable
of providing the circuitry necessary to make the device operable for use as a
computer’”) (citations omitted).
Rambus asserts that the Board’s use, in a related decision, of the cited
trade dictionary (supra note 9), lacks evidence to show “that the relied upon
definition was the ordinary meaning.” (Rambus Reb. Br. 2.) To the
contrary, the cited trade dictionary facially describes the ordinary meaning.

9
clock . . . A source of accurately timed pulses, used for synchronization in
a digital computer . . . .” McGraw-Hill Dictionary of Scientific and
Technical Terms 387 (Fifth Ed. 1994). This reference indicates that clock
signals and clock pulses are the same: i.e., “clock signals. See Clock
pulses.” Id. “[C]lock pulses. . . . Electronic pulses which are emitted
periodically, usually by a crystal device, to synchronize the operation of
circuits in a computer. Also known as clock signals.” Id.

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Also, Rambus does not allege or show that the term “clock” carries a special
meaning which diverges from the standard trade definition. (See Rambus
Reb. Br. 1-3.)
Rambus’s prosecution history argument (see Rambus App. Br. 17
(citing Rambus’s U.S. Patent 6,564,281)), and the argument that Rambus
somehow distinguished the type of clocks involved in Inagaki, fails to
address the combined teachings involving the iAPX periodic clocks, or the
notion that skilled artisans, see Paulsen, 30 F.3d at 1480-81, would have
recognized that Inagaki teaches periodic external and internal clocks based
on the ordinary use of the terms, references to timing, and Inagaki’s
synchronous clock operation. (See I1-I5, note 9.) Again, Rambus’s
prosecution history arguments are incomplete and fail to mention that the
examiner of the `281 patent application allowed the claims for reasons
unrelated to those Rambus advances here.
10

10
Rambus made many arguments, basing claim distinctions on recited
elements in the independent claims eventually allowed in the `281 patent
including “precharge information,” “operation codes,” and “automatic[]
precharge.” (See Rambus Appeal Br. Ex. N-10, Amendment in `281 patent
prosecution at 7-8.) The prior `281 patent application examiner did not rely
on Rambus’s external clock arguments and relied on other Rambus
arguments, as follows: “With regard to independent claims 151,166,177 and
186, the examiner agrees with applicants' arguments that the prior art does
not show precharge information in the operation code which control the
automatic precharge of the sense amplifiers.” (See Notice of Allowance 2 in
App. No. 09/969489, U.S. 6,564,281.) Also, while Rambus argued, inter
alia, that “‘the external clock signal’ [as claimed] is a periodic signal used to
orchestrate timing events (e.g., a read operation)” (see Rambus App. Br. 18
(quoting Rambus Appeal Br. Ex. N-10, Amendment in `281 patent
prosecution at 7, n.2)), Inagaki’s external clock is periodic, and Rambus’s
argument was an attempt to distinguish CAS and RAS “input clock signals”
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In other words, the iAPX system employs dual edges of two different
periodic clocks (i.e., CLKA, CLKB), and Inagaki teaches using dual edges
of a single clock in order to provide an increase in the output data rate
relative to a fixed number of data lines to a memory device. (See iAPX
Specification MCU-36; I1-I3.) For example, Inagaki discloses “performing
I/O [input/output] of data on every half-cycle of the external clock that
drives the I/O shift register.” (I3.) Contrary to Rambus’s arguments limiting
Inagaki to pulses, shift registers, and Inagaki’s system (see Rambus App.
Br. 20-21), Inagaki’s teaching applies to all types of clock systems,
including the iAPX clocks. The iAPX system evidences that Inagaki’s
teachings are not limited, because the iAPX system similarly uses both
edges of a periodic clock to transfer data to and from memory modules (i.e.,
“memory devices”) – without a shift register. (See Rambus Reb. Br. 8
(describing “the [iAPX] four-phase clocking scheme” and describing use of
four clock edges, i.e., the rising and falling edges of CLKA and CLKB), id.,
n.5 (“data on the ACD bus is driven on the falling edge of CLKB and
captured on the rising edge of CLKB”); Rambus App. Br. 20 (describing
Inagaki’s system as “different from the periodic CLKA and CLKB signals of
the iAPX system”).)
Using Inagaki’s simple dual edge technique would have amounted to
using a known technique in the iAPX system in a predictable manner for its
intended purpose of providing output data based on dual edges of a clock.
“The combination of familiar elements according to known methods is likely

and “asynchronous strobe signals.” (See id., Amendment in `281 patent
prosecution at 7, n.2.)
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to be obvious when it does no more than yield predictable results.” KSR
Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007)(citation omitted).
According to the references of record, the Murphy declaration, and
other related trial testimony submitted by Rambus, the skill level involved
here is rather advanced in the art of electrical engineering, and specifically,
memory devices and systems. Skilled artisans would have recognized that
Inagaki teaches that data bus systems, like that of iAPX, could have
employed the simple technique of outputting data onto bus lines during the
rising and falling edges of a clock. As indicated, such a technique produces
the fastest possible transfer for a given clock and given number of data lines.
(See I1-I3.) Rambus acknowledges that “[f]aster edges of φ can cause data
to be output faster.” (Rambus App. Br. 21.) Rambus’s argument that the
iAPX system would not run faster “unless the underlying components are
capable of running at a faster rate” merely states the obvious. Rambus’s
related arguments that the iAPX components and Inagaki’s clock are speed
limited (see Rambus App. Br. 20-21) does not mean skilled artisans could
not have matched the two speeds, or found it obvious to do so, given
Inagaki’s clear teachings.
Using both edges of a clock to output data increases the relative data
rate and provides a compact device having a reduced data line bus width and
corresponding pin numbers, thereby saving cost, and providing universal
motivation for employing the technique. (See I1-13.) See Dystar
Textilfarben GmBH & Co. Dutschland KG v. C.H. Patrick Co., 464 F.3d
1356, 1368 (Fed. Cir. 2006) (“[A]n implicit motivation to combine exists …
when the ‘improvement’ is technology-independent and the combination of
references results in a product or process that is more desirable, for example
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because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable,
or more efficient.”)
Rambus argues, under one alternative rationale, that the iAPX system
would be rendered inoperable if some functions are dropped and only one
clock, such as CLKB, is employed to output data. For example, Rambus
argues that modifying the iAPX system to be capable of “‘handl[ing] simple
one-way data (or two-way) data transfers, without arbitration and of the
unneeded functions pursuant to the breadth of claim 1’” renders the system
inoperable.’” (Rambus Reb. Br. 9 (quoting and responding to a related
Board decision).) Contrary to Rambus’s argument, making the iAPX system
simpler, so that it transfers data using a single clock, does not make it
inoperable. Making something simpler does not render it legally or factually
inoperable. If it does, then Dystar’s implicit motivations, making systems
cleaner and faster, would amount to teachings away, as opposed to
motivations.
Rambus similarly maintains that it would have been “unreasonable” to
drop unneeded functions associated with a second clock because that would
be “modifying selected features of the prior art based only on the Farmwald
claims.” (Id. at 9.) To the contrary, the Board and the Examiner rely on
Inagaki, which provides evidence that simple data transfer systems using one
timing mechanism and dual clock edges were desired and well-known.
Precedent, and Inagaki, shows that skilled artisans would have recognized
that one of the clocks and other functions “could be removed if . . . not
wanted.” See In re Sovish, 769 F.2d 738, 743 (Fed. Cir. 1985) (“This
argument presumes stupidity rather than skill.”); In re Kuhle 526 F.2d 553,
555 (CCPA 1975) (deleting a prior art “switch member (and other elements)
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. . . thereby deleting their function, was an obvious expedient.”); In re
Larson, 340 F.2d 965, 969 (CCPA 1965) (obvious to eliminate “a great deal
of additional framework,” including an additional axle, which “serve[] a
particular purpose in that it increases the cargo carrying capacity,” if the
structure and its function are not desired.)
Despite Rambus’s arguments that the iAPX system would not be
faster because of device constraints (Rambus Reb. Br. 7-8), Rambus
concedes that speed increases would result from “providing more frequent
edges of a signal” (id. at 6) and “[f]aster edges of φ can cause data to be
output faster” (Rambus App. Br. 21). Even if the iAPX system was
operating at its capacity when the iAPX manual was published as Rambus
alleges, at the time of the invention, skilled artisans would have recognized
that any speed capacity for sampling (or outputting) data according to the
breadth of claim 1 could have been matched to a clock using rising and
falling edges thereof according to Inagaki’s teachings.
The Federal Circuit rejected a similar inoperability argument by also
focusing on the breadth of the claimed invention and noting that any
“difference [between the prior art optical circuit and claimed electrical
circuit] does not affect the operability of Mouttet’s [i.e., the applicant’s]
broadly claimed device—a programmable arithmetic processor.” In re
Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012) (citations omitted) (also
reasoning that physical incorporation is not required to support
obviousness). So even though iAPX uses two clocks, CLKA and CLKB,
that does not alter the operability of Rambus’s claimed device which only
requires a single clock, or alter the principle of transferring data in the iAPX
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system. The `937 patent indicates that the disclosed system also can operate
with two clocks. (See `937 patent, Fig. 13.)
The principle of operation of the broadly claimed operation of a
memory device involves synchronously outputting data using rising and
falling edges of a single clock signal. The iAPX principle involves
transferring data and other control signals to and from a memory module
using rising and falling clock signals. Inagaki’s similar principle simply
transfers one-way or two-way data on dual clock edges of a single clock.
The iAPX system transfers data to and from on at least two different buses,
the ACD bus and the MACD bus, while performing error correction and
other functions. (See, e.g., iAPX Specification MCU-36; BIU-20, BIU-38.)
Based on Inagaki’s teachings, any alleged complexity which involves
multiple functions, multiple buses, and two clocks in iAPX, is not required
to output data on dual clock edges as broad claim 1 requires.
Rambus’s broad claim 1 only requires one-way data transfer, a read or
“output” operation. (See claim 1.) Using either one or two external clocks,
as alternatively proposed to support obviousness, does not undermine the
broad principle of transferring data either in the claims or in the prior art. In
other words, the iAPX principle of transferring data “is not unique to its . . .
[two clock] operation.” See Mouttet, 686 F.3d at 1332. Also, the Court has
recognized that “the interaction of multiple components means that changing
one component often requires the others to be modified as well.” KSR, 550
U.S. at 424. Making other required modifications to increase the data speed
relative to a given clock and number of data lines, or simply to provide a
predicable variation of outputting data, by using both clock edges, as Inagaki
teaches (I1-I3), does not defeat obviousness or show inoperability.
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Rambus similarly argues that “[c]omplex systems like iAPX’s cannot
have significant features replaced by other features that do not satisfy the
system requirements, especially when such change has no reasonable
expectation of success and does not address any recognized problem.”
(Rambus App. Br. 21.) However, Rambus fails to present evidence that
skilled artisans would have been unable to modify the interrelated parts to
provide a simple system, or even a complex system, satisfying the broad
reach of claim 1. Rambus also maintains that omission of Inagaki’s shift
registers while retaining the function is indicative of obviousness. (Id., n. 9.)
These allegations are not persuasive and impermissibly attack the
references separately. The iAPX system uses both edges of a clock to
transfer data and thereby shows a reasonable expectation of success without
using a shift register. Inagaki shows a simple data transfer system without
complexity. The arguments also are not commensurate in scope with broad
claim 1 which does not have significant interrelated features other than those
required to output data synchronously using two clock edges of a clock
signal. As such, given the claim breadth, skilled artisans could have
modified the iAPX system in view of Inagaki’s clocking scheme by
dropping unneeded functions. For example, with one (or a handful more)
DRAM(s), which the claims do not preclude, and which Inagaki suggests,
arbitration schemes, error correction, and other control signals would not be
required. Cf. Alergan, Inc. v. Sandoz, Inc., 2013 WL 1810852, *6 (Fed. Cir.
2013) (“There is no requirement that one of ordinary skill have a reasonable
expectation of success in developing [the commercial product] Combigan®.
Rather, the person of ordinary skill need only have a reasonable expectation
of success of developing the claimed invention.”)(Emphasis added.) In other
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words, Mouttet, Alergan, and other precedent involve ascertaining the scope
of the claimed invention to determine inoperability and the reasonable
expectation of success.
Moreover, Mr. Murphy, Rambus’s expert, states that sending data on
rising and falling edges “is often referred to as ‘dual edge clocking’ and
allows for data transfer at twice the rate of the external clock signal.”
(Murphy Decl. ¶ 26 (emphasis added).) Mr. Murphy’s statement does not
imply that the inventors of the `937 patent “often referred to . . . ‘dual edge
clocking’” or coined the phrase. Rather, Mr. Murphy’s statements imply
that skilled artisans referred to known technique as “dual edge clocking.” In
any event, Inagaki merely teaches a well-known concept which is applicable
to a variety of clocked memory systems, including the iAPX system.
Rambus also maintains that Inagaki’s speed is limited to its clock, a
period of 100ns, or 10MHz, according to Rambus, and that “the problem
presented by Inagaki is that its alleged clock is not fast enough” and “the
problem is not the speed of the memory.” (See Rambus App. Br. 20.)
Rambus relies on Mr. Murphy, and contends that Inagaki does not solve a
problem that exists in the iAPX system. (See id., citing Murphy Decl. ¶¶
109-119.) Rambus also argues that the iAPX system has the opposite
problem that Inagaki has. Rambus maintains that iAPX memory devices are
too slow and that the iAPX system could not increase in speed “without
speeding up the underlying devices.” (Rambus App. Br. 23.) Rambus
maintains that the iAPX system is limited to 10MHz, and cannot extend to a
speed doubling of 20MHz. (See RAN 57 (addressing Rambus); Murphy
Decl. ¶ 112 (“If the system could operate twice as fast, the clock frequency
would be 20MHz instead of 10MHz.”)
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It is not clear what limits the “cycle” in Inagaki – the system, the
clock, or the memory device. (See Inagaki 3.) However, even if Rambus is
correct that Inagaki discloses a clock speed limit, one of the Rambus
inventors testifies to the opposite effect, i.e., generally that memory devices
(presumably like those in iAPX), could not keep up with faster CPU
systems, which implies that the clocks at the time of the invention were fast
enough.
11
Inagaki similarly teaches that “the demand is increasing to have
higher speeds even for MOS RAM” and that “one method is to make the
circuit operate at a higher speed” or to “increase the bit width . . . to increase
the data transfer rate.” (Id. at 2.) In any event, Inagaki’s central concern is to
teach a method for increasing the data rate for a set data bus width,
regardless of the clock speed, by using both edges of a clock. (See also I1-
I3.)
Despite Rambus’s arguments, the record shows that faster memory
chips and clocks than those disclosed in the iAPX system would have been

11
For example, Rambus expert and inventor Dr. Farmwald testified that
50 MHz computers were available in the late 1980s and that, while DRAM
speed increased at a slower rate than CPUs (which doubled in speed yearly),
solutions were available if expensive. (See Rambus App. Br. Ex. E-5,
Farmwald Trial Dep. 268-270, 275-276).) Another article, published in
1989, shows that an IEEE working group would establish single DRAMs at
500MHz (i.e., “500 hundred million transfers per second”) as a standard and
that there was “no technical reason for this” lack of speed/bandwidth. See
Moussouris, Life Beyond RISC: The Next 30 Years in High-Performance
Computing, Technologic Comp. Let. V. 5, No. 5, p. 2 (July 31, 1989) (cited
in the PTAB 2012-001917 decision at 23, n. 13 as part of the record). A
patent to Bennett, filed in 1986, also of record, refers to a 25 MHz preferred
embodiment, but expected 20ns (50MHz) speed. (See U.S. 4,734,909, col. 9,
ll. 58-60; col. 13, ll. 50-54.)

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available at the time of the invention in 1990. Based on Inagaki’s teachings,
matching the clock’s dual edges to the device limitations, or any other
system constraints alleged by Rambus, would have been obvious for the
purpose of maximizing the output data rate for a given device size or pin
number.
According to Rambus, an iAPX disclosed example of holding MACD
data for one full CLKB cycle shows certain device or system limitations (of
10MHz) and proves that the iAPX MACD data cannot be output from the
MCU on rising and falling edges of a CLKB cycle. (See Rambus Reb.
Br. 7-8, App. Br. 22.) Rambus also argues that “using both edges does not
result in any more bandwidth [i.e., speed] than the faster system using one
edge.” (Rambus App. Br. 23.) However, these arguments merely confirm
that a slower clock using both edges to output data outputs data at the same
rate a faster clock would do using one edge at twice the clock rate, as
Inagaki teaches.
To amplify its argument about device or system limitations and
assuming it would not have been obvious to employ one clock as discussed
above (i.e., under a proposed modification in which data is output on both
CLKB edges in which both clocks, CLKA and CLKB, operate), Rambus
explains that “data must be held for an entire clock cycle in order to be
accurately sent and received.” (Rambus Reb. Br. 7.) In other words,
according to Rambus, outputting data on both CLKB rising and falling edges
would have created corrupted data transfers. (See Rambus App. Br. 22).
However, setting aside that speed increases in memory chips and devices
would have occurred naturally in the industry over time, Rambus’s
arguments also ignore the fact that the BIU captures data from the MCU on
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the MACD bus before a full CLKB cycle transpires – i.e., the BIU captures
MACD data from the MCU on the rising edge of the CLKA cycle which
occurs before a full CLKB cycle transpires. (See MCU-36; BIU-38; BIU-
43; Rambus Reb. Br. 8 (annotating BIU-43 timing diagram).)
12

In other words, since the BIU captures data from a specifically
addressed one of a number of MCUs on the MACD bus before a full CLKB
cycle transpires, this suggests, further in light of Inagaki’s teachings, that the
data alternatively can be sampled before the falling CLKB edge, so that
more data can be output from the MCU on the falling CLKB edge. (See
iAPX Specification BIU-43 (annotated Rambus Reb. Br. 8).) Rambus
agrees that data output on the falling edge of CLKB is captured from the
MACD bus on the rising CLKA edge. (See id. at 9.)
Therefore, because the MACD data is captured at the rising CLKA
edge which occurs between falling and rising CLKB edges, contrary to
Rambus’s unsupported assertions, the iAPX system does not require that the
data must be held for a full CLB cycle. Further, assuming that a separate
data capture CLKA signal would be required (Inagaki teaches it is not),
nothing precludes a simple modification which includes capturing data from
the MACD bus at the falling CLKA edge (which occurs between the rising
and falling CLKB edges (see BIU-43)), and then, outputting more data on
the subsequent falling CLKB edge (see iAPX Specification MCU-41) as
Inagaki suggests. Such a simple modification would satisfy the disputed
claimed limitations even if the two iAPX clocks are employed. As noted,
Inagaki teaches that outputting data on the rising and falling edges of a

12
Rambus maintains that the “ACD DATA” in the timing diagram at
BIU-43 should be “MACD DATA.” (See Rambus Reb. Br. 8.)
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clock, such as the rising and falling edges of CLKB, provides for the fastest
possible data transfer absent adding more data lines or increasing the clock
frequency. (See I1-I3.)
These simple modifications, as described above (i.e., either with or
without a separate CLKA capture signal), would not result in corrupted data.
Rambus does not contend that they would. Also, Rambus fails to explain
how the `937 patent avoids corrupted data. Presumably, applying Rambus’s
arguments to claim 1 should mean data corruption occurs because claim 1
does not require capturing the first portion of data before outputting more
data on the subsequent falling clock edge. (See claim 1.) On the other hand,
as implied above and discussed further below, the record suggests a separate
data capture signal (such as CLKA) would not be required to avoid data
corruption for simple or compact systems which have minimal propagation
delays.
Rambus also maintains that the data capture at the rising edge of the
iAPX CLKA occurs three-quarters of a clock cycle between the two rising
CLKB edges (Rambus Reb. Br. 9), and that the iAPX designers “desired
[this] quarter-cycle granularity” “which allows data to be captured at a time
that would not be possible if only the rising and falling edges of CLKB were
available.” (Rambus Reb. Br. 9.) However, under one of the proposed
alternative modifications discussed above, both CLKA and CLKB would be
available with any “desired quarter-cycle granularity.” Under another
alternative, as discussed above, in small or simple systems, two clocks
would not be desired or required to avoid data corruption, as Inagaki
suggests. Rambus fails to show that the iAPX could not be modified as
described, or that it would have been unobvious to do so.
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33
As Rambus acknowledges, data on another bus, the ACD bus, is input
and output on rising and falling edges of CLKB. (See Rambus Reb. Br. 8,
n.5.) This shows that all the data need not be held for more than a quarter
CLKB cycle, let alone a full CLKB cycle, and that a separate data capture
signal also is not required. This further suggests that Inagaki’s known
method would work and have been obvious in the iAPX system. Rambus
maintains that the noted ACD bus data transfer does not support the
rejection because “data on the ACD bus is driven on the falling edge of
CLKB and captured on the rising edge of CLKB – only one transfer occurs
per clock cycle and data is not output on both rising and falling edges or
input on both rising and falling edges.” (See id.) Rambus’s main point, that
the ACD transfer does not satisfy the claims, is not material to the
obviousness analysis.
Rather, the disclosed ACD transfer implies that because data from and
to another processor can be input and output by the BIU on the successive
rising and falling CLKB edges (see BIU-20; BIU-38), the BIU also can
output data on both CLKB edges. That is, the disclosed ACD data transfer
apparently does not require a separate CLKA signal to capture data output
on the ACD bus. For example, the processor apparently outputs data and the
BIU inputs it on the rising CLKB signal, and the BIU outputs data and the
processor inputs it on the falling CLKB signal. (See id.). These BIU ACD
transfers occur virtually at each CLKB edge and further suggest the disputed
claim limitation could similarly occur for data transfers between the BIU and
MCU on the MACD bus, at least in simple single memory module systems,
with one or two modules having a limited number of DRAMs, for example,
as suggested further by Inagaki.
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34
In other words, the processor and its BIU are close together in a single
module, whereas multiple memory modules are implicitly spread out along
the MACD memory bus. (See BIU-20.) This implies, per the ACD data
transfer disclosed by iAPX and the Inagaki single clock system, that singular
memory modules or devices, as set forth in broad representative claim 1, and
as disclosed by Inagaki, simply do not require a separate clock to indicate
when to capture data. Implicit or suggested in the comparison is that
propagation delays would be minimized, and data corruption would not be a
problem with simple systems or relatively short data transmissions.
Under another rationale, the proposed combination does not require
dropping iAPX functions or modifying the underlying timing of the iAPX
system. That is, Inagaki suggests a modification in which a slower external
clock’s rising and falling edges triggers the rising edges of the iAPX clock.
In Inagaki at Figure 4, a slower external clock φ has rising and falling edges
corresponding to and triggering faster clocks φ1 and φ2, suggesting a similar
external clock to trigger signals such as iAPX CLKA and CLKB signals or
modified versions thereof. (See Inagaki Fig. 4; I3, I4.) This concept also is
heuristically shown in the iAPX Specification at BIU-41 which shows an
Initialization Timing diagram. Therefore, Inagaki suggests a similar slower
external clock to trigger signals such as iAPX CLKA and CLKB signals or
modified versions thereof, thereby rendering obvious the disputed
limitations of claim 1 under this alternative rationale. (See e.g. Inagaki
Fig. 4; I1-I4.)
Rambus responds to this rationale by arguing with respect to Inagaki’s
Figure 4 that Inagaki does not show how “it is determined when φ1 should
transition from high to low . . . and that transition is unrelated to any
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Patent 6,304,937 B1

35
transitions in φ.” (See Rambus Reb. Br. 10, 1 (addressing the
PTAB 2012-000171 decision – referring to the Board’s “‘097 Decision” – a
decision involving the `097 patent, reexamination control no. 95/001,134.)
Rambus also maintains that Inagaki does not provide any teaching as to how
the CLKA and CLKB edges in iAPX can be generated from a slower clock.
(See Rambus Reb. Br. 10.) Contrary to Rambus’s argument, Inagaki clearly
shows the relationship in Figure 4 and states that “[t]he rise and fall of the
external clock φ are detected, and clocks φ1 and φ2 are generated.”
(Inagaki 4.) Inagaki refers to the clock relationship and system in general as
involving a “conventional example.” (Id.)
Rambus does not maintain, let alone show, that Inagaki’s triggered
clock transitions are not enabled. Rambus’s argument amounts to asserting
that skilled artisans would not have been able to create an internal clocking
scheme by using an external clocking scheme. However, Inagaki clearly
portrays such a scheme in Figures 4 and 6. (See also I4 (discussing internal
and external clocks).)
13

In summary, Inagaki shows that using both clock edges to transfer
data faster was well-known for transferring data in the fastest manner
possible. (See I1-I4.) Contrary to Rambus’s arguments, the broad reach of

13
Rambus also challenges the reliance on the heuristic concept depicted in
BIU-41 as employing an “INIT” signal to trigger the clock. According to
Rambus, the “INIT” signal is not a clock. (See Rambus Reb. Br. 10, n. 6.)
The Board only points to the example to serve as a vehicle to explain the
proposed rationale, and to bolster the showing in Inagaki that it was known
to use a slower trigger, such as the iAPX “INIT” signal, to trigger two faster
rising edges in CLKA from slower rising and falling edges in the “INIT”
signal. The figure is described as “Initializing Timing,” so the initialization
signal triggers or initiates the timing.
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36
the claims does not require two clocks, two-way data transmission, buffer
directional control, arbitration, or error-checking. Skilled artisans would
have known how to modify the iAPX system to handle the one-way or two-
way data transfers embraced by claim 1 using a single clock as Inagaki
suggests, in order to maximize data speed for a given number of data lines
and a given external clock in simple systems. As a second alternative, using
both clocks of the iAPX system modified to output data on successive rising
and falling edges of CLKB would have been within the skill of ordinary
artisans and an obvious variant well known in the art for transferring data as
Inagaki teaches. As a third alternative, using Inagaki’s slower clock’s rising
and falling edges to trigger the rising CLKB edges would have amounted to
a simple modification well known and suggested in the art for producing
clock edges.
Rambus argues that the rejection of claim 3 should be reversed
because the “s” value relied upon by the Examiner is not the “programmed
amount of time” to determine when data is output on the MACD bus in the
iAPX system. (App. Br. 24.) Rambus characterizes the issue as follows:
The Examiner agrees that the “s” value of iAPX does not
determine when data is actually output onto the MACD bus.
(RAN at 65.) However, the Examiner asserts that “[t]he claim
language reads on a scenario in which data is output anytime
after a programmed amount of time transpires” and “the claim
does not require the output to be responsive to the programmed
amount of time.” (Id.)
(Rambus App. Br. 23.)
Rambus’s contentions imply that Rambus agrees with the Examiner
that claim 3 literally reads on the iAPX system, because “the first portion of
the data is output [sometime] after a programmed amount of time expires.”
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Patent 6,304,937 B1

37
In other words, Rambus agrees that, “anytime,” i.e., sometime after the
programed amount of time, the first portion of data is output. (See Rambus
Appeal Br. 23.) As the Examiner reasons, claim 3 does not specify a
certain amount of time or even require the output to be responsive to the
programmed time. (See RAN 65.) Rambus focuses on the `937
specification, but that focus does not show that any claim term carries a
special meaning or that the specification somehow imparts a limitation
overcoming the iAPX system. (See Rambus App. Br. 24.)
What Rambus shows is that claim 3 is broader than the disclosure.
Rambus relies on the following disclosures in the `937 patent:
“After a specified access time the slave(s) respond by returning
one or more bytes (8 bits) of data or by storing information
made available from the bus. More than one access time can be
provided to allow different types of responses to occur at
different times.”, 8:48-55, “To reduce the complexity of the
slaves, a slave should preferably respond to a request in a
specified time. . . . The time for this bus access phase is known
to all devices on the bus-each master being responsible for
making sure that the bus will be free when the bus access
begins.”, 9:16-20, “The time after which a data block is driven
onto the bus lines is selected from values stored in slave access-
time registers. The timing of data for reads and writes is
preferably the same . . . .”)

(See Rambus App. Br. 24 (quoting the `937 patent, emphasis supplied).)
That “a slave should preferably respond to a request in a specified
time” reveals that claim 3 is broader than this preferred embodiment.
Claim 3, for example, does not recite that “the first portion of the data is
output [in response] to a programmed amount of time expires,” as the
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Patent 6,304,937 B1

38
Examiner determined. Therefore, Rambus does not show error in the
Examiner’s determination.
Rambus does not present separate patentability arguments for the
other claims. Rambus’s secondary considerations of non-obviousness are
addressed below and do not outweigh the Examiner’s initial showing and
response to the secondary considerations. Based on the foregoing discussion
and the discussion below regarding secondary considerations, Rambus has
not shown error in the Examiner’s decision to reject claims 1-3, 8, 10-16, 18,
23-30, 36-38, and 40. As such, it is not necessary to reach the Budde based
rejection. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not
reaching obviousness after finding anticipation).
Secondary Considerations
Rambus contends that secondary evidence supports unobviousness.
(Rambus App. Br. 25-28.) The evidence fails to establish a nexus because
any success likely flows from a variety of several unclaimed features touted
here or in other Rambus proceedings or patents. Such unclaimed, but
disclosed features, include eight data lines, small DRAM sizes with minimal
bus loading, multiplexed bus architecture and device interfaces, packetized
control, unique device identifiers, time access and arbitration schemes, a
500 MHz data rate, controlled-impedance, double terminated lines, reduced
power and production costs, and memory devices having all the functionality
of prior art circuit boards. (See `937 patent, Abstract, col. 3, ll. 23-48; col. 4,
ll. 22-57; col. 7, ll. 8-31; col. 9, ll. 39-65; col. 12, ll. 45-59; col. 14, ll. 46-65;
Murphy Decl. ¶¶ 31-36.) See also Rambus Inc. v. Infineon Technologies
AG, 318 F.3d 1081, 1095 (Fed. Cir. 2003) (“The present invention is
designed to provide a high speed, multiplexed bus’” (quoting Rambus’s
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Patent 6,304,937 B1

39
related `918 patent, col. 5, ll. 36-46), but “the prosecution history shows that
a multiplexing bus is only one of many inventions disclosed in the
‘898 application.”)
Mr. Murphy testifies that “[t]he original disclosure includes a number
of different inventions, and while some inventions or embodiments may
include a multiplexed bus, many do not.” (Murphy Decl. ¶ 38 (emphasis
added).) Mr. Murphy also testifies that in “[a]nother invention,” the
inventers “included complex delay locked loop circuitry on the synchronous
memory device, as recited in claims 20 and 21 of the `937 patent.” (Id. at
¶ 33.)
The `937 patent shows still more inventions. For example, “[t]he bus
supports large data block transfers and . . . transactions to allow a user to
achieve high bus utilization. This ability to rapidly read or write large block
of data to one single device at a time is an important advantage to this
invention.” (`937 patent, col. 4, ll. 17-21.) Also, “prior art devices need to
be modified so they can provide and accept data to and from the bus at the
peak data rate of the bus. This requires changes to the column access
circuitry in the DRAM . . . .” (Id. at col. 29-31.) One inventor (see supra
note 11) testifies that the number of data pins are “like the lanes on a
freeway, the more lanes I have, the more cars I can send” (Ex. E-5 at 279),
that size is a factor in speed with smaller sizes being faster due to shorter
signal distances traveled (i.e., shorter propagation delay) (id. at 281), and
that the inventor “set [him]self to build a DRAM that would be at . . . 500
Megahertz . . . . at 8 bits wide” (id. at 277).
Rambus does not show how the invention claimed here has any of
these required attributes, i.e., a nexus. For example, claims 21 and 22 have
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Patent 6,304,937 B1

40
been confirmed, and delay locked loops are not required in the claims at
issue here. Some of the dependent claims arguably require data blocks (see
claim 23) but not data block transfers to a single device which the
specification touts as important; further, Rambus does not point to claim
limitations which require other touted advances: a reduced size chip,
500 MHz speed, 8 data pins, modified column access circuitry, or other
features listed above and below. As prior decisions by the Board note,
Rambus relies upon the same evidence of secondary considerations it has
provided in multiple pending inter partes reexaminations. Different claims
in the different proceedings have varying scope. Rambus’s proffered
evidence also is short on objectivity and relies on interested witnesses,
including the named inventors. Rambus has not established a sufficient
nexus to the claims as the Examiner determined. (See RAN 66-72.)
As the Examiner essentially reasons, Rambus’s evidence does not
demonstrate that any success was due solely or even mainly to the claimed
features, or to claimed features that were not already known in the prior art.
Rambus does not rely specifically on licensing in the appeal, although
Mr. Murphy does. (See Murphy Decl. ¶ 34; RAN 70.) In any event,
Rambus does not provide evidence showing what claimed or unclaimed
features any of the licenses involve. Also, it is well known and settled law
that competitors often take licenses for commercial or other reasons having
nothing to do with unobviousness. (See RAN 70.)
Rambus points to the use of dual clock edges, but speed increases
based on the double data rate concept was well-known as Inagaki shows and
as Mr. Murphy implies as noted above. Rambus also points to operation
codes as speed enhancers, but iAPX, which Rambus characterizes as speed
Appeal 2013-004540
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Patent 6,304,937 B1

41
limited, discloses such codes according to the Examiner’s findings as
mentioned supra. (See discussion supra and Rambus App. Br. 26.) In any
event, the claimed features relied upon by Rambus were standard features in
memory devices as iAPX and Inagaki show. Rambus’s comments with
respect to claim 3 rely on unclaimed features, for the reasons discussed
supra. (See Rambus App. Br. 26; RAN 67.)
Single chip and other synchronous memory devices and operation
codes also were known according to Bennett. Bennett is discussed in the
RAN and several related Board decisions (see, e.g., PTAB 2012-1976).
Further, according to another reference of record, “the most popular form of
read/write memory is the semiconductor DRAM.” (Wicklund,
U.S. 5,159,676, col. 1, ll. 36-39, see RAN 85 (discussing Wicklund).)
Hence, the record suggests that a large part of any alleged commercial
success by Rambus would have been due to “the most popular” memory
chip, a DRAM chip, in general (or to Bennett’s known synchronous memory
chips in general). Cf. In re DBC, 545 F.3d 1373, 1384 (Fed. Cir. 2008)
(Board’s conclusion of nonobviousness supported, the Board finding, inter
alia, that “evidence in the record suggested that the success of XanGo™
juice may be due to other factors-for example, the increasing popularity of
the mangosteen fruit in general” ).
The Federal Circuit further reasoned in DBC that
. . . DBC has done little more than submit evidence of sales.
However substantial those sales, that evidence does not reveal
in any way that the driving force behind those sales was the
claimed combination of mangosteen fruit, mangosteen rind
extract, and fruit or vegetable juice. Nor is there any evidence
that sales of XanGo™ juice were not merely attributable to the
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42
increasing popularity of mangosteen fruit or the effectiveness
of the marketing efforts employed.

Id. at 1384 (emphasis added). See also Ormco Corp. v. Align Technology,
Inc., 463 F.3d 1299, 1312, 1313 (Fed. Cir. 2006) (“[I]f the feature that
creates the commercial success was known in the prior art, the success is not
pertinent.” Reasoning that success that is due “‘partially’ to claimed
features” and to unclaimed features and/or other features already in the art
lacks the requisite nexus to show unobviousness.) (Citations omitted).
Under Rambus’s theory, but contrary to DBC and Ormco, Rambus
can claim a broad memory device, such as a synchronous memory device,
and show commercial success even if the claim only embraces a minor
component which may contribute to success –e.g., double data rate and
operation codes – and even though such concepts were known well in the
prior art, and a myriad of other factors likely contributed to any success.
Under In re Tiffin, 448 F.2d 791 (CCPA 1971) (commercial success
evidence of thermoplastic foam cups is not commensurate in scope with
broad claims directed to thermoplastic foam containers), this sort of
evidence does not establish nonobviousness.
While Rambus also argues that the claims solve a memory
“bottleneck” problem and obtain high-speed performance (Rambus App.
Br. 26), the inventors solution to the bottleneck problem involves a modified
DRAM having 8 data pins and operating at 500Mhz as discussed supra,
whereas the claims here are not limited to a DRAM, a single chip, a set
speed, or any number of pins. The claims do not recite other sufficient and
necessary circuitry to obtain such speed. Moreover, Dr. Farmwald testified
that “even up into the early part of the ‘90s, it [speed] wasn’t going to be a
Appeal 2013-004540
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43
problem.” (See Rambus App. Br. Evidence Ex. E-5 at 276).) In other
words, Dr. Farmwald may have solved a problem predicted to occur in the
relevant future for memory devices at the time of the invention, but not a
long-standing problem. Any speed problem had already been solved by
generic memory modules or boards which were capable of relatively high
speeds according to Dr. Farmwald.
Rambus’s allegations of recognition and praise for the “‘high
bandwidth memory-interface technology’” and bandwidth advances “‘as a
result of the ideas [Dr. Horowitz] pioneered’” (Rambus App. Br. 27) also
point to a lack of nexus as to any success or praise. The devices claimed
here have no bandwidth limitation, let alone a “high bandwidth memory-
interface,” or the other limitations directed to the myriad other “ideas
[Dr. Horowitz] pioneered” – whatever they may have been.
As to alleged skepticism “about many of the specific features of the
technology,” including “a 500 megabit per second DRAM data rate,” and
because “putting registers on DRAM was too expensive . . . and that one
could not put a phase locked loop or a delay locked loop on the DRAM
itself,” this skepticism has nothing to do with claimed features. (See id.) As
noted, the data rate, a DRAM, and a phase locked or delay locked loop, are
not required in the claims at issue here.
Based on the foregoing discussion, the record suggests that the
proffered evidence is not commensurate with the claim scope and lacks a
nexus thereto. Rambus has not demonstrated that any success is not due to
popular DRAMs in general, synchronous memory chips in general, or, to a
whole host of unclaimed features, including the unclaimed but touted
multiplexed bus interface, high bandwidth and/or speed, and other
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Patent 6,304,937 B1

44
unclaimed circuit features, such as the identification feature, arbitration
control features, low capacitance and power, precharging circuitry, and
block data transfer circuitry. The record indicates that such features (and
other pioneering ideas) would have been required to obtain the touted high
speed from a single DRAM upon which any alleged success appears to be
based. See Infineon, 318 F.3d at 1095 (quoted supra, mentioning Rambus’s
high speed multiplexed system).
Rambus has not established that a manufacturer would have
purchased a synchronous memory device having multiple chips, operation
codes, and double data rate capability merely because of such capabilities.
The claims read on slow memory devices, so that even if some evidence
shows that some fast DRAM memory devices were successful, after careful
consideration of the record, the obviousness of combining rising and falling
timing edges to output data as Inagaki suggests, with the iAPX synchronous
memory system which similarly employs dual clock edges, outweighs the
proffer of secondary considerations.
NVIDIA’s CROSS-APPEAL
As indicated supra, NVIDA withdraws its cross-appeal to the Board.
Hence, NVIDIA does not appear to dispute the Examiner's refusal to adopt
or maintain NVIDIA’s proposed rejections of claims 4-7, 17, 19-22, 31-35,
and 39 under 35 U.S.C. § 103(a) as unpatentable over several different
grounds of rejection. (See NVIDIA Cross-Appeal Brief 1-4 (listing 84
different groups of proposed rejections).)
In view of Cross-Appellant NVIDIA’s withdrawal of its appeal, we
affirm, pro forma, the Examiner's decision to confirm claims 4-7, 9, 17, 19-
22, 31-35, and 39.
Appeal 2013-004540
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Patent 6,304,937 B1

45
CONCLUSION
Rambus has not shown error in the Examiner’s decision to reject
claim 1-3, 8, 10-16, 18, 23-30, 36-38, and 40 for obviousness over iAPX and
Inagaki. Accordingly, that rejection is sustained. Based on this decision,
there is no need to consider the cumulative rejection over Budde and
Inagaki. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not
reaching obviousness after finding anticipation). The Examiner's decision to
confirm claims 4-7, 9, 17, 19-22, 31-35, and 39 also is sustained, pro forma.
AFFIRMED

ak

Patent Owner:

Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716

Third Party Requester:

Novak Druce & Quigg, LLP
(NDQ Reexamination Group)
1000 Louisiana Street
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rd
Floor
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MCGRAW-Hill

ICTIONARY Of

CllNTlflC AND

ICHNICAl

~ IRMS

Fifth Edition

Sybii P. Parker
Editor in Chief
McGraw-Hili, Inc.

New York San Francisco Washington, D.C.

Auckland Bogota Caracas Lisbon London Madrid Mexico City Milan

Montreal New Delhi San Juan Singapore Sydney Tokyo Toronto

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being clipped or sheared in finishing. Also known as
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similar temporary connector at one or both ends. {'klip
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circuit See limiter. {'klip-il) ,s3l'k:lt I
edge [MET) Area of a forging where flash is re­
{ 'klip'iQ ,ej I
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fabric See clip-dot fabric. {'klip ,spat ,fab,rik I
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clock method [ORD] Method of calling artillery shots by
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clock motor See timing motor. I 'kllik ,mOd-:lr I
clock oscillator [ELECTR] An oscillator that controls an elec­
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clOCk signals See clock pulses. {'k1lik ,sig-n~lz I .
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clonorchiasis [MED] A parasitic infection of humans and
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Clonothrix [MICROBIO) A genus of sheathed bacteria; cells
are attached and encrusted with iron and manganese oxides, and
filaments are tapered. {'kUin~,thriks I
clonus [PHYSIOj Irregular, alternating muscular contractions
and relaxations. I 'klo'o;.lS I
close [COMPUT sCll To make a file unavailable to a computer
program which previously had access to it. [METEoROL) Col­
loquially. descriptive of oppressively still, warm, moist air, fre­
quently applied to indoor conditions. {klos I
close-control radar [ENG} Ground radar used with radio to
position an aircraft over a target that is normally difficult to
locate or is invisible to the pilot. I :klOs k.,n'trol 'ra,diIr 1
close-coupled pump [MECH ENG] Pump with built-in elec­
tric motor (sometimes a steam turbine), with the motor drive
and pump impeller on the same shaft. I :klOs :k;;lp'<')ld 'p<')mp I
close coupling [ELEC] 1. The coupling obtained when the
primary and secondary windings of a radio-frequency or inter­
mediate-frequency transformer are close together. 2. A degree
of coupling that is greater than critical coupling. Also known
as tight coupling. I :klos 'k<')p-lig I
closed aerodrome [NAV1 An aerodrome at which ceiling and