Ex Parte 6272646 et al

Patent Trial and Appeal Board

Mar 26, 2014

95001550 (P.T.A.B. Mar. 26, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,550 02/18/2011 6272646 3059.008REX0 2728
26111 7590 03/27/2014
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
SAGER, MARK ALAN
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
03/27/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
XILINX, INC.
Requester

v.

INTELLECTUAL VENTURES II LLC
Patent Owner and Appellant
____________________

Appeal 2013-008748
Reexamination Control 95/001,550
Patent US 6,272,646 B1
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, MEREDITH C. PETRAVICK, and
WILLIAM V. SAINDON, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
In this inter partes reexamination proceeding, Patent Owner
Intellectual Ventures II LLC appeals under 35 U.S.C. § 134(b) (2002)
from the final decision of the Examiner unfavorable to the patentability
of claims 1-42, each of which is original, amended, or added to
U.S. patent 6,272,646 (“the '646 patent”). Oral hearing was held on
October 16, 2013. We have jurisdiction under 35 U.S.C. § 315 (2002).
We affirm-in-part.

Invention
The '646 patent describes a phase lock loop (PLL) with a
programmable logic device (PLD) for realizing a variety of clocking options.
'646 patent Abstract.
Figure 1 of the '646 patent is reproduced below.
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Figure 1 is said to be a block diagram illustrating a complex
programmable device (CPLD). Id. at col. 2, ll. 21-23. CPLD 10 includes an
input section 12, logic sections 14 and 16, and a Programmable Interconnect
Matrix (PIM) 18. The input section includes PLL structure 20. The PLL
structure produces a number of individual clock signals (e.g.., four) that are
presented to PIM 18. Id. at ll. 43-58. Each of the clock outputs may be
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configured to operate at an independent frequency that can drive the
individual logic blocks of the programmable logic device. Id. at col. 2, l. 59
– col. 3, l. 8; Fig. 2.

Claims
Claims 1-42 are subject to reexamination. The '646 patent contains 20
claims. Claims 1, 12, and 18 are independent. Patent Owner has submitted
proposed amendments to claims 18, 19, and 20, and has further submitted
proposed new claims 21-42.
Claims 1 and 12, reproduced below, are representative.

1. A device comprising:

a programmable logic circuit configured to (i) generate
one or more control signals and (ii) receive one or more clock
signals; and

a phase lock loop circuit configured to generate said one
or more clock signals, each capable of oscillating at a different
one of a plurality of frequencies, said clock signals generated in
response to (i) a reference clocks [sic] (ii) said one or more
control signals, and (iii) one or more of said clock signals
wherein said programmable logic circuit and said phase lock
loop circuit are integrated on a single circuit.

12. A method for dynamically changing a frequency of
operation of a programmable logic circuit comprising the steps
of:

(a) configuring said programmable logic circuit to
generate one or more control signals and receive one or more
clock signals; and
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(b) generating said one or more clock signals with a
phase lock loop circuit, each of said one or more clock signals
being:

(i) capable of oscillating at a different one of a
plurality of frequencies, and

(ii) generated in response to a reference clock, one
or more of said clock signals, and said one or more control
signals.

Prior Art

Graham US 5,204,555 Apr. 20, 1993
Parker US 5,260,979 Nov. 9, 1993
Winen US 5,276,716 Jan. 4, 1994
Wright US 5,349,544 Sept. 20, 1994
Davis US 5,394,114 Feb. 28, 1995
McBride US 5,594,376 Jan. 14, 1997

Intel’s FLEXlogic FPGA Architecture, by Daniel Smith, IEEE, 1993
(“Intel”).

Patent Owner’s Contentions
Patent Owner contends that the Examiner erred in entering the
following grounds of rejection.

Reference(s)

35 U.S.C. Section

Claims

Wright

102(b)
1-4, 6, 10-13, 16-18,
21, 31, and 33
Wright, McBride 103(a) 5 and 14
Wright, Winen 103(a) 7-9
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Reference(s)

35 U.S.C. Section

Claims
Wright, Parker 103(a) 7-9 and 15
Wright, Graham 103(a) 19
Wright, Graham,
McBride
103(a) 20
Wright 103(a) 25-29 and 37-40
Wright, Intel 103(a) 22-24, 30, 32, 34-36,
41, and 42

ANALYSIS
Introduction
In making our determinations, we have considered the following
declarations filed by the parties:

For Patent Owner
James Stine, Ph.D., June 28, 2011, App. Br. Ex. 12 (“Stine Decl. I”);
James Stine, Ph.D., Feb. 1, 2012, App. Br. Ex. 25 (“Stine Decl. II”);
Frank Koperda, Feb. 1, 2012, App. Br. Ex. 26 (“Koperda Decl.”);
Earl Swartzlander, Jr., Ph.D., Feb. 1, 2012, App. Br. Ex. 27
(“Swartzlander Decl.”).

For Requester
Ray Mercer, Ph.D., July 27, 2011, Resp. Br. Ex. 1 (“Mercer Decl. I”);
Ray Mercer, Ph.D., Feb. 29, 2012, Resp. Br. Ex. 2 (“Mercer Decl.II”).
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Patent Owner argues claims 1 and 12 together, as if they were
identical in scope. However, first we will consider Patent Owner’s
arguments in relation to claim 1 before considering claim 12. Further, we
will consider other claims in view of Patent Owner’s arguments set out in
the Appeal Brief. See 37 C.F.R. § 41.67(c)(1)(vii).

Claim Interpretation
In this proceeding, the claim language should be read in light of the
specification as it would be interpreted by one of ordinary skill in the art. In
re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). The
Office must apply the broadest reasonable meaning to the claim language,
taking into account any definitions presented in the specification. Id. (citing
In re Bass, 314 F.3d 575, 577 (Fed. Cir. 2002)). There is a “heavy
presumption” that a claim term carries its ordinary and customary meaning.
CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002).
The “ordinary and customary meaning” is that which the term would have to
a person of ordinary skill in the art in question. In re Translogic Tech., Inc.,
504 F.3d 1249, 1257 (Fed. Cir. 2007).

Claim 1 -- Programmable Logic Circuit
Patent Owner contends that the “programmable logic circuit” that is
claimed requires that it be reconfigurable in situ. Patent Owner explains that
it considers the phrase “reconfigurable in situ” to mean that the logic circuit
is configurable in place, which precludes removing the logic circuit from the
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larger system (such as a PC motherboard), configuring the logic circuit, and
returning the logic circuit to the system. App. Br. 10-16.
We find, however, as did the Examiner, that Requester’s declarations
are better supported by the evidence and thus more credible. Patent Owner
does not allege that the language of claim 1 is specific to in situ
reconfiguring, or somehow precludes removing the logic circuit for
reconfiguration. Rather, Patent Owner contends that the specification of the
'646 patent and extrinsic evidence require that the broadest reasonable
interpretation of “programmable logic circuit” places such a limitation on
the scope of the claim.
Requester’s declarant, Dr. Mercer, testifies that “programmable logic
circuit” was not a term of art at the filing of the '646 patent application, nor
has it since become a term of art. Mercer Decl. I ¶ 12. In Dr. Mercer’s
opinion, one of ordinary skill in the art would interpret the meaning
consistent with the three words constituting the term, not limited to any
particular way of reconfiguring or reprogramming the circuit.
1
Id.
Dr. Mercer continues that that term “programmable logic circuit” does not
appear to be used in the '646 patent except for the claims themselves. Id. at
13. Further, the '646 patent does not provide details as to how the logic
circuits may be reconfigured (id. at ¶¶ 14-16) and does not contain the term
“in-situ” (Mercer Decl. II ¶ 13).
Although an inventor is free to define the specific terms used to
describe the invention, “this must be done with reasonable clarity,

1
Patent Owner acknowledges that “reconfiguration” and
“reprogrammability” are equivalent. Hearing Tr. 5, ll. 18-20.
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deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
1994).
To act as its own lexicographer, a patentee must “clearly
set forth a definition of the disputed claim term” other than its
plain and ordinary meaning. It is not enough for a patentee to
simply disclose a single embodiment or use a word in the same
manner in all embodiments, the patentee must “clearly express
an intent” to redefine the term.

Thorner v. Sony Computer Ent. Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir.
2012) (citations omitted).
The '646 patent contains vague references to a “programmer” that can
“dynamically change the functionality” of the programmable logic device,
such that a “virtual hardware device” is achieved. The patent, however, only
mentions in passing a programming input for Programmable Interconnect
Matrix (PIM) 18 (Fig. 1). '646 patent col. 2, ll. 53-55. The programming
input at multi-bit bus 26 (Fig. 1) is not further discussed in the patent.
Moreover, the patent expressly teaches that the preferred embodiment, even
assuming it is programmable in situ, is not the only embodiment. See id. at
col. 3, ll. 11-15; col. 4, ll. 41-44, 50-55.
In view of the evidence presented on this record, we interpret
“programmable logic circuit” in accordance with the ordinary and customary
meaning of the terms. A “programmable logic circuit” is, simply, a logic
circuit that can be programmed. Claim 1 recites “a programmable logic
circuit configured to (i) generate one or more control signals and (ii) receive
one or more clock signals.” The words “one or more” serve to broaden the
claim scope. The claim recitation directed to the programmable logic circuit
requires, at a minimum, a logic circuit that can be programmed, the logic
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circuit being configured to generate a control signal and receive a clock
signal.
Patent Owner argues, in response to the rejection of claim 1 as being
anticipated by Wright, that Wright fails to disclose a programmable logic
circuit because none of the reference’s circuits are in-situ reconfigurable.
App. Br. 17-18; Rebuttal Br. 8. Wright describes a programmable logic
circuit 10 (Fig. 1) that is coupled to phase lock loop 20. Wright col. 3,
ll. 13-20. Patent Owner acknowledges, however, that programmable logic
circuit 10 is, consistent with its terms, capable of being programmed. See,
e.g., Stine Decl. I ¶ 30 (“The programmable logic circuit 10 of Wright
consists of a programmable AND array 22, eight output blocks 24, eight
input blocks 40, four OR gates 50, OR gate 52, and OR gate 54. (Wright,
3:16-24, 3:42-43, & 3:57-4:3.)” (emphasis added). The programmable logic
circuit can include a fuse-programmable or electrically erasable
programmable array. Id. at ¶ 31.
Because we are not persuaded that the broadest reasonable
interpretation of “programmable logic circuit” requires in-situ
reconfigurability, we are, accordingly, not persuaded of error in the
Examiner’s finding that Wright anticipates claim 1. We sustain the
Examiner’s § 102(b) rejection of claim 1 over Wright.

Claim 12 -- Dynamically Changing a Frequency of Operation of a
Programmable Logic Circuit
We have construed “programmable logic circuit,” in accordance with
its broadest reasonable interpretation, in our consideration of claim 1.
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Claim 12 recites “configuring said programmable logic circuit to generate
one or more control signals and receive one or more clock signals.”
Claim 12 further recites, in its preamble, that the method is for “dynamically
changing a frequency of operation of a programmable logic circuit.” For
purposes of this appeal we will presume that the preamble language limits
the subject matter of claim 12, because it appears that the Examiner and both
parties treat the preamble recitation as a limitation.
With regard to the preamble recitation, Dr. Mercer testifies:
Patent Owner fails to show that this dynamically changing the
frequency of operation requires any modification of the
programmable elements of the programmable logic circuit. For
example, Figure 1 of the ’646 patent shows that dynamically
changing the frequency of the CLOCK INPUT TO PLL
(element 22) will definitely dynamically change the “frequency
of operation of a programmable logic circuit.” In a similar
manner, observation of Figure 7 of the '646 patent shows that
changing the logic value of either the select input 80 to the
multiplexer 72 or values input at 94 can dynamically change the
frequency of operation. Thus, the claim phrase in no way
requires any modification to the programmable components of
the programmable logic circuit to accomplish the required
functionality.

Mercer Decl. II ¶ 10.
Consistent with this testimony, the '646 patent describes: “Since the
frequencies present at the outputs 86, 88, 90 and 92 [Fig. 7] are controlled in
part by the control signal received at the input 94, the frequencies may be
programmed after fabrication of the clock distribution scheme 70.”
'646 patent col. 4, ll. 28-32 (emphasis added). The frequencies are also
controlled in part by the frequency of the selected input clock. Id. at col. 3,
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l. 66 – col. 4, l. 16; Fig. 7, inputs 76, 78. The '646 patent’s linking of the
“programmed” frequencies with the configuration signal at 94 (Fig. 7)
demonstrates that the frequency of operation of the programmable logic
device can be dynamically changed in part by the control signal received at
input 94. The configuration controls at Figure 2 and Figure 7 of the patent
do not represent, for example, a signal for reprogramming the logic elements
of the device. According to Patent Owner, the configuration signals are
merely outputs of the logic blocks (e.g., Fig. 1) of the programmable logic
device, as discussed at the oral hearing:
JUDGE BLANKENSHIP: But you said there’s no
reprogramming in Element 12 ['646 patent Fig. 1].

MS. GORDON: Correct. The phase lock loop is not
reprogrammed, so the phase lock loop is a loop structure that
receives a reference, clock signal, and it has an oscillator and it
feeds back the clock signals it generates. And what it does is it
uses the control signals to change the oscillator in a way to
generate different frequencies. So I guess, in a sense, you could
argue that the control signals are changing -- are programming,
in a sense, the frequency of operation that the phase lock loop
is. But in the context of the 646 patent, the programming that’s
generating the control signals [is] the programming inputs into
the programmable input matrix we see here in Figure 1, the
programmable logic circuit.

. . . .

JUDGE BLANKENSHIP: Where’s the control signal?

MS. GORDON: So the control signals are the signals
coming out of the logic blocks. So those are the signals that
you see being output from the logic blocks. And those control
signals are what is inputted into the system of Figure 2, which
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is the clock distribution scheme of the phase lock loop. And the
phase lock loop sends those clock signals to the clock
distribution network on the programmable logic device, which
we see coming in in Figure 1 through line 24.

Hearing Tr. 9, ll. 13-24; 27, ll. 4-11.
Thus, “dynamically changing a frequency of operation” of a
programmable logic circuit, as recited in the preamble of claim 12, does not
require “dynamically” changing the programming of (reprogramming) the
programmable logic circuit itself. Although programming the device to
generate the control signals may require programming of the device itself,
the configuration controls in the '646 patent do not represent signals for the
programming of the device.
Patent Owner refers to evidence submitted to show that “dynamically”
changing the operation of a programmable device means that the
configuration of the device is effected on-the-fly or at run-time. App.
Br. 14-15; Rebuttal Br. 7. Claim 12, however, recites “configuring” the
programmable logic circuit to generate one or more control signals and
receive one or more clock signals, similar to the language of claim 1.
Claim 12 does not recite, nor does it otherwise require, “dynamically
configuring” the programmable logic circuit.
We note, further, that Dr. Mercer’s testimony that Patent Owner has
not shown that dynamically changing the frequency of operation requires
any modification of the programmable elements of the programmable logic
circuit is consistent with the '646 patent’s description as to how to effect its
independent clock configuration, by its incorporation of U.S. Patent
Application 08/549,915. '646 patent col. 3, ll. 5-15. The incorporated
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application, now U.S. Patent 5,684,434, describes the use of EPROMs to
store frequency and configuration information, such that the frequencies of
the clock outputs can be dynamically changed. '434 patent Fig. 1, elements
86, 18; col. 3, l. 64 – col. 4, l. 41. “Frequency selection during normal
operation is provided by external frequency select signals 88 and 90
[Fig. 1].” Id. at col. 4, ll. 28-30.
As with Patent Owner’s arguments in relation to claim 1, the
arguments in support of claim 12 are based on an unfounded claim
interpretation that is alleged to distinguish over Wright. In view of the
foregoing, we are not persuaded that the Examiner erred in finding claim 12
to be anticipated by Wright. We sustain the § 102(b) rejection of the claim.

Claim 18 -- Means for Implementing Programmable Logic for
Manipulating Information to Generate One or More Control Signals
Patent Owner submits that the “means for implementing
programmable logic” language in claim 18 requires interpretation in
accordance with 35 U.S.C. § 112, sixth paragraph. Patent Owner argues that
the structure corresponding to the “means” is the PIM and logic sections 14
and 16, as depicted in Figure 1 of the '646 patent. Because Wright’s circuits
do not include a PIM, Patent Owner argues that claim 18 distinguishes over
the reference. App. Br. 18-20.
However, as we have noted, the preferred embodiment described by
the '646 patent is not the only described embodiment. Requester points to
disclosure of different devices, and further points out that claim 10 of the
patent includes field programmable gate arrays as a species of the
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programmable logic circuit or device. Resp. Br. 14; '646 patent col. 3, ll. 11-
15; col. 4, ll. 41-44, 50-55.
Patent Owner notes Requester’s position concerning alternative
structures (Rebuttal Br. 9), but does not provide any satisfactory response.
Moreover, we note that Patent Owner’s argument in support of claim 18 is
inconsistent with proposed new claim 23, which ultimately depends from
patent claim 1 but further limits the programmable logic circuit as
comprising a PIM. We are not persuaded of error in the § 102(b) rejection
of claim 18 and thus sustain the rejection.

Claim 19
Claim 19, as proposed to be amended, further limits base claim 18 in
that two or more clock signal are individually programmable to oscillate at
one of the plurality of frequencies. The claim stands rejected for
obviousness over the combination of Wright and Graham. Graham is relied
upon as teaching individual programmability of clock outputs.
Patent Owner’s declarants aver that Wright’s system already includes
an AND array 150 in the programmable logic circuit. For providing more
flexibility and greater choice in clock outputs, “common sense” would
dictate that the solution would be to suitably program Wright’s AND array
250 to provide such functionality, not to replace Wright’s 4-bit counter 216.
See, e.g., Koperda Decl. ¶ 17. The AND array of Graham would be
“superfluous” to the AND array of Wright. Id.
Requester’s declarant avers that a purpose of element 216 of Wright is
to provide feedback to the PLL; therefore, element 216 logically resides
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within the PLL portion 200 and not within the programmable logic portion
202. Mercer Decl. II ¶ 22. As such, it would be error to reconfigure
Wright’s AND array 250. Id. Dr. Mercer submits that combining the
teachings of Graham to generalize the functionality of Wright’s block 216
for individually programmable frequencies would have been well within the
abilities of the ordinarily skilled artisan and would achieve anticipated
results. Id.
We credit Dr. Mercer’s testimony over that that relied upon by Patent
Owner. Wright’s AND array 250 is part of programmable logic circuit 202.
Wright Fig. 3; col. 8, ll. 14-27. AND array 250 is configured to receive
signals from PLL 200. However, the 4-bit counter 216 provides clock
signals to the programmable logic section. Wright, e.g., col. 7, l. 52 – col. 8,
l. 13; col. 9, ll. 13-33. Moreover, Patent Owner’s declarants do not indicate
why, even if Wright’s AND array 250 were programmed to provide the
additional functionality as taught by Graham, the AND array of Graham
would be “superfluous” to the AND array of Wright.
Patent Owner further submits that “[a]dding control of counter 216 by
adding another AND array is a new ground of rejection on appeal,” which is
improper in a Respondent Brief. Rebuttal Br. 11-12. Patent Owner asserts
that this “new ground of rejection” is set forth at page 15, paragraph (c) of
the Respondent Brief. Id. However, Requester, at the indicated section,
merely responds, persuasively, why Patent Owner’s reliance on In re NTP,
Inc., 654 F.3d 1279 (Fed. Cir. 2011) is misplaced -- because no
“superfluous” functionality is proposed. Control of counter 216 by “adding
another AND array” is an issue raised by Patent Owner, not a new ground of
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rejection on appeal. Similarly, Patent Owner’s allegation (Rebuttal Br. 12)
that the Respondent Brief, page 15, paragraph (b) represents another “new
ground of rejection” is not persuasive because it is Patent Owner, not
Requester, that proposes modifying AND array 250 in Wright.
We are not persuaded of error in the § 103(a) rejection of claim 19
and thus sustain the rejection.

Claim 20
Claim 20 depends from claim 19 and further recites, as proposed to be
amended, that the two or more clock signals each have an impedance that is
adjusted to match an impedance of an external device. Requester proposes a
rejection, adopted by the Examiner, whereby McBride is added to the
combination of Wright and Graham.
McBride teaches that, for proper operation of a system using
integrated circuits on a printed circuit board, it is important for all loads on
the board to receive the clock signal at essentially the same time. McBride
col. 1, ll. 13-16. The reference further teaches that, to prevent reflections
from occurring along a transmission line, a resistive termination is required
at the sense end of the transmission line. Id. at col. 3, ll. 13-17.
Claim 20, however, recites an impedance adjusted to match an
impedance of “an external device.” Neither Requester nor the Examiner
contends that a transmission line is an external device. As Patent Owner
points out, McBride teaches that the load (i.e., an external device) has a high
impedance in comparison to the transmission line to which the output
impedance is matched. McBride col. 5, ll. 3-14. Requester attempts to fill
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this gap in the prior art with the testimony of Dr. Mercer, who opines that
one of ordinary skill in the art would know how to apply the teachings of
McBride with respect to impedance matching “at all necessary interfaces
where distributed parameter effects would be of significance.” Mercer
Decl. II ¶ 24. The fact remains, however, that McBride teaches that the
impedance of a transmission line is of significance for impedance matching,
as opposed to the impedance of an external device.
The Examiner and Requester have not provided sufficient factual
foundation for the § 103(a) rejection of claim 20 over Wright, Graham, and
McBride. We cannot sustain the rejection.

Claim 24
Proposed new claim 24 depends from new claim 21, which in turn
depends from patent claim 1. Claim 24 recites that the programmable logic
circuit is configured to route a first clock signal to a first logic block in the
plurality of logic blocks and to route a second clock signal to a second logic
block in the plurality of logic blocks. The claim is rejected for obviousness
over Wright and Intel. Intel is relied upon as teaching a system that provides
a selection of six clocks at each Configurable Function Block (CFB) of a
field programmable gate array (FPGA), thereby to demonstrate that a first
clock is routed to a first CFB and a second clock is routed to a second CFB.
Intel 381-82; Resp. Br. 17.
Patent Owner submits that Intel’s description of clocks being routed to
different CFBs does not support the speculation that Intel’s architecture
routes multiple clocks to multiple different CFBs. App. Br. 31. Patent
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Owner points out that Figure 2 of Intel (at 380) shows CFBs receiving clock
signals from an element other than the Global Interconnect Matrix. Id.
Requester notes that the entirety of Intel’s FPGA is analogous to the
claimed programmable logic circuit. Resp. Br. 17. As such, according to
Requester, regardless of whether Intel’s Global Interconnect Matrix, within
the FPGA, performs the routing or not, “clock signals CLK1, CLK2 are
certainly routed within Intel’s FPGA.” Id.
The claim at issue, however, recites that the programmable logic
circuit is “configured to route” a first clock signal to a first logic block and a
second logic signal to a second logic block. The Examiner and Requester
have not shown that any part of the programmable logic circuit – or the
FPGA, in Requester’s understanding of the rejection – is configured to route
a clock signal to one logic block (CFB) and a second clock signal to another
logic block (CFB). Requester does not point to any testimony or Examiner
finding that explains how the programmable logic circuit in Intel may be
configured consistent with the requirements of claim 24. Nor does the
rejection make up for the deficiency in Intel’s teachings. Accordingly, we
do not sustain the § 103(a) rejection of claim 24 over Wright and Intel.

Summary/Conclusion
We have considered the claims for which the Appeal Brief provides
arguments for separate patentability. See 37 C.F.R. § 41.67(c)(1)(vii). We
are not persuaded of error in the Examiner’s § 102(b) rejection applied
against claims 1-4, 6, 10-13, 16-18, 21, 31, and 33. We are not persuaded of
error in the Examiner’s § 103(a) rejections applied against claims 5, 7-9, 14,
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15, 19, 22, 23, 25-30, 32, and 34-42. Patent Owner has demonstrated error
in the § 103(a) rejections of claims 20 and 24. Accordingly, we sustain the
rejection of claims 1-19, 21-23, and 25-42. We do not sustain the rejection
of claims 20 and 24.

DECISION
The Examiner’s decision unfavorable to the patentability of claims 1-
42 is affirmed with respect to claims 1-19, 21-23, and 25-42 but reversed
with respect to claims 20 and 24.
Requests for extensions of time in this proceeding are governed by
37 C.F.R. §§ 1.956 and 41.79(e).
This is a final decision. Parties to the proceeding seeking judicial
review of the decision must comply with the notice and service requirements
of 37 C.F.R. § 90.2. For judicial review of decisions arising out of
proceedings referenced in 37 C.F.R. § 90.1, the notice and service
requirements are governed by the pertinent regulations in effect on
July 1, 2012.

AFFIRMED-IN-PART

Appeal 2013-008748
Reexamination Control 95/001,550
Patent US 6,272,646 B1

21
Patent Owner:

Sterne Kessler Goldstein & Fox, PLLC
1100 New York Ave. NW
Washington, DC 20005

Third Party Requester:

David L. McCombs
Haynes and Boone, LLP
IP Section
2323 Victory Avenue
Suite 700
Dallas, TX 75219