Ex Parte 6260097 et al

Board of Patent Appeals and Interferences

Jun 8, 2012

95001134 (B.P.A.I. Jun. 8, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,134 01/09/2009 6260097 42940.4 8506
86497 7590 06/11/2012
Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
06/11/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

RAMBUS, INC.
Patent Owner, Appellant

v.

NVIDIA CORPORATION
Requestor, Respondent
____________

Appeal 2012-000171
Inter Partes Reexamination Control No. 95/001,134
United States Patent 6,260,097 B1
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2012-000171
Reexamination Control 95/001,134
Patent 6,260,097

This proceeding arose out of a request by NVIDIA for an inter partes
reexamination of U.S. patent 6,260,097 B1 to Farmwald et al., Method and
Apparatus for Controlling A Synchronous Memory Device (issued
July 10, 2001, claiming priority to April 18, 1990) assigned to Rambus.
Appellant and Patent Owner Rambus appeals from the Examiner’s
decision in the Right of Appeal Notice (RAN) rejecting claims 1-5, 7, 8, 10-
12, 14, 26, 28-32, 34 and 35. (Rambus App. Br. viii.) The Examiner’s
Answer relies on the RAN, incorporating it by reference.
We have jurisdiction under 35 U.S.C. §§ 134(b) and 315.
We AFFIRM the Examiner’s decision rejecting claims 1-5, 7, 8, 10-
12, 14, 26, 28-32, 34 and 35.

STATEMENT OF THE CASE
Rambus and NVIDIA refer to several related judicial and other
proceedings including inter partes and ex parte reexaminations,
International Trade Commission proceedings, and Federal District Court and
Circuit Court proceedings in their briefs. An oral hearing of this appeal
transpired on April 4, 2012 and was subsequently transcribed.
Introduction
Requestor and Respondent NVIDIA filed an appeal brief, respondent
brief, and a rebuttal brief in this appeal, and supporting papers prior to that,
but subsequently withdrew from the appeal pursuant to a settlement with
Rambus. (See Notice of Withdrawal of Third-Party Requester’s Appeal and
Other Papers (Feb. 17, 2012).) In the Notice, NVIDIA seeks to withdraw its
briefs and supporting papers but fails to point the Board to authority for
allowing such brief and paper withdrawal. (See id.)
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The Examiner relied on NVIDIA’s supporting papers, including
NVIDIA’s Request for Inter Partes Reexamination, to arrive at the decision
in the RAN to maintain NVIDIA’s proposed rejections. The Answer, which
incorporates the RAN by reference, implies that the Examiner agrees with
positions outlined in NVIDIA’s Respondent Brief. (See MPEP 2677 (“The
examiner should reevaluate his/her position in light of the arguments
presented in the briefs, and should expressly withdraw any rejection or
determination of patentability not adhered to.”); MPEP 2677 (L) (The
Answer must contain “[a] statement of whether the examiner disagrees with
each of the contentions of appellants and respondents in their briefs.”).)
Rambus’s appeal is essentially an appeal of the Examiner’s decision
to reject the claims. Withdrawing the supporting papers would undermine
the Examiner’s decision to maintain NVIDIA’s proposed rejections. Even
though the Board may have some discretion to ignore NVIDIA’s papers and
briefs, the Board also has the discretion not to ignore them. See 37 C.F.R.
§ 41.77(a) (the Board may consider “all issues raised on each appealed
claim”).
As such, NVIDIA’s request to withdraw its Respondent Brief and
supporting papers is denied, but the request to withdraw its Appeal Brief,
which contests the Examiner’s decision to confirm claims, is granted – since
the Examiner’s RAN and Answer generally agree with the thrust of the
Respondent Brief but not the Appeal Brief.

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RAMBUS’s APPEAL
Claims 1 and 2 on appeal by Rambus follow:
1. A method of controlling a synchronous memory device,
wherein the memory device includes a plurality of memory cells, the
method of controlling the memory device comprises:
issuing a write request to the memory device, wherein in
response to the write request, the memory device samples first and
second portions of data;
providing a first portion of data to the memory device
synchronously with respect to a rising edge transition of an external
clock signal; and
providing a second portion of data to the memory device
synchronously with respect to a falling edge transition of the external
clock signal.

2. The method of claim 1 wherein the write request includes
an operation code.

The Examiner’s rejections follow:
Claims 1, 2, 7, 8, 10, and 14 as anticipated based on Inagaki.
1

Claims 1-5, 7, 8, 10-12, 14, 26, 28-32, 34, and 35 as obvious based on
the iAPX Manual
2
or Budde,
3
and Inagaki.

1
Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record) (attached as Exhibit 2 to NVIDIA’s
Respondent Brief).
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Claims 1-5, 7, 8, 10-12, 14, 26, 28-32, 34, and 35 as obvious based on
the iAPX Manual, the iAPX Specification
4
and Inagaki.

I. Inagaki -Anticipation
The issues here turn on claim construction and whether Inagaki
discloses a clock, a synchronous memory device, and a write request as set
forth in claim 1, and a write request which includes an op code, as set forth
in claim 2.
Factual Findings
I1. Inagaki describes increasing data transfer rates in block access
memory devices: “the demand is increasing to have higher speeds even for
MOS RAM.” (Inagaki 2.) As further background, Inagaki explains that
conventional methods to increase data transfer rates in RAMs [random
access memories] included increasing the data bus width, which adds to the
cost of packaging (by increasing the pin count), or increasing the clock rate.
(Id.) Inagaki’s solution doubles the data rate and involves using the rising
and falling edges of an external clock (i.e., without increasing the clock
rate): “The rise and fall of external clock φ are detected, and clocks φ1
and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift

2
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
(attached as Exhibit 3 to NVIDIA’s Respondent Brief).
3
Budde et al., U.S. 4,480,307 (Oct. 30, 1984).
4
Electrical Specifications for iAPX 43204 Bus-Interface Unit (BIU) and
iAPX 43205 Memory Control Unit (MCU) (March 1983) (attached as
Exhibit 7 to NVIDIA’s Respondent Brief).
.
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register. . . . In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed.” (Id. at 4.)
I2. Inagaki’s system performs “data input or output every half-cycle
based on an external clock.” (Id. at 2.)
I3. Inagaki explains that a conventional “I/O shift register drive[s]
clocks . . . synchronized by an external clock” based on outputting one bit
per each cycle of that clock thereby limiting speed based on that clock.
Inagaki improves upon this conventional method in terms of speed as
follows: “In order to overcome this problem, the present invention presents
block access memory that transfers data with a speed that is twice the
conventional speed, by performing I/O [input/output] of data on every half-
cycle of the external clock that drives the I/O shift register.” (Id. at 3.)
I4. Inagaki discloses a block memory device which includes “a shift
register . . . that reads an external signal to perform parallel reading of data
into said memory cells.” (Id. at 3; accord id. at 1, claim 1).
I5. In Inagaki’s block access memory device, an internal timing
generator controls memory cells, a read circuit, row and column decoders, a
data input buffer, the shift register, and data output buffer. The “I/O shift
register, data input buffer, and data output buffer . . . [are] driven offset by a
half-cycle from each other.” (Id. at 3; accord id. at 2, claim 3)
I6. Inagaki describes clocked control of the input and output buffers
50 and 60 and shift registers in Figures 3, 5, and 7. Figures 3, 5, and 7
represent improvements over the conventional circuit of Figure 1 and
operate at twice the conventional speed. (Id. at 4-6.)
I7. Inagaki’s Figure 3 embodiment employs a shift register as a
timing switch 70 to control the input and output (I/O) of data through the
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input and output buffers, but the data does not go through the shift register.
(Id. at 3-4.) In the Figure 3 embodiment, “since one bit is output on each
half-cycle, the operating speed is twice that of the conventional speed.” (Id.
at 4.)
Analysis
Rambus focuses on claim 1 and argues that Inagaki does not disclose
a “synchronous memory device,” a “write request,” or providing data to a
memory synchronously with respect to an external clock signal. (Rambus
App. Br. 2.) Rambus reasons that Inagaki’s clock “is simply a pulsed
signal” and therefore “does not provide a periodic signal that serves as a
timing reference, which is required by a synchronous memory device as that
term is understood by one of skill in the art.” (App. Br. 4 (citing Murphy
Decl. ¶¶ 116-120; Murphy Supp. Decl. ¶¶ 9-18).)
To the contrary, Inagaki describes an “external clock” and bits that are
input (written) based on internal clocks synchronized to the rising and falling
edges of that external clock. (I1-I3.) According to the Examiner, Inagaki’s
clock is periodic “at least . . . during data input.” (RAN 45.) Rambus does
not dispute this underlying finding, but contends that a clock cannot be
periodic if it is pulsed on and off as opposed to running continually. (See
App. Br. 4-6.) Rambus’s arguments lack merit. The Examiner’s
interpretation comports with the industry meaning of “clock” as understood
by skilled artisans.
5

5
“clock . . . A source of accurately timed pulses, used for synchronization in
a digital computer . . . .” McGraw-Hill Dictionary of Scientific and
Technical Terms 387 (Fifth Ed. 1994). This reference indicates that clock
signals and clock pulses are the same: i.e., “clock signals. See Clock
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As the industry specific meaning shows, Rambus’s purported
distinction that Inagaki’s clock is “toggled or ‘pulsed’” and is not “periodic”
(App. Br. 4) contradicts the fact that computer clocks typically use pulses to
time digital events. (See note 5.) The ‘097 patent does not disclose a
computer clock that runs forever or that cannot be turned off. The claimed
method only implies that the clock runs during data inputs to synchronize
data transfers and Inagaki’s clock “at least shows a limited periodic
duration” as the Examiner finds. (See RAN 45.)
Further, according to Rambus, “Inagaki . . . uses the word ‘clock’ in
numerous locations.” (Murphy Supp. Decl. ¶ 15.) Such repeated generic
references to a “clock” and claims reciting an “external clock” (I4) show that
Inagaki’s clock is not limited to any specific embodiment. Rather, Inagaki’s
“numerous” computer “‘clock’” (id.) references point skilled artisans to and
embrace the well-known computer clock (note 5) – in other words, the same
type of external computer clock generically claimed in the ‘097 patent. See
In re Paulson, 30 F.3d 1475, 1480-81 (Fed. Cir. 1994) (“a prior art reference
must be ‘considered together with the knowledge of one of ordinary skill in
the pertinent art’,” and where the skill level was “‘quite advanced’ . . . ‘one
of ordinary skill certainly was capable of providing the circuitry necessary to
make the device operable for use as a computer’”) (citations omitted).
Rambus also alleges that the Examiner “did not identify a signal that
distinguishes between a read and a write, much less a series of bits that
would constitute a ‘write request’.” (Rambus App. Br. 7.) But Rambus fails

pulses.” Id. “[C]lock pulses. . . . Electronic pulses which are emitted
periodically, usually by a crystal device, to synchronize the operation of
circuits in a computer. Also known as clock signals.” Id.
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to address the Examiner’s finding (RAN 46) that Inagaki discloses
“read[ing] an external signal to perform parallel reading of data into said
memory cells.” (I4 (emphasis added).) Mr. Murphy, Rambus’s expert, also
does not address this finding and focuses, like Rambus, on Inagaki’s
allegedly asynchronous “/CE signal” in Figure 2. Mr. Murphy similarly
states that Inagaki “does not … disclose any signal or group of signals used
to distinguish between a read and a write.” (Murphy Supp. Decl. ¶ 20.)
To the contrary, Inagaki’s RAM memory device necessarily must
distinguish between a read and a write; otherwise, it could not function as
the well-known “RAM” and perform input and output (I/O) of data (See I1-
I7.) The Examiner relies on Inagaki’s amended claim 1 which recites that
the block memory “reads an external signal to perform parallel writing of
data into said memory cells.” (RAN 46.) The Examiner also relies on
Inagaki’s description of Figure 5 which describes that “‘data that is to be
input or output to the I/O buses is read or written.” (RAN 46.) Inagaki’s
“‘external signal’” (I4) identified by the Examiner reasonably corresponds to
the recited “write request.” Inagaki’s RAM responds to the external signal
by writing data to the RAM. (I1, I4.)
Rambus’s focus on the allegedly asynchronous /CE signal and other
related arguments also erroneously imply that the claimed write request in
claim 1 must be synchronous with the external clock. To the contrary,
claim 1 requires providing “the portion[s] of data to the memory device
synchronously with respect to . . . and external clock” (emphasis added),
thereby showing that “issuing the write request” is not necessarily
synchronously provided with respect to the clock or anything else.
(Compare claim 26 (requiring a synchronous write request – “wherein the
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memory device samples the write request synchronously”) with claim 1 (no
such requirement – “issuing a write request”).)
Rambus also argues as follows:
Rambus [previously] argued that Inagaki does not disclose write operations
that utilize the shift register and that any data that is input in to the memory
device would be shifted into the shift register before any signal transitions
that signify a write operation are received and that therefore data could not
be sampled by the memory device in response to anything that could be
alleged to be a write request.
(Rambus App. Br. 7 (citation to earlier Rambus response omitted).)
In other words, Rambus argues that “shifting of data into the shift
registers does not constitute a write” because Inagaki’s system makes the
decision to write after putting data into the shift register. (See id.) Rambus
bases this contention on an isolated sentence in Inagaki: As Rambus notes,
Inagaki states “that ‘data that is to be input or output to the I/O buses is read
or written after being temporarily stored in the shift register’” (App. Br. 7
(quoting Inagaki at 4, emphasis by Rambus).)
Contrary to Rambus’s point, that Inagaki sentence does not imply
anything about the timing of a write (or read) request. That sentence only
points out that the shift register in Figure 5 temporarily holds data before it
is written or read. (Accord Resp. Br. 3.) In Figure 5, data passes over an
I/O bus, and as an input, through the RAM input buffer, through the RAM
shift register, and then to the RAM memory array. (See Inagaki 4. Figs. 1, 5
(describing similarities and differences between the Figure 3 and the
conventional Figure 1 embodiments).)
Rambus’s conjectural assertion amounts to arguing that Inagaki’s
system sends data over the bus to the RAM’s shift register before the system
decides to send it to the RAM’s input buffer for writing it to the RAM’s
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memory array. There is no support for such an inefficient system, but even
if there is, another Inagaki embodiment (see Figure 3) does not employ a
shift register in the data path; i.e., neither the relied-upon Inagaki sentence
nor the argument applies to the Figure 3 embodiment. (See I7; accord
NVIDIA Resp. Br. 3.) Rambus’s conjectural contention misinterprets an
isolated sentence and does not square with a normal reading of any of
Inagaki’s embodiments. (See Figures 1, 3, 5, 7, and 9).
In addition to Inagaki’s external signal described supra, the Examiner
also finds another “write request” satisfying claim 1, including Inagaki’s
“‘address signal . . . [which is supplied to] a data input buffer that latches
these signals and supplies data to the memory cells’.” (RAN 47 (quoting
Inagaki at 3).) In response to these external write request signals, Inagaki’s
input buffer and/or shift register sample synchronous data which is provided
on rising and falling clock edges as claim 1 requires - and the system thereby
doubles the data speed relative to conventional systems. (See I2, I2, I6, I7.)
Rambus fails to explain persuasively why Inagaki fails to satisfy the
disputed “write request” claim element.
Rambus argues that the write request must include “a series of bits”
based on Infineon
6
which interpreted a related Rambus claim, and based on a
disclosed embodiment in the ‘097 patent. (Rambus App. Br. 6.) But this
argument fails to square with Mr. Murphy’s declaration and claims 1 and 2
in a sufficient manner to show a patentable distinction over Inagaki.
Mr. Murphy declares that “[w]rite requests and operation codes are made up
of bits or the state of a signal at a particular time.” (Murphy Supp. Decl. ¶

6
Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081 (Fed. Cir. 2003).
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20 (emphasis added).) Mr. Murphy’s testimony shows that write requests
and operations codes can correspond to “the state of a signal” and not
necessarily “a series of bits.”
Moreover, claim 1 does not define a “write request” as a “series of
bits.” Rambus seeks to incorporate that implied limitation from the
‘097 patent specification. But the disclosed series of bits are carried by a
request packet (‘097 patent, col. 9, ll. 23-64; Fig. 4) and Mr. Murphy
testifies that the claims do not require any packet or an interface for such a
packet. (Murphy Decl. ¶¶ 31, 35). If the claims do not require the disclosed
packet which carries the bits, logically, the claims cannot require anything in
that packet such as bits. Besides the “signal” explicitly mentioned by
Mr. Murphy as discussed supra, he also indicates in other testimony that the
disclosed invention generally encompasses signals on a generic bus – i.e.,
not necessarily a multiplexed bus carrying packets. (See Murphy Decl.
¶¶ 31-35.)
Further, Mr. Murphy testifies that the op code, as recited in claim 2
and which depends from claim 1 and qualifies the write request in claim 1,
only requires “one or more bits to specify a type of action” (Murphy Decl.
¶ 122), even though, according to other Murphy testimony, a write request
requires “‘a series of bits to request a write of data to a memory device’” (id.
at ¶ 121 (emphasis added)). Rambus similarly describes the operation code
as requiring “one or more bits specifying an action.” (Rambus App. Br. 8
(emphasis added, citations and quotation marks omitted).)
Thus, according to Rambus’s argument and Mr. Murphy, the
operation code recited in dependent claim 2 and which narrows the write
request in independent claim 1, only requires one bit. In other words, even if
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claim 1 somehow requires a series of bits, the series can be a series of one
bit. This interpretation squares with the ‘097 patent (‘097 patent, col. 9, ll.
46-55 (write or read operation code can be either a 1 or a 0 to specify a read
or a write)) and Mr. Murphy’s alternative testimony noted supra that a signal
state satisfies the claimed operation code and the write request. For
example, a high or low signal (voltage) level signifies the two possible
choices: a write or a read operation code.
7
Inagaki’s memory device
processes digital signals including an operation code which signifies a write
action and reasonably constitutes a bit, even if a “bit” is somehow different
than a signal. Mr. Murphy’s conclusion that Inagaki’s transition-based
control signals are not “in the form of bits” (id. at ¶ 122) fails to explain
adequately why Inagaki’s signal is not the same as “the state of a signal at a
particular time” which Mr. Murphy testifies corresponds to the op code and
write request.
Based on the foregoing discussion, Rambus fails to show error in the
anticipation rejection based on Inagaki of claims 1 and 2, or of claims 7, 8,
10, and 14 which Rambus did not argue separately from claims 1 or 2.

7
This interpretation is not inconsistent with Infineon, 318 F.3d at 1093,
especially given Rambus’s proffer here of Mr. Murphy’s testimony that a
signal can satisfy the claims. In Infineon, the court determined, after
discussing read requests, that a write request means “a series of bits used to
request a write of data,” but the court did not decide if such a series could be
one bit or a signal. .
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II. iAPX Manual, iAPX Specification, and Inagaki - Obviousness
8

The iAPX Manual –Factual Findings
A1. Figure 1-2 of the iAPX Manual follows:

Figure 1-2 depicts a memory module comprising a memory storage
array and a MCU (Memory Control Unit).
“The storage arrays will typically be constructed with high-density
dynamic RAM (DRAM) components.” The MCU requires a “modest
amount of external logic . . . to interface the MCU to the storage array
RAMs - - for simple configurations, as few as 12 external TTL packages are
required.” (iAPX Manual 1-4.)
The BIU (bus interface unit) works in conjunction with a GDP
(general data processor) in a processor module. (iAPX 1-1 - 1-3; Fig. 1-2.)
“The BIU is also responsible for arbitrating the usage of the memory bus.”

8
According to Rambus, the iAPX Specification describes the same system
as the iAPX Manual. (App. Br. 26-27.) The two rejections which either
involve or do not involve the iAPX Specification (in addition to the iAPX
Manual and Inagaki) are treated as the same rejection here since Rambus
does not treat the rejections differently based on arguments presented. (See
id.)
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(iAPX 1-3.) It also “decides which memory bus(es) will be used to form the
[memory bus] access.” (Id.)
A2. The memory module constitutes “a memory confinement area.”
(iAPX Manual 1-8, 3-2.) The MCU “interfaces memory storage arrays to
the memory bus.” (iAPX Manual 1-4.)
A3. A component level constitutes the lowest level of hardware in the
system, an example of which is a RAM chip. A module comprises a group
of interconnected components. (iAPX Manual 2-1.) The presence or
absence of any module does not prevent communication between any other
modules. (iAPX Manual 2-6.)
Analysis
The Examiner finds that the iAPX BIU (bus interface unit) sends data
packets including a write request to the MCU (memory control unit). (See
RAN 53-55; A1 (showing the GDP and BIU to be part of a processor
module).) The Examiner finds the MCU to be a synchronous interface to
memory arrays; therefore, the MCU and arrays, constrained to a confined
area (A1, A2), constitute the memory device recited in claim 1. (See RAN
53-54.) The Examiner also finds data to be sent synchronously with respect
to rising clock edges. (Id.) The iAPX BIU, in a fashion similar to the
‘097 memory controller or master, aids in arbitrating access to the memory
bus and makes other memory bus access decisions. (Compare A1 with
‘097 patent col. 12, ll. 55-58.) The Examiner relies on Inagaki to suggest
modifying the iAPX system to include the providing of first and second data
portions on rising and falling edges. (RAN 55-57.)
Many of Rambus’s arguments with respect to the iAPX Manual raise
the same “single chip” issue as raised in at least three related appeals before
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the Board (App. No. 2011-008431, App. No. 2011-009664, App. No. 2010-
011178).
9
The patents involved in those appeals claim continuity back to the
same application (App. No. 07/510,898) as the ‘097 patent under
reexamination and appear to have the same or substantially the same
disclosures.
10
The relevant findings and reasoning from those related appeal
decisions address Rambus’s similar arguments including, inter alia,
prosecution history, District Court findings, expert opinion and other such
“memory device” interpretation arguments, and are adopted and
incorporated by reference here. Some of that previous rationale is repeated
and honed here for context.
Rambus’s arguments with respect to the iAPX manual reduce to the
unsupported argument that the claims, which recite a “memory device,”
require a single chip. (See Rambus App. Br. 8-20.) Rambus does not
present persuasive objective evidence establishing that the ordinary and
customary meaning of a “synchronous memory device” is a “chip.”
11
As
similarly found in our previous decisions, the term “memory device”
includes the disclosed memory device embodiment in Figure 9 of the
‘097 patent, “sometimes called a memory stick,” (‘097 patent, col. 19, ll. 63-

9
The latter decision is now on appeal to the Federal Circuit (Fed. Appeal
No. 2011-1247).
10
See Infineon 318 F.3d at 1084-86 (supra note 6) (finding that the written
descriptions of related Rambus patents are substantially identical to the
written description of another patent where all claim continuity back to the
07/510,898 application involved here.).
11
Cf. Infineon, 318 F.3d at 1091 (holding that the term “integrated circuit
device” as recited in claim 26 of Rambus’s related ‘804 patent takes its
ordinary meaning of “chip”) (internal quotation marks and citations to trade
dictionaries and other authority omitted).
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64 (emphasis supplied)), or a “primary bus unit,” (id. at l. 62): “In general,
each teaching of this invention which refers to a memory device can be
practiced using a transceiver device and one or more memory devices on an
attached memory bus unit.” (Id. at col. 20, ll. 7-10 (emphasis added).) In
other words, “this invention” includes what can sometimes be called a
memory stick, but in general, each reference to a memory device includes a
memory stick.
The term memory device is generic to both embodiments disclosed by
the ‘097 patent – the memory chip device and the memory stick device.
Skilled artisans would have understood that a memory stick and a chip are
each a specific species of the generic term “memory device.” (See RAN 27-
30.) Rambus argues that the memory stick “can be used in place of a
memory device” (Reb. Br. 6, n.4) but this replacement rationale only
bolsters the finding that the stick and chip each constitute a device. The
memory device can include a single chip or multiple chips.
12
The District
Court findings, addressed by Rambus (see Rambus App. Br. 19-20) and our
previous opinions, do not discuss this memory stick device.
Contrary to Rambus’s arguments (App. Br. 12), the ‘097 patent does
refer to the memory stick as a memory device. For example, the ‘097 patent
describes “memory devices on the transceiver bus as well as on the primary
bus units” (col. 20, ll. 6-7 (emphasis added)) and refers to preferably busing
a TrncvrRW signal to “a more sophisticated transceiver” on a memory stick

12
See also Mangosoft, Inc. v. Oracle Corp., 525 F.3d 1327, 1331 (Fed. Cir.
2008) (“‘the persistent memory device will be understood to include a
plurality of local persistent memory devices’”) (quoting U.S. Pat. No.
6,148,377).
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18
and generally busing that signal to “all devices on the transceiver bus” (id. at
ll. 32-36 (emphasis added)). Of course, a memory stick is a device on the
transceiver bus. A device includes a memory device which includes a
memory stick device. Moreover, in direct contradiction to the disclosure of
“memory devices [are] on the transceiver bus,” Rambus argued in the related
BPAI 2011-005266 appeal that only memory sticks are on the transceiver
bus.
13
Rambus’s argument in the ‘266 BPAI appeal necessarily means that
memory devices include memory sticks.
This reference to the memory stick as a type of device also contradicts
Rambus’s central argument that “[t]he specification uses the terms ‘device’
and ‘chip’ to mean the same thing” – i.e., in all cases. (See App. Br. 11.)
Since the ‘097 patent describes a memory stick as a device, a device is not
always a chip. Similarly, the ‘097 patent refers to “memory devices” and
then in the next sentence describes “[o]ther devices, generically referred to
as peripheral devices, including disk controllers, video controllers or I/O
devices” (col. 20. ll. 10-14 (emphasis added)), thereby implicitly
distinguishing these “[o]ther [peripheral] devices” from “memory devices.”

13
See BPAI 2011-005266 at 23, 18-24. In the ‘266 appeal, attempting to
overcome a prior art rejection based on U.S. 5,319,755 owned by Rambus,
Rambus argued that the TrncvrRW signal disclosed there is only applied to
the memory stick device, because, according to Rambus, the memory stick is
the only device on the transceiver bus. The Board held otherwise, noting
that the ‘755 patent specifically discloses “‘memory devices on the
transceiver bus’,” id. at 23 - i.e., just like the ‘097 patent discloses here.
The cited discussion and underlying facts in the ‘266 appeal is also adopted
and incorporated by reference here. The ‘755 patent and ‘097 patent claim
continuity to the same underlying application and have the same disclosure.
See supra note 10.
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19
Rambus argues that original claim 13 in the ‘898 application (supra
note 10), which recites “‘a plurality of semiconductor devices connected in
parallel to a bus, at least one of said semiconductor devices being a memory
device or a transceiver device’,” shows that “a ‘memory device’ is different
from a ‘transceiver device’.” (See App. Br. 12 (quoting original claim 13).)
Of course the two devices are “different,” but that proves nothing. The
original claim does not show that a memory stick, which includes a
transceiver device, is not a memory stick device.
14
If anything, original
claim 13 supports the Board’s prior holding (BPAI 2011-013706) that a
“semiconductor memory device” claimed by Rambus in that reexamination
proceeding corresponds to a single chip as Rambus argued there. Rambus’s
arguments here attempt to render the term “semiconductor” in the claim
phrase “semiconductor memory device” superfluous.
Similar to the related findings in the previous BPAI ‘1178 decision,
the disclosed memory device, “sometimes called a memory stick”
(‘097 patent, col. 19, ll. 63-64) can include masters, other controllers, and/or
transceivers thereon. (Id. at col. 20, ll. 1-16, Fig. 9.) These findings also
contradict Rambus’s related argument that a memory device precludes a
controller and other prior art memory board functions. (App. Br. 9-10, 13,
18-20.) In other words, since the disclosed ‘097 patent’s memory stick
device includes the controllers noted (i.e., transceiver, master, or other
controller), the claims do not preclude the memory control unit (MCU) on
the iAPX memory controller. (See A1-A3.)

14
The transceiver chip device 19 serves as a bus 65 interface on the memory
stick 66. (See ‘097 patent. Fig. 9.)
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20
Rambus’s arguments fail to demarcate a meaningful claimed
difference (implied or express) between the iAPX MCU and the controllers
and/or transceivers disclosed as part of the ‘097 patent’s memory stick
device (or control functions disclosed as part of the chip embodiment). The
MCU is similar to the interface on the ‘097 patent’s memory device (chip
and stick) and responds to write requests from the BIU which act
analogously to masters in the ‘097 patent system which also send the write
requests in packets. (See A1.) In other words, like the memory device
interfaces disclosed in the ‘097 patent (i.e., including the transceiver
interface between the memory stick memory arrays and bus, and the chip
interface), the MCU “interfaces memory storage arrays to the memory bus.”
(A2; accord A1.) The MCU, like the chip or stick interface, merely
responds to requests and does not initiate memory requests.
Rambus also unpersuasively argues that the following ‘097 patent
sentence distinguishes the disclosed memory devices over prior art memory
boards (and their controllers) such as the iAPX module: “‘Another unique
aspect of this invention is that each memory device is a complete,
independent memory subsystem with all the functionality of a prior art
memory board’.” (App. Br. 11, quoting ‘097 patent at col. 7, ll. 18-21).). To
the contrary, the sentence shows no distinction, and rather, shows that the
“invent[ive]” memory devices include new functions and prior art controller
functions, including the prior art iAPX MCU functions, because the iAPX’s
module and the ‘097 patent’s memory stick (and chip) are “complete
independent memory subsystem[s]” (id.) which may include controllers
and/or masters as discussed supra. Even the chip embodiments have control
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21
functions: “Registers store control information, device identification, device-
type and other information . . . .” (‘097 patent, col. 4, ll. 23-25.)
The memory devices also have “[n]ew bus interface circuits”
(‘097 patent, col. 4, l. 27) with such device identification and multiplexing
features.
15
The touted features would be within both of the disclosed
embodiments (i.e., the chip and stick), based, inter alia, on Rambus’s
replacement argument supra - with the stick having more functional
capability since it can include transceivers, masters, and other controllers.
Rambus maintains that using Inagaki’s clocking scheme in the iAPX
system would not have been obvious because Inagaki uses shift registers and
the iAPX system uses dual edges of two clocks for other specific functions.
(App. Br. 21-26.) Rambus’s arguments reduce to the unpersuasive assertion
that the two systems must be bodily incorporated. See In re Seed, 710 F.2d
1544, 1550 (Fed. Cir. 1983) (“[I]t is not necessary that the inventions of the
references be physically combinable to render obvious the invention under
review.”); In re Nievelt, 482 F.2d 965, 968 (CCPA 1973) (“Combining the
teachings of references does not involve an ability to combine their specific
structures”).
The iAPX system employs dual edges of two different periodic clocks
as Rambus acknowledges (App. Br. 23-24), and Inagaki teaches using dual
edges of a single clock in order to increase speed or reduce the number of
data paths in a memory device. (I1-I3.) For example, Inagaki discloses

15
See also Infineon, 318 F.3d at 1094 (“‘The present invention is designed
to provide a high speed, multiplexed bus . . . .’”) (quoting Rambus’s related
‘918 patent, col. 5, ll. 36-46).

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22
“performing I/O [input/output] of data on every half-cycle of the external
clock that drives the I/O shift register.” (I3.) As the Examiner finds,
Inagaki’s system “provides read/write data at twice the rate of the external
clock.” (RAN 68.) As the Examiner also reasons, “‘if a technique has been
used to improve one device, and a person of ordinary skill would recognize
that it would improve similar devices in the same way, using the technique is
obvious unless its application is beyond his or her skill.’” (Id. (quoting KSR
Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007)(citation omitted).)
Even if the iAPX Manual discloses a complicated system as Rambus
maintains (see App. Br. 23), skilled artisans would have recognized that
Inagaki teaches that data bus systems, like that of iAPX, can push data on
bus lines by using the rising and falling edges of a clock to trigger sampling
the data at twice the normal speed. (See I1-I3.) Rambus alleges that
Inagaki’s shift registers render unobvious using dual edge clocks in the
iAPX system for data transfer to the MCU, but the iAPX system already
employs dual clock edges as Rambus acknowledges. (Rambus App. Br..
23-24.) Therefore, contrary to Rambus’s assertions, skilled artisans would
have understood how to implement the known feature of using both clock
edges on data to maximize speed whether shift registers were employed or
not. As NVIDIA reasons: “the fact that iAPX already uses both rising and
falling edges of the clock” for other purposes “means that iAPX already has
the circuitry available to send/receive data on both edges” without a shift
register. (See NVIDIA Resp. Br. 12.)
It is also not entirely clear how any “combinatorial logic,” which
Rambus states Inagaki discloses, limits data speed as Rambus alleges. (App.
Br. 24.) Inagaki’s system increases the speed over prior art systems and
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23
Rambus does not direct attention to where Inagaki describes any such logic,
let alone logic which slows down Inagaki’s system. (See I1-I4, I7.) If by
logic Rambus refers to logic associated with a shift register, such logic is not
required to implement dual pulse edges as the iAPX Manual teaches as
discussed supra.
Rambus also argues that the iAPX system’s buffer directional control
precludes data transfers on both edges of CLKB. (See App. Br. 23.) Since
claim 1 does not require two-way traffic implicit in buffer directional
control, or even a buffer, the argument is not commensurate in scope with
the claim. Alternatively, skilled artisans would have recognized that buffer
directional control could have been provided with other CLKA or CLKB
edges (see NVIDIA Resp. Br. 12 n. 25), or even with other bused signals.
Still further, other modifications discussed below would not impact the
iAPX system adversely.
Inagaki’s teachings, and the iAPX use of dual edges, evidence a
reasonable expectation of success in using dual clock edges on data for
increased speed. Increased speed and compactness by reducing bus width
and corresponding pin number while saving cost (see I1) constitute universal
motivators. Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H.
Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit
motivation to combine exists … when the ‘improvement’ is technology-
independent and the combination of references results in a product or
process that is more desirable, for example because it is stronger, cheaper,
cleaner, faster, lighter, smaller, more durable, or more efficient.”)
Despite Rambus’s related arguments that the proposed modification
would render the iAPX system nonfunctional (see App. Br. 23-25), the
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24
Court also recognized that “the interaction of multiple components means
that changing one component often requires the others to be modified as
well.” KSR, 550 U.S. at 424. In other words, as KSR implies, making other
required modifications to increase the data speed by using both clock edges,
as Inagaki teaches (I1-I3), does not defeat obviousness or show
inoperability.
According to Rambus, “[c]omplex systems like iAPX’s cannot have
significant features replaced by other features.” (Rambus Reb. Br. 11.) But
Rambus fails to present evidence that skilled artisans would have been
unable to modify interrelated parts. Moreover, the arguments are not
commensurate in scope with broad claim 1 which does not have significant
interrelated features other than those required to sample data. As such,
given the claim breadth, skilled artisans easily could have modified the
iAPX system in view of Inagaki’s clocking scheme by dropping, instead of
replacing, many functions. Such a modification would create a “cleaner”
memory device for handling mere one-way data transfers embraced by broad
claim 1. Making a device “cleaner” (i.e., simpler) constitutes a universal
motivator under Dystar.
Alternatively, the combination does not require dropping any iAPX
functions. Skilled artisans would have recognized that the iAPX system
could have been modified to include the external slower Inagaki clock as a
trigger for the faster CLKA and/or CLKB –thereby retaining all existing
APX functions. That is, Inagaki (see Fig. 4) teaches that fast clocks can be
created by using the dual edges of a slower external clock. In Inagaki, a
slower external clock φ has rising and falling edges corresponding to and
triggering faster clocks φ1 and φ2 , suggesting a similar external clock to
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25
trigger the fast iAPX CLKA or CLKB. (See e.g. Inagaki Fig. 4; I3, I4.)
Inagaki and iAPX similarly employ multiple clocks, rendering such a
combination obvious.
The slower external clock’s rising and falling edges would simply
trigger the existing CLKA and CLKB, with the external clock’s rising and
falling edges corresponding to the existing rising edges of faster CLKB
and/or CLKA, and the latter clocks retaining all functions. The iAPX
Specification heuristically illustrates this concept (which Inagaki teaches as
noted) by showing a slower “INIT” clock trigger signal with falling and
rising edges corresponding to the faster CLKA rising edges. (See BIU-41.)
The ‘097 patent similarly discloses using internal clock complements being
created or triggered by external bus clocks. (See Fig. 13; App. Br. 4, 25-26
(describing the ‘097 patent’s internal “device” 500 MHz clocks as triggered
by dual edges of an external “bus” 250MHz clock).)
Despite Rambus’s arguments about existing device limitations based
on speed (see Rambus App. Br. 25-26 (discussing 10 MHz operation)),
faster memory devices than those disclosed in the iAPX system would have
been available at the time of the invention. And even if the iAPX
components could not have handled faster speeds, the iAPX system could
have benefitted, at the time of the invention, from a slower external clock’s
dual pulse speed doubling function as a mere substitute or trigger for the
existing clock timing, as Inagaki teaches (see I1-I3).
Rambus also raises an untimely new argument in its Rebuttal Brief
improperly buttressed by new evidence and thereby waives the argument.
Rambus alleges that the iAPX system requires holding BIU data on the
MACD bus over successive rising edges of CLKB, thereby precluding data
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26
transfers on the falling edge between the two rising edges. (See Rambus
Reb. Br. 11-12 (newly citing BIU-43 as evidence).)
16
But even if Rambus’s
characterizations are correct and timely, such data holding does not impact
the substitution and modification rationales described supra. For example,
having rising and falling edges of an external clock trigger the rising CLKB
edges does not impact any timing relying on those rising CLKB edges,
regardless of the data hold length. Or, replacing the iAPX system’s dual
clock system with Inagaki’s simpler single clock system to handle simple
one-way (or two-way) data transfers, without arbitration and other unneeded
functions pursuant to the breadth of claim 1, would obviously involve using
dual clock edges based on whatever the signal length constraints dictate.
Inagaki’s system provides the fastest speed relative to the dual clock edges
regardless of the data length, because the speed is ultimately governed by the
dual edges of the clock or the bus width and the system constraints. (See I1-
I3.)
Further, setting aside the above-discussed rationales for a moment,
while Rambus relies on an example to show that data is held over successive
CLKB edges, this does not mean that the iAPX MACD data cannot be
modified to correspond to rising and falling clock edges. Rambus’s reliance
on specific examples does not show that the iAPX system requires the data

16
Rambus supports the argument by discussing inherent hold and delay
times in the iAPX system. Rambus does not persuasively demonstrate that
those delays necessarily impact the data length on the bus. See id. at 11-12.
See BIU-40, 41, 43) (describing various inherent time delays between clock
edges and signals based on capacitance, etc.) Similar delays would occur in
the ‘097 patent system, but any such delays are not addressed in depth, if at
all.
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27
to be held for the duration argued, or that the data could not be modified to
be held for less than the time defined by the CLKA pulse, or that the CLKA
pulses could not be extended. As Rambus points out, the iAPX
Specification (at BIU-38) reveals that the BIU inputs and outputs
ACD15…0 data (to and from a processor) on the rising and falling edges of
CLKB. (See App. Br. 24; BIU 20.) This ACD data transfer further suggests
the claimed combination and suggests that other iAPX data, including MCU
data, need not be held for the duration that Rambus argues.
And even if the iAPX DRAMs or the MCU somehow constrain data
to be held as Rambus argues, faster devices at the time of filing of the ‘097
patent would not have been as constrained. For example, as indicated,
where the BIU uses both clock edges to transmit and receive data to and
from a (fast) processor on a single ACD bus (see BIU-20), the iAPX system
suggests, and Inagaki shows, that skilled artisans knew how to provide data
over the same bus using the falling and rising edges of a single clock.
In summary, the thrust of Rambus’s arguments, directed as they are
toward arbitration, buffer control, two-way traffic control between the
master BIU and slave memory device MCU, and other unclaimed features
(see e.g., App. Br. 22-23), are not commensurate in scope with claim 1,
which does not require those features. Claim 1 broadly embraces a method
for controlling a memory device which samples one-way data portions
“provid[ed]” at the memory device. Rambus has not demonstrated that
skilled artisans, motivated by Inagaki’s teaching of using rising and falling
clock edges for increasing data transfer speed to a known DRAM memory
device on a single bus, would not have been able to arrive at the broadly
claimed invention. Inagaki’s clocking scheme provides the fastest possible
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28
signal transfer on a bus, regardless of any signal length delays advanced by
Rambus, thereby providing the motivation for the modification.
Rambus’s other arguments fail to demonstrate Examiner error. The
Examiner’s findings and rationale and NVIDIA’s responses are more
persuasive than Rambus’s arguments. Based on the foregoing discussion,
Rambus failed to show error in the obviousness rejection of the claims based
on iAPX and Inagaki. See KSR, 550 U.S. 398, 416 (2007) (“The
combination of familiar elements according to known methods is likely to be
obvious when it does no more than yield predictable results.”).
Rambus also alleges in a section heading that “iAPX Does Not
Disclose Other Features Recited in the Claims.” (App. Br. 21 (emphasis
omitted).) But Rambus’s truncated arguments reduce to the unpersuasive
single-chip arguments addressed supra. For example, with respect to claim
26, Rambus asserts that “[t]he actual memory devices in the storage array of
iAPX never receive any block size information.” (Id.) Rambus makes
similar arguments with respect to claims 1 and 8 which fail show error.
Based on the foregoing discussion and the secondary considerations
discussed next, Rambus did not show error in the Examiner’s obviousness
rejection of claims 1-5, 7, 8, 10-12, 14, 26, 28-32, 34, and 35 based on the
iAPX (Manual and/or Specification) and Inagaki. Affirmance of the iAPX
based obviousness rejection renders it unnecessary to reach the Budde based
obviousness rejection. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir.
2009) (not reaching obviousness after finding anticipation).
Secondary Considerations
Rambus alleges secondary considerations of long-felt need, failure of
others, skepticism, commercial success, and praise by others, as rebuttal to
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29
the obviousness finding by the Examiner regarding claims 1-5, 7, 8 10-12,
14, 26, 28-32, 34, and 35. (App. Br. 27-30.) Rambus does specify which of
these claims relate to these secondary considerations.
Representative claim 1 includes limitations pertaining respectively to
a method of using the rising and falling edges of a clock signal but does not
require the operation code recited in claim 2. Rambus argues both of these
claim features addressed the long-felt need for higher memory performance.
(App. Br. 28.) But the claims do not require any higher performance or
address any bottleneck problem. Claims 1 and 2 do not recite a specific
clock speed and therefore embrace slow memory devices.
In addition, Mr. Murphy testifies that the memory industry started
looking for solutions to narrowing the performance gap between
microprocessors and memory chips “[i]n the 1990s.” (Murphy Dec. ¶ 28.)
Mr. Murphy does not specify what is meant by this 1990s timeframe or
provide evidence showing when the industry determined that there was a
problem in search of a solution. The earliest effective filing date recited on
the face of the ‘097 patent is April 18, 1990. That date implies that the
‘097 patent inventors solved a problem predicted by them to occur before
the industry even recognized a problem existed. For example, Mr. Murphy
also describes a commercial failure which occurred in the “mid-1990s.”
(Murphy Dec. ¶ 30.) Such evidence fails to establish an inventive solution
to a long-felt problem at the time of the effective filing date listed on the
face of the ‘097 patent.
According to Rambus, part of any alleged solution involves
employing both clock edges and using an operation code in a synchronous
RAM, but those features were not novel based on the anticipation of
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claims 1 and 2 by Inagaki. As such, Rambus has not established a nexus
between the claims and any alleged solution to a long-felt need. See Tokai
Corp. v. Easton Enters., Inc., 632 F.3d 1358, 1369 (Fed. Cir. 2011) (“If
commercial success is due to an element in the prior art, no nexus exists.”);
Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299, 1312 (Fed. Cir.
2006) (“[I]f the feature that creates the commercial success was known in
the prior art, the success is not pertinent.”).
Also, Rambus has not established that any commercial success is
commensurate in scope with the broad reach of the claims. See Application
of Tiffin, 448 F.2d 791 (CCPA 1971) (commercial success evidence of
thermoplastic foam cups is not commensurate in scope with broad claims
directed to thermoplastic foam containers). Even if Rambus’s evidence does
point to the unobviousness of using dual internal clock edges inside of a
single DRAM, the proffered evidence does not rebut the obviousness of
using these known features within other memory devices such as the iAPX
memory module and array.
Rambus also alleges commercial success by way of licensing
evidence for the “Farmwald Family.” (App. Br. 29.) But Rambus does not
point the Board to the evidence of any sales and it is well established that
competitors have many reasons for taking licenses which are not necessarily
related to unobviousness (i.e., litigation costs, etc.). Also, Rambus does not
explain whether the licenses pertain to DRAMs, generic memory devices,
memory controllers, or memory systems, or what claimed or disclosed
features are involved in the licenses.
Mr. Murphy testifies about “adding complexity to DRAMs,” that
“memory controllers available today . . . employ features that are claimed in
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31
the ‘097 patent” (Murphy Decl. ¶ 30), and that memory controllers and
synchronous memory devices were successful. But the claims here do not
involve controllers or DRAMs, while synchronous memory devices were
known. Therefore, Rambus has not shown that the proffered licensing
evidence is commensurate in scope with the claims at issue here.
Rambus also proffers evidence of praise for Dr. Horowitz, as a
pioneer in high bandwidth memory-interface technology. (App. Br. 29.)
Rambus adds, as evidence of skepticism, that “‘it was felt that . . . one could
not put a phase locked loop or a delay locked loop on the DRAM itself.’”
(Id.) But the memory devices rejected for obviousness do not require
DRAMs, let alone DRAMs with either phase or delay locked loops, or high
bandwidth technology. It follows that the proffered evidence of praise,
skepticism, and commercial success is not commensurate in scope with the
claims.
Also, the proffered arguments and other evidence suggest that many
other unclaimed features involving the ‘097 patent may have contributed to
any commercial success, including the delay-locked loop, multiplexed buses,
packetized control, identification control mechanisms, doubly terminated
clocks, memory controllers, synchronous DRAMs, and other features
“claimed in other patents derived from the ‘898 application.” (Murphy
Decl. 29.)
17
As such, the proffered secondary evidence is 1) not
commensurate in scope with the broad claims recited here because they do

17
See Infineon, 318 F.3d at 1095 (“the prosecution history shows that a
[high speed] multiplexing bus [in related Rambus patents] is only one of
many inventions disclosed in the ‘898 application”); see also Murphy Decl.
¶¶ 29-35 (describing purported success and other important aspects of the
invention in addition to the multiplexed bus).)
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32
not require the other features Rambus has claimed elsewhere, and 2) lacks a
nexus because any alleged success appears to be due partly to these
unclaimed features. NVIDIA’s responses also persuasively show a lack of
nexus. (NVIDIA Resp. Br. 13-15.)
Weak secondary considerations generally do not overcome a strong
prima facie case of obviousness. See Media Techs. Licensing, LLC v. Upper
Deck Co., 596 F.3d 1334 (Fed. Cir. 2010), cert. denied, 2010 WL 2897876
(Oct. 04, 2010) (“Even if [the patentee] could establish the required nexus, a
highly successful product alone would not overcome the strong showing of
obviousness.”). Rambus’s proffered secondary considerations fail to
outweigh the evidence and rationale of record for combining known prior art
dual edge clock features with known memory device methods to yield
predictable results as set forth in the method claims at issue here.

CONCLUSION
Rambus did not demonstrate that the Examiner erred in deciding to
reject claims 1, 2, 7, 8, 10, and 14 for anticipation based on Inagaki; or
claims 1-5, 7, 8, 10-12, 14, 26, 28-32, 34, and 35 for obviousness based on
the iAPX (Manual and/or Specification) and Inagaki. The Budde based
rejection is not reached.
DECISION
The Examiner’s decision to reject claims is affirmed.
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED
Appeal 2012-000171
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Patent 6,260,097

33
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I Idr,sir I
[COMPUT SCI] A file containing a series of commands
processed in the order given when the file is entered.
for command list. I 'se,list I
[INV zoo] The thickened, glandular, saddlelike por­
ebody wall of some annelid worms. I k1~'teh)m J
(AN AT) The homolog of the penis in females, located
anterior portion of the vulva. I 'klid-;;I-ras I
See clevis. I 'kliv'e }
The amount of insulation which will maintain nor­
of the human body when heat production
per meter squared per hour, air temper­
(21°C), and the air is still. I klo J
zoo1 The chamber which functions as a respi­
, ,.crP..orv and reproduclive duct in certain invertebrates.
chamber which receives the discharges of the
tract, and reproductive canals in monotrcmes,
birds, reptiles, and many fish. I k1o'a-k~ )
der [VERT ZOO] A diverticulum of the cloacal
monotremes, amphibians, and some fish, into which
forced from the cloaca. I klo'a:kat 'blad'n'se I
clock method [ORD] Method of calling artillery shots by
reference to the figures on an imaginary clock dial assumed to
have the target at its center; thus a shot directly above the target
is at 12 o'clock. I 'kllik ,meth':!d )
clock motor See timing motor. I 'kllik ,mOd-:lr I
clock oscillator [ELECTR] An oscillator that controls an elec­
tronic clock. ('kllik 'iis'a,l1id'~r )
clock paradox [RELAT] The apparent contradiction between
the principle of relativity, which asserts the equivalence of dif­
ferent observers, and the prediction, also part of the theory of
relativity, that the clock of an observer who passes back and
forth will be slower than the clock of an observer at rest. Also
known as twin paradox. I 'kllik ,paf'~,daks I
clOCk pulses [COMPUT SCI] Electronic pulses which are emit­
ted periodically, usually by a crystal device, to synchron~ze the
operation ofcircuits in a computer. Also known as clock Signals.
I 'klak ,p3J.sn }
clock rate [ELECTR] The rate at which bits or words are
transferred from one internal element of a computer to another.
[HOROL] The amount of time which a clock gains or loses
during a fixed period of time, usually a day. I 'klak ,riit I
clOCk signals See clock pulses. {'k1lik ,sig-n~lz I .
clock star [ASTRON] Any star that IS used to measure time;
always a bright star, whose right ascension j.s well known.
I 'klak ,star I
clock time See internal cycle time. I 'kllik I tim I
clock track [COMPUT SCI] A track on a magnetic recording
medium that generates clock pulses for the synchronization of
read and write operations. I 'kllik ,trak I
clock watch [HOROL] A watch that strikes the hours. ('kllik
,wiich)
clockwork [HOROL] A timing mechanism. I 'kllik,w~rk I
clod [AGR] A compact mass of soil, ranging from about 0.2
to 10 inches (0.5 to 25 centimeters) in size, which is produced
by plowing and digging ofexcessively wet or dry soil. I kliid I
clog snow [HYO] A skiing term for wet, sticky. new snow.
( 'ldag ,sno )
cloister vault [ARCH] A vault resembling a pyramid with
outward-curving sides. I 'kIOi'st~r,vOlt I
cloithoid See Cornu's spiral. t 'kIOi,th6id I
clone [BIOL] All individualS, considered collectively, pro­
duced asexually or by parthenogenesis from a single individual.
[COMPUT SCI] A hardware or software product that closely
resembles another product created by a different manufacturer
or developer, in operation, appearance, or both. [GEN] A copy
of genetically engineered DNA sequences. (klon I
clonorchiasis [MED] A parasitic infection of humans and
other fish-eating mammals which is caused by the trematode
Opisthorchis (Clonorchis) sinensis. which is usually found in
the bile ducts. I ,klon'or'kY-:l's:lS I
Clonothrix [MICROBIO) A genus of sheathed bacteria; cells
are attached and encrusted with iron and manganese oxides, and
filaments are tapered. {'kUin~,thriks I
clonus [PHYSIOj Irregular, alternating muscular contractions
and relaxations. I 'klo'o;.lS I
close [COMPUT sCll To make a file unavailable to a computer
program which previously had access to it. [METEoROL) Col­
loquially. descriptive of oppressively still, warm, moist air, fre­
quently applied to indoor conditions. {klos I
close-control radar [ENG} Ground radar used with radio to
position an aircraft over a target that is normally difficult to
locate or is invisible to the pilot. I :klOs k.,n'trol 'ra,diIr 1
close-coupled pump [MECH ENG] Pump with built-in elec­
tric motor (sometimes a steam turbine), with the motor drive
and pump impeller on the same shaft. I :klOs :k;;lp'<')ld 'p<')mp I
close coupling [ELEC] 1. The coupling obtained when the
primary and secondary windings of a radio-frequency or inter­
mediate-frequency transformer are close together. 2. A degree
of coupling that is greater than critical coupling. Also known
as tight coupling. I :klos 'k<')p-lig I
closed aerodrome [NAV1 An aerodrome at which ceiling and