Ex Parte 6236608 et al

Board of Patent Appeals and Interferences

May 9, 2012

90010426 (B.P.A.I. May. 9, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/010,426 02/26/2009 6236608 5545.2013 1793
7590 05/10/2012
Robert M. Shore, Esq.
Motley Rice LLC
14th Floor
1100 Glendon Avenue
Los Angeles, CA 90024-3503
EXAMINER
NGUYEN, TUAN H
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
05/10/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte FAST MEMORY ERASE, LLC1,
Appellant and Patent Owner
____________

Appeal 2011-010502
Reexamination Control No. 90/010,426
Patent 6,236,608 B12
Technology Center 3900
____________

Before JAMESON LEE, KARL D. EASTHOM, and
KEVIN F. TURNER, Administrative Patent Judges.

TURNER, Administrative Patent Judge.

DECISION ON APPEAL
Fast Memory Erase, LLC, Appellant, appeals under 35 U.S.C. §§
134(b) and 306 from a final rejection of claims 1, 16, 29-31, 35, 36, 43, and
46-49. We have jurisdiction under 35 U.S.C. §§ 134(b) and 306.
We REVERSE the Examiner’s rejections and enter new grounds of
rejection against some of the previously-rejected claims.

1 Fast Memory Erase, LLC is the Patent Owner and the real party in interest
(App. Br. 2).
2 Issued May 22, 2001, to Perumal Ratnam.
Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

2

STATEMENT OF THE CASE3
This proceeding arose from a request for ex parte reexamination filed
on behalf of Intel Corporation on February 26, 2009, of United States Patent
6,236,608 B1 (the '608 Patent), based on U.S. Patent Application
09/375,702, filed August 16, 1999.
The '608 Patent was asserted in Fast Memory Erase, LLC v. Spansion,
Inc., et al., CA No. 3:08-cv-0977-M (N.D. Tex. 2008) (App. Br. 4).
We heard oral arguments from Patent Owner’s representative on
November 2, 2011, a transcript4 of which is part of the record.

CLAIMED INVENTION
Appellant’s invention relates to flash erasable programmable read-
only memory (EPROM) cells and an erase technique that reduces leakage
during source erase of a flash EPROM cell (col. 1, ll. 8-13).
Claims 1, 16, and 29-49 are pending and subject to reexamination.
Original claims 2-15 and 17-28 are not subject to reexamination, and claims
32-34, 37-42, and 44-47 have been allowed or indicated to be allowable
(Ans. 10-12). Claims 1, 16, 29-31, 35, 36, 43, 48, and 49 have been rejected
and are appealed (Reply Br. 2, 4).

3 Our decision will make reference to the Appellant’s Appeal Brief (“App.
Br.,” filed August 30, 2010) and Reply Brief (“Reply Br.,” filed April 11,
2011), and the Examiner’s Answer (“Ans.,” mailed February 11, 2011).
4 Record of Oral Hearing (hereinafter Oral Hr’g Tr.)
Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

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We take independent claim 1 to be representative:
1. A method for erasing a semiconductor device
comprising:
applying a voltage pulse at the source of the
semiconductor device, wherein said pulse comprises a rapid
increase in magnitude of voltage which is sustained for an
interval of time followed by a rapid decay in magnitude of
voltage; and
applying a multiple step voltage pulse of the opposite
polarity, said multiple step voltage pulse having at least a first
voltage pulse and a second voltage pulse, at the gate of the
semiconductor device;
wherein each of said first and second voltage pulses
comprises a rapid increase in magnitude of voltage which is
sustained for an interval of time followed by a rapid decay in
magnitude of voltage; and
wherein said second voltage pulse is greater in magnitude
than said first voltage pulse.
(App. Br. 19, Claims App’x., emphasis added).

REJECTIONS OVER ART
The Examiner maintained a rejection of the claims on the following
basis:
 claims 1, 16, 29-31, 35, 36, 43, 48, and 49 under 35 U.S.C. § 102(e)
as being anticipated by Muramoto5 (Ans. 3-8);

5 U.S. Patent No. 5,825,062, issued Oct. 20, 1998, to Jun Muramoto, having
a filing date of Dec. 10, 1996.
Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

4

Appellant relies upon the following evidence in rebuttal to the
Examiner’s rejection:
 Declaration of David Kuan-Yu Liu, Ph.D., dated August 31, 2009
(App. Br.; Evidence Appx.)(“Liu Decl.”).

ISSUE
Appellant has asserted numerous arguments as to whether the
Examiner erred in proffering the above-cited rejection, which we detail in
the analysis section below. We have considered in this decision only those
arguments that Appellant actually raised in the Briefs. Arguments which
Appellant could have made but chose not to make in the Briefs are deemed
to be waived. See 37 C.F.R. § 41.37(c)(1)(vii).
The issue arising from the respective positions of Appellant and the
Examiner, which we consider herein, is:
Did the Examiner err in finding that Muramoto anticipates the subject
matter of claims 1, 16, 29-31, 35, 36, 43, 48, and 49?
FINDINGS OF FACT
1. The '608 Patent is directed to flash erasable programmable read-
only memory (EPROM) cells and an erase technique that reduces
leakage during source erase of a flash EPROM cell (col. 1, ll. 8-
13).
2. According to a third embodiment disclosed in the '608 Patent, a
voltage pulse (704) is applied to the source of an EPROM cell and
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Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

7

of a positive voltage and turning the control gate electrode 7
into a level of a negative voltage.
(col. 5, ll. 17-28).

PRINCIPLES OF LAW
Anticipation is established when a single prior art reference discloses,
expressly or under the principles of inherency, each and every limitation of
the claimed invention. Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342,
1347 (Fed. Cir. 1999).
A finite number of solutions within the skill and understanding of
ordinarily skilled artisans can be indicative of obviousness:
When there is a design need or market pressure to solve a
problem and there are a finite number of identified, predictable
solutions, a person of ordinary skill has good reason to pursue
the known options within his or her technical grasp. If this
leads to the anticipated success, it is likely the product not of
innovation but of ordinary skill and common sense.
KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).

ANALYSIS
Central to both of the instant independent claims 1 and 29 is the
application of a pulse voltage to the source of the memory device, and
pulses, of the opposite polarity, applied to the gate (FF 2-3). Muramoto
discloses, primarily, a series of pulses to the source, with progressive
voltages applied through those pulses (FF 4), and also discloses that the
Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

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same voltage differences can be applied through other combinations of
voltages applied to the source and gate (FF 5).
Appellant argues that Muramoto discloses a genus, whereas the
“mirror image embodiment,” alleged to be applied by the Examiner in the
rejection, is a species thereof (App. Br. 15; Reply Br. 4). Appellant cites to
Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868 F.2d 1251, 1262
(Fed. Cir. 1989), for the proposition that a reference that discloses a genus
does not thereby disclose each species within that genus, and we agree.
Muramoto’s disclosure that positive voltages may be applied to the source
and negative voltages may be applied to the gate to achieve the same voltage
difference required for erasure (FF 5) would have informed one of ordinary
skill in the art of the myriad of different ways of achieving that erasure, but
would not necessarily specifically teach the pulses applied in the methods
recited by independent claims 1 and 29. As such, we find that Muramoto
does not anticipate the subject matter of claims 1 and 29, and claims
dependent thereon, and we conclude that the Examiner erred in rejecting 1,
16, 29-31, 35, 36, 43, 48, and 49 under 35 U.S.C. § 102(e) as being
anticipated by Muramoto.

New Grounds of Rejection Under 37 C.F.R. § 41.50(b)

Claims 1 and 29 Obvious Over MuramotoUnder35 U.S.C. § 103

Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

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As discussed above, independent claims 1 and 29 both recite
application of a pulse voltage to the source of the memory device, and
pulses, of the opposite polarity, applied to the gate (FF 2-3). Appellant has
acknowledged that “mirror image embodiment,” applied by the Examiner in
the rejection, is a species of the genus disclosed by Muramoto (App. Br. 15;
Reply Br. 4). Thus, one of ordinary skill in the art would have understood
that one species of the genus, such as the “mirror image embodiment,” could
have been selected and applied based on Muramoto, which Appellant has
acknowledged (Oral Hr’g Tr. 8). However, Appellant has argued that “[i]t’s
not obvious to pick and choose the positive and the negative levels because
of the disadvantages” (Oral Hr’g Tr. 9), but we disagree.
One of ordinary skill in the art would have known that each set of
parameters within the genus of Muramoto would come with specific
advantages and a different set of disadvantages. Acknowledging those
advantages and disadvantages does not change the obviousness of those
parameters. Selecting a subset of those parameters, whereas a pulse is
applied to source, and opposite polarity pulses are applied to the gate, per
independent claims 1 and 29, would be employing routine voltage
summation principles and selecting a finite number of identified, predictable
solutions within the disclosed solution. Thus, we find that claims 1 and 29
would have been obvious to one of ordinary skill in the art in view of
Muramoto.
Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

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We also acknowledge that Dr. Liu has testified that nothing in
Muramoto would have motivated an ordinarily skilled artisan to pick “any
specific waveform that would practice the invention” (Liu Decl. 9), and that
many selections would achieve the voltage difference required by Muramoto
but not reach the subject matter of the claims (Liu Decl. 10-12). However,
that does not change the obviousness of the different waveforms suggested
by Muramoto, given that one of ordinary skill in the art is not an automaton
and would apply proper judgment in selecting from the discussed options.
Indeed, Muramoto’s disclosure of many options, without focusing on a
single option, is not a teaching away from any single option.
Dr. Liu also testifies with respect to the disadvantages of employing
the different parameters for the application of voltages to the source and gate
of the memory device of Muramoto (Liu Decl. 13-18). He provides that
these disadvantages might include increased power requirements, an
additional pullback voltage generator, timing circuits, and additional wiring
(id.). However, potential advantages and disadvantages are always
considered when constructing an embodiment, but they do not necessarily
speak to the obviousness thereof. Modifications are necessarily required
where a reference provides a general teaching and discloses that other
embodiments may achieve the same result through different configurations.
Muramoto itself provides no negative teachings as to any embodiment that
would council those who practice its methods to avoid specific
configurations. As such, we do not find Dr. Liu’s analysis to be persuasive
Appeal 2011-010502
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as to the unobviousness of the subject matter of claims 1 and 29 in view of
Muramoto. Thus, we reject claims 1 and 29 as being obvious over
Muramoto under 35 U.S.C. § 103.

CONCLUSION
We conclude that the Examiner erred in finding that that Muramoto
anticipates the subject matter of claims 1, 16, 29-31, 35, 36, 43, 48, and 49.
We enter a new ground of rejection finding that independent claims 1 and 29
are obvious over Muramoto.

DECISION
We have reversed the Examiner’s rejection of claims 1, 16, 29-31, 35,
36, 43, 48, and 49. However, we have entered new grounds of rejection
under 37 C.F.R. § 41.50(b) for independent claims 1 and 29. Although we
have not entered a new ground of rejection for every claim under our
discretionary authority, we emphasize that our decision does not mean the
remaining claims are patentable. Rather, we merely leave the patentability
determination of these claims to the Examiner. See MPEP § 1213.02.
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) provides "[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
Appeal 2011-010502
Reexamination Control No. 90/010,426
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review."

37 C.F.R. § 41.50(b) also provides that the Appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of
the claims so rejected or new evidence relating to the claims so
rejected, or both, and have the matter reconsidered by the
examiner, in which event the proceeding will be remanded to
the examiner. . . .
(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same record. . . .

REVERSED; 37 C.F.R. § 41.50(b)

Appeal 2011-010502
Reexamination Control No. 90/010,426
United States Patent 6,236,608 B1

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ack

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FOR PATENT OWNER:
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