Ex Parte 6182184 et al

Board of Patent Appeals and Interferences

Jan 19, 2012

95000183 (B.P.A.I. Jan. 19, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,112 11/17/2008 6,182,184 8963.002.184 6635 22852 7590 01/19/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 01/19/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/000,183 08/24/2007 6182184 38512.5 2395 22852 7590 01/19/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 01/19/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Inter Partes RAMBUS, INC. Patent Owner v. SAMSUNG ELECTRONICS, CO., LTD. and MICRON TECHNOLOGY INC. ______Requestors______ Appeal 2011-008431 Reexamination Control Nos. 95/000,183 & 95/001,112 United States Patent 6,182,184 B1 Technology Center 3900 ____________ Before ALLEN R. MacDONALD, KARL D. EASTHOM, and STEPHEN C. SIU, Administrative Patent Judges. EASTHOM, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 This proceeding arose out of separate third party requests by Samsung Electronics Co., Ltd, and Micron Technology, Inc., for inter partes reexaminations of U.S. patent 6,182,184 B1 to Farmwald et al., Method of Operating a Memory Device Having a Variable Data Input Length (Jan. 30, 2001) assigned to Rambus, Inc. The USPTO granted the two requests, respectively assigned Reexamination Control Nos. 95/000,183 and 95/001,112, and then, merged the two. (See Decision, Sua Sponte, to Merge Reexamination Proceedings, Mar. 6, 2009.) Requestor Samsung Electronics, Co., Ltd. has not filed a brief in this proceeding. Appellant, Patent Owner Rambus, appeals under 35 U.S.C. §§ 134(b) and 306 from the Examiner’s Right of Appeal Notice (RAN) rejecting claims 1-23 of the ‘184 patent. (P.O. App. Br. 1.) Respondent, Requestor Micron, filed a Responsive Brief disputing contentions by Rambus and supporting the Examiner’s decision. (Micron Resp. Br.) Claims 24-29 have been confirmed and are not on appeal. Requestor Micron also cross-appeals from the Examiner’s decision in the RAN not to maintain some of Micron’s and Samsung’s proposed rejections of claims 13 and 14. (Micron Cr. App. Br. 3-6). Rambus filed a responsive brief opposing the cross-appeal and supporting the Examiner’s decision not to adopt those proposed rejections. (P.O. Resp. Br.). Rambus and Micron also each filed rebuttal briefs. (P.O. Reb. Br.; Micron Reb. Br.) We have jurisdiction under 35 U.S.C. §§ 134(b) and 315. We AFFIRM certain of the adopted rejections of claims 1-23 and decline to reach other proposed rejections which the Examiner maintained or failed to maintain. See 37 C.F.R. 41.77 (a) (“The Board . . . may affirm or reverse each decision of the examiner on all issues raised on each appealed Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 3 claim . . . .”); cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding anticipation). STATEMENT OF THE CASE Appellant Rambus and Respondent Micron refer to several related judicial and other proceedings including inter partes and ex parte reexaminations, International Trade Commission proceedings, and Federal District Court and Circuit Court proceedings in their briefs. An oral hearing of this appeal and a related inter partes reexamination appeal (App. No. 2011-009664) involving the same parties transpired concurrently on Sept. 21, 2011 and was subsequently transcribed as one document. Exemplary Claims Exemplary claims on appeal follow: 1. A method of controlling a memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be sampled by the memory device in response to a write request; issuing a first write request to the memory device, wherein in response to the first write request the memory device inputs the first amount of data corresponding to the first block size information; and providing a first portion of the first amount of data to the memory device synchronously with respect to a first transition of an external clock signal, and a second portion of the first amount of data synchronously with respect to a second transition of the external clock signal. Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 4 13. A method of operation of a memory device, wherein the memory device includes a plurality of memory cells, the method of operation of the memory device comprises: receiving first block size information from a master, wherein the first block size information defines a first amount of data to be sampled by the memory device in response to a write request; receiving a first write request from the master; and sampling a first portion of the first amount of data synchronously with respect to a first transition of an external clock signal and a second portion of the first amount of data synchronously with respect to a second transition of the external clock signal. 14. The method of claim 13 wherein the first transition of the external clock signal is a rising edge transition and the second transition of the eternal clock signal is a falling edge transition. 22. The method of claim 13 further including generating an internal clock signal using a delay locked loop circuit and the external clock signal wherein the first amount of data corresponding to the first block size information is sampled in response to the internal clock signal. 23. The method of claim 13 further including generating first and second internal clock signals using clock generation circuitry and the external clock signal wherein the first amount of data corresponding to the first block size information is sampled synchronously with respect to the first and second internal clock signals. Rejections The Examiner adopted the following proposed rejections: Claims 1-10, 13, 15, 16, 18, 19, and 21 under 35 U.S.C. 102(b) as anticipated based on iAPX. 1 1 iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 5 Claims 1-7, 9, 10, 13, 15, 16, 18, 19, and 21 under 35 U.S.C. 102(b) as anticipated based on Budde. 2 Claims 13 and 14 as anticipated under 35 U.S.C. 102(b) based on Novak. 3 Claims 11, 12, 14, 17, 20, and 23 under 35 U.S.C. 103(a) as obvious based on either iAPX or Budde, and Inagaki. 4 Claim 22 under 35 U.S.C. 103(a) as obvious based on either iAPX or Budde, and Lofgren. 5 (See P.O. App. Br. 5-6.) ISSUES Rambus and Micron raise the following issues: Did the Examiner err in finding that the memory device recited in claim 1 reads on the memory module of iAPX? Did the Examiner err in finding that the combination of iAPX and Inagaki renders claim 14 obvious? Did the Examiner err in finding that the combination of iAPX and Lofgren renders claim 22 obvious? PRINCIPLES OF LAW Claims “must be read in view of the specification. . . . [T]he specification ‘is always highly relevant to the claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of a 2 Budde et al., U.S. 4,480,307 (Oct. 30, 1984). 3 Novak et al., U.S. 4,663,735 (May 5, 1987). 4 Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an English language translation of record). 5 Lofgren et al., G.B. 2,197,553 A (May 18, 1998). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 6 disputed term.’” Phillips v. AWH Corp., 415 F.3d, 1303, 1315 (Fed. Cir. 2005) (en banc) (citation omitted). Also, “the ordinary and customary meaning of a claim term is the meaning that the term would have to a person of ordinary skill in the art in question at the time of the invention, i.e., as of the effective filing date of the patent application.” Id. at 1313 (internal citations omitted). “‘[A] claim interpretation that would exclude the inventor’s device is rarely the correct interpretation; such an interpretation requires highly persuasive evidentiary support . . . .’” Interactive Gift Exp. Inc. v. Compuserve Inc. 256 F.3d 1323, 1343 (Fed. Cir. 2001) (quotingModine Mfg. Co. v. U.S. Intern. Trade Comm’n, 75 F.3d 1545, 1550 (Fed. Cir. 1996).) FINDINGS OF FACT (FF) The iAPX Manual A1. Figure 1-2 of the iAPX Manual follows: Figure 1-2 depicts a memory module comprising a memory storage array and a MCU (Memory Control Unit). (iAPX Manual 1-3). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 7 “The storage arrays will typically be constructed with high-density dynamic RAM (DRAM) components.” The MCU requires a “modest amount of external logic . . . to interface the MCU to the storage array RAMs - - for simple configurations, as few as 12 external TTL packages are required.” (iAPX Manual 1-4.) A2. The memory module constitutes “a memory confinement area.” (iAPX Manual 1-8, 3-2.) The MCU “interfaces memory storage arrays to the memory bus.” (iAPX Manual 1-4.) A3. A component level constitutes the lowest level of hardware in the system, an example of which is a RAM chip. A module comprises a group of interconnected components. (iAPX Manual 2-1.) The presence or absence of any module does not prevent communication between any other modules. (iAPX Manual 2-6.) The ‘184 Patent D1. The ‘184 patent states that “[p]referred devices for use in this invention include device-type register information specifying the type of chip.” (Col. 7, ll. 53-54.) D2. The ‘184 patent refers to chips as devices as follows: “Fig. 8b illustrates how each device 51, 52 receives each of the two bus clock signals . . . .” (Col. 19, ll. 14-15.) Figures 8A and 8B label each device 51 and 52 as a “CHIP.” D3. The disclosed invention reduces consumed power: By using a single row access in a single RAM to supply all the bits for a block request (compared to a row-access in each of multiple RAMs in conventional memory systems) the power per bit can be made very small. Since the power dissipated by memory devices using this invention is significantly reduced, Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 8 the devices potentially can be placed much closer together than with conventional designs. (Col. 17, ll. 18-25) D4. Memory devices are described as subsystems with all the functionality of prior art memory boards: “Another unique aspect of this invention is that each memory device is a complete, independent memory subsystem with all the functionality of a prior art memory board in a conventional backplane-bus computer system.” (Col. 7, ll. 18-22.) As one example, the memory devices must be able to decode packets sent by a bus master. (Col. 8, l.65 to col. 9, l.10.) The memory device must be able to “initiate[] certain functions” and coordinate when to immediately set up internal addressing and when to respond to the master by writing or reading data from or to the bus based on “a time specified in the request packet control information” and also based on time “selected from values stored in slave access-time registers.” (Col. 9, ll. 11-23.) D5. Slaves and masters are described as follows. [T]his invention connects master or bus controller devices, such as CPUs, Direct Memory Access devices (DMAs) or Floating Point Units (FPUs), and slave devices, such as DRAM, SRAM or ROM memory devices. A slave device responds to control signals; a master sends control signals. Persons skilled in the art realize that some devices may behave as both master and slave at various times, depending on the mode of operation and the state of the system. For example, a memory device will typically have only slave functions, while a DMA controller, disk controller or CPU may include both slave and master functions. Many other semiconductor devices, including I/O devices, disk controllers, or other special purpose devices such as high speed switches can be modified for use with the bus of this invention. (Col. 6, ll. 13-27 (emphasis added).) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 9 D6. A primary bus unit in the ‘184 patent has two or more devices, typically 32, connected to a transceiver device 19. A primary bus unit can be mounted on a circuit board 66, sometimes called a memory stick. A primary bus unit is also a memory subsystem. The circuit board includes the transceiver device 19, two or more memory devices, and a primary bus 18 connecting the devices together. The circuit board connects to a transceiver bus 65. (Col. 19, ll. 46-67.) D7. The memory stick embodiment is described more fully as follows: Referring to FIG. 9, each primary bus unit can be mounted on a single circuit board 66, sometimes called a memory stick. Each transceiver device 19 in turn connects to a transceiver bus 65, similar or identical in electrical and other respects to the primary bus 18 described at length above. In a preferred implementation, all masters are situated on the transceiver bus so there are no transceiver delays between masters and all memory devices are on primary bus units so that all memory accesses experience an equivalent transceiver delay, but persons skilled in the art will recognize how to implement systems which have masters on more than one bus unit and memory devices on the transceiver bus as well as on primary bus units. In general, each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices on an attached primary bus unit. Other devices, generically referred to as peripheral devices, including disk controller, video controllers or I/O devices can also be attached to either the transceiver bus or a primary bus unit, as desired. Persons skilled in the art will Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 10 recognize how to use a single primary bus unit or multiple primary bus units as needed with a transceiver bus in certain system designs. (Col. 19, l. 60 to col. 20, l. 14 (emphasis added).) D8. The ‘184 patent refers to busing a TrncvrRW signal “to all devices on the transceiver bus” 65. (Col. 20, ll. 33 (emphasis added).) Figure 9 depicts one such device, a memory stick, connected to the transceiver bus 65. (The memory stick includes a circuit board 66, transceiver device 19 and “DRAMS or other devices 15, 16, and 17” (col. 20, l. 65), and can include “masters” (see D5, D7).) The ‘184 patent states that the TrncvrRW signal indicates “valid data to a slave.” (Col. 20, ll. 36-37.) D9. “One object of the present invention is to use a new bus interface built into semiconductor devices to support high-speed access to large blocks of data from a single memory device by an external user of the data, such as a microprocessor, in an efficient and cost-effective manner.” (Col. 3, ll. 23-27.) The ‘184 patent also provides “individual devices,” (col. 3, l. 61), “devices, especially DRAMs,” (col. 3, ll. 46-47), and transfers data blocks “to one single device at a time” (col. 4, ll. 19-20). D10 According to one aspect of the invention, prior art DRAMs are modified to include column access circuitry, provisions for multiplexing and demultiplexing, and bus lines are doubly terminated to run high clock rates. (Col. 4, ll. 21-50.) Fewer bus lines are employed with the bus carrying device select information as compared to prior art conventional schemes. (Col. 3, ll. 51-61.) Also, bus master sets and control access time registers, Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 11 control registers, and memory registers in devices, and control packets are employed. (Col. 6, ll. 38-60.) The bus master must ensure the bus is free and provides arbitration. (Col. 8, 1l. 53-58.) Inagaki 6 I1. Inagaki discloses a method for increasing data rates in block access memory. As background, Inagaki teaches that conventional methods to increase data transfer rates in RAMs were to increase the data bus width, which adds cost of packaging and pin count, or to increase the clock rate. (Inagaki 2.) Inagaki’s solution is to use dual edges of a clock as quoted as follows. I2. “The rise and fall of external clock φ are detected, and clocks φ1 and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift register. . . . In this way, since one bit is output on each half-cycle, the operating speed is twice that of the conventional speed.” (Id. at 4). I3 “[T]he present invention presents block access memory that transfers data with a speed that is twice the conventional speed, by performing I/O [input/output] of data on every half-cycle of the external clock that drives the I/O shift register.” (Id. at 3.) ANALYSIS 6 Reference hereinafter is to an English translation attached to Micron’s Appeal Brief as Exhibit E8. Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 12 The findings of the Examiner and the position and rationale of the Requestor as set forth in the Answer, RAN, and Briefs are hereby adopted and incorporated by reference. Anticipation With respect to the first issue of anticipation based on iAPX, the issue is the virtually the same issue as that addressed in our previous decision (Appeal No. 2010-011178), now on appeal to the Federal Circuit (Appeal No. 2011-1247). The patent there (U.S. 6,034,918) and the ‘184 patent here claim continuity back to the same application (App. No. 07/510,898) and appear to have the same or substantially the same disclosures. As such, the findings and reasoning in that prior decision are adopted and incorporated by reference here to the extent that those findings and rationale apply here (i.e., without raising new issues). The specific issue of whether a memory device reads on the iAPX module is the same here as it is in our prior ‘1178 decision. To the extent different evidence, arguments, and positions exists here, this Decision addresses the different positions to supplement the incorporation by reference of our prior decision and the findings, rationale and positions of the Examiner and Micron mentioned supra. Most, if not all, of Rambus’s arguments, while couched in terms that seem to constitute separate patentability arguments, reduce to the issue of whether or not the iAPX module is a memory device. For example, Rambus lists essentially all the claim elements of claims 1 and 13 and asserts that “Rambus will show that it is entitled to reversal based on every feature.” Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 13 (P.O. App. Br. 6.) However, Rambus’s advanced reasons reduce later in the Brief to the assertion that the iAPX module is not a device. For example, Rambus argues that the iAPX Manual does not disclose providing first and second portions of data synchronously “because the memory module in iAPX is not the claimed memory device.” (P.O. App. Br. 33.) At other portions, Rambus describes DRAMS, write requests, block size information, delay locked loop, and double data rate, but Rambus does not assert or explain persuasively that the iAPX module, the asserted memory device, fails to perform any claimed functions. (See P.O. App. Br. 7-10.) As another example, Rambus asserts that the memory devices described in the iAPX Manual do not receive write requests. (P.O. App. Br. 12.) But then Rambus refers to the iAPX’s “DRAMs themselves [which] never receive the alleged block size information.” (App. Br. 12 (emphasis added).) And Rambus acknowledges that the memory control unit (MCU) “may receive a command from a processor indicating that multiple bits of data are to be written (which the Examiner alleges to be block size information).” (Id.) (Accord P.O. App. Br. 33 (“iAPX does not disclose a memory device [i.e., a DRAM] receiving ‘block size information’ or receiving a ‘write request’”); Ans. 56-56 (pointing out that Rambus does not argue that the iAPX memory module fails to satisfy any limitations other than the device limitation); Ans. 80-91 (similar rationale).) As stated, Rambus’s arguments reduce to the repeated assertion that the iAPX module is not a device. While the ‘184 patent expired during the reexamination proceeding, as Micron argues, prior to that, “Rambus had ample opportunity to modify its claims to correspond to its desired single chip claim scope, but chose to Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 14 forego that opportunity.” (Micron Resp. Br. 6.) And Rambus knew how to so amend the claims. See, e.g., Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1091 (Fed. Cir. 2003) (holding that the term “integrated circuit device” as recited in claim 26 of Rambus’s related ‘804 patent takes its ordinary meaning of “chip”) (internal quotation marks and citations to trade dictionaries and other authority omitted) 7 ; accord Micron Resp. Br. 14-15 (listing Rambus claims in other patents, reciting, for example, “a single semiconductor substrate”).) Here, Rambus does not maintain that other known memory devices constitute single chips and does not present persuasive objective evidence, if any, by way of either trade dictionaries or other prior art literature, establishing the plain meaning of a memory device as limited to a single chip, cf. Infineon, 318 F.3d at 1091. The terms “device” 8 and “memory” 9 ordinarily are not limited to a single chip. Rambus does not show how the two terms together create a plain meaning of a single chip. Based on the definitions of the two terms (supra notes 8 and 9), the plain meaning of the term “memory device” implies a device that includes memory. 7 The Federal Circuit in Infineon found that the written descriptions of each of four Rambus patents, 5,954,804; 5,953,263; 6,034,918; and 6,032,214, are substantially identical to the written description of the 5,243,703 patent and the 07/510,898 application filed in April 1990. Id. at 1084-86. The ‘184 patent also derives from the 1990 ‘898 application, also rendering its written description substantially identical to those just noted. 8 “Something constructed or devised for a particular purpose, esp. a machine used to perform one or more relatively simple tasks.” Webster’s II New Riverside Dictionary 370 (1984). 9 “A unit of a computer that stores data for retrieval.” Webster’s II New Riverside Dictionary 741 (1984). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 15 Rambus’s expert, Mr. Murphy, and other experts of record, Mr. Rhoden and Mr. McAlexander (see P.O. App. Br. 21-22), are addressed persuasively by the Examiner (see Ans.68-70) and Micron (Micron Resp. Br. 11-12), and the respective positions show that no expert here sets forth a persuasive plain meaning of the term “memory device” limiting it to a chip. 10 It follows that Rambus’s attempt to narrow the term “memory 10 In its Federal Circuit appeal brief, appealing the above-noted related Board decision (Bd. App. No. 2010-011178, Fed. Cir. App. No. 2011-1247), Rambus characterizes Murphy’s and McAlexander’s testimony as “at best, a wash,” with Mr. McAlexander “nakedly opin[ing]” and rendering a “conclusory” opinion because it lacked any context to the patent at issue. (Rambus ‘1247 Fed. Cir. App. Br. at 23.) Rambus also argues that Mr. Rhoden, a “Rambus adversary,” in other litigation, confirms the ordinary meaning of a memory device as a single chip because he “testified in an unrelated interference proceeding that it was ‘typically not’ the case that ‘memory device’ referred to a card with multiple chips on it.’.” (Id. (citation omitted).) Mr. Rhoden’s testimony occurred in a related Rambus interference proceeding involving a patent (to Perego et al., U.S. 6,502,161 B1) assigned to Rambus (with junior party Rambus and senior party Drehmel). (See BPAI Interference No. 105,467 (June 2010).) The context of the testimony there is not clear, Rambus took the deposition, the Board’s interference opinion does not rely on it, and it occurs in 2007, well after the filing date here, shedding scant light on ordinary meaning at the time of the invention. And Rambus inconsistently dismisses McAlexander’s testimony about plain meaning because it lacks context to the patents at issue (Rambus ‘1247 Fed. Cir. App. Br.23), while accepting Mr. Rhoden’s testimony without describing its context to the ‘184 patent. (See id. and P.O. App. Br. 21-22). Mr. Rhoden makes clear that “‘in the context [t]here [there is] probably . . . very little difference’” between a memory chip and a memory device, but also that a memory module can be a memory subsystem. (See ‘1178 decision at 21-22 (discussing expert testimony and quoting Rhoden deposition (citation thereto omitted).) But before the Federal Circuit, Rambus maintains that the “‘ordinary meaning . . . depends on the ‘context Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 16 device” to “memory chip” must derive chiefly from the ‘184 patent. See Phillips, 415 F.3d at 1316 (the specification can limit the apparent breadth of a claim if the specification reveals a “special definition . . . that differs from the meaning it would otherwise possess,” or if the “specification . . . reveal[s] an intentional disclaimer, or disavowal of claim scope, by the inventor”); Helmsderfer v. Brobrick Washroom Equip., Inc., 527 F.3d 1379, 1381 (Fed. Cir. 2008) (“A patentee may act as its own lexicographer and assign to a term a unique definition that is different from its ordinary and customary meaning; however, a patentee must clearly express that intent in the written description.”). But Rambus’s proffered arguments and evidence fail to establish such a special definition, intentional disclaimer, or disavowal of claim scope, implied or otherwise. Rather, Rambus improperly attempts to elevate a disclosure of preferred DRAM chip embodiments (see D1, D2, D9) to such a special definition. It is normally improper to limit claims based on a preferred embodiment. “Even when the specification describes only a single embodiment, the claims of the patent will not be read restrictively unless the patentee has demonstrated a clear intention to limit the claim scope using ‘words or expressions of manifest exclusion or restriction’.” Leibel- Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004) (citation omitted). In an attempt to inferentially limit the claim scope so as to preclude reading it on the iAPX memory module, Rambus points to the following phrase in the ‘184 patent: “‘each memory device is a complete, independent of the entire patent, including the specification’.” (Rambus ‘1247 Fed. Cir. App. Br. 21 (quoting Phillips, 415 F.3d at 1313).) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 17 memory subsystem with all the functionality of a prior art memory board in a conventional backplane-bus computer system.’” (P.O. App. Br. 19 (citing ‘184 patent at col. 7, ll. 19-25); also quoted supra at D4.) Rambus explains that this sentence, and certain disclosed advantages touted, including reduced power in disclosed devices (see D3), contrasts prior art memory boards such as the iAPX memory module because the invention “seeks to achieve the functionality of a prior art memory board in a single memory device.” (See P.O. App. Br. 18-19). According to Rambus, “[i]f a ‘memory device’ in this context could refer to many memory devices connected to a memory controller, the discussion would be nothing more than a description of the operation of a conventional memory system that relied on prior art memory boards, which makes no sense.” (App Br. 18.) These arguments are unconvincing for several reasons. First, “[t]he fact that a patent asserts that an invention achieves several objectives does not require that each of the claims be construed as limited to structures that are capable of achieving all of the objectives.” Leibel- Flarsheim Co., 358 F.3d at 908. Of course, including some touted advantages and not others (or preferred embodiments) as inferential claim limitations would lead to absurd results and eviscerate the meaning of claim terms. (See e.g., Micron Resp. Br. 10 (“If Rambus is correct that disclosed benefits limit the claims, then at least the following features must be read into the claims: the package layout and bus dimensions (id. at 4:36-44; the stub capacitances and inductances (id. at 4:44-46); having pins on only one side of the chip (id. at 4:47-48); clock averaging circuit (id. at 22:50-23:12); etc.” ).) And following Rambus’s logic, the claimed memory devices would Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 18 have to be limited to the preferred DRAM embodiments, and not include ROMs and other chip memory devices. Second, Rambus’s opening Brief arguments do not address the memory stick embodiment disclosed in the ‘184 patent at Figure 9. (See D6- D8). The Examiner correctly finds that the ‘184 disclosed memory stick is a memory device (even though it may comprises several memory devices on it) according to the ‘184 patent. (See Ans. 52 (citing the ‘184 patent, col. 20, ll. 5-14, 62, 67-68 (noting Figure 9 shows a memory device).) Rambus does not direct attention to testimony by their experts about this finding or the Figure 9 embodiment. It follows that any proffered expert opinions as to the meaning of “memory device” based on the ‘184 patent disclosure lack in probative value. (Our prior ‘1178 decision mentioned supra also discusses a corresponding Figure 9 memory stick embodiment in a related Rambus patent and relies on it to support the finding that the term “memory device” is not limited to a single chip.) Third, Respondent’s arguments bolster the fact that a memory device is not limited to a single chip by referencing other instances in the ‘184 patent where the word “device” is not necessarily limited to a single chip. (See e.g., Micron Resp. Br. 9-10 (“Instead, the patent explains that multi-chip devices, include[e] an ‘I/O device, disk controller or other special purpose device such as a high speed switch’.”)(quoting the ‘184 patent, col. 3, ll. 63-65); accord D5.) Rambus responds by arguing that Micron does not show that these devices are multi-chip devices. (P.O. Reb. Br. 6 n. 7.) Such an argument fails to even deny that they are multi-chip devices. At the least, no clear disavowal in the Specification emerges as required under the cases cited supra. Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 19 Fourth, one of the touted features includes operating “the memory device synchronously.” (184’ patent Abstract.) Rambus concurs, arguing as follows: “Claim 1 is directed to a method of controlling a new kind of memory. . . . Memory devices that operate synchronously, unlike asynchronous memory devices . . . .” (P.O. App. Br. 8.) Rambus touts other “disclosed” features that “enable many improvements . . . , greatly increasing the efficiency of data storage and retrieval. The claims at issue in this appeal recite a memory device with some of these features, including block size information, a delay locked loop, and double data rate.” (P.O. App. Br. 8-9 (emphasis added).) In other words, as the ‘184 patent plainly states, and as Rambus argues, the ‘184 patent’s disclosed memory devices can include all the features of prior art memory boards and also can include other claimed features such as synchronous operation, block size information, a delay locked loop, and double data rate, and also other disclosed features (see D4 (describing memory device functions); D10 (describing system features required for speed)). Therefore, it makes sense, contrary to Rambus’s arguments, to describe the disclosed memory devices as including prior art circuit board functions, as well as other claimed or unclaimed features, like synchronous operation, especially in light of the disclosed memory stick embodiment which can include “master” and “slave” devices (i.e., a circuit board with memory chips, controllers, a transceiver and/or a CPU, etc. (see D5-D8)). In a related argument, Rambus also asserts that the MCU in the iAPX memory module is the sort of memory controller precluded by the district Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 20 court’s findings 11 because it acts “acts as an intelligent memory controller” and Rambus discloses such an intelligent memory controller as separate from a memory device. (See P.O Reb. Br. 3-4.) This argument ignores the facts that the ‘184 patent refers to the invention as a complete memory subsystem which includes chip and memory stick embodiments (see D4, D7), that the memory stick embodiment can include a transceiver (a type of controller/interface) (D6, D7), and can include other controllers or other “masters” (on the circuit board) (D6, D7, D8), such as a DMA controller or CPU (D5), i.e., that the invention includes all the functionality of prior art memory boards (D4), plus other functions. Also, the iAPX MCU similarly constitutes an interface between the bus and memory. (A2.) In rebuttal, Rambus argues that the memory stick embodiment is an alternate embodiment, and is not disclosed as a memory device and as including a controller. (See P.O. Reb. Br. 5-6, 8-9). These arguments lack merit for reasons just discussed and for the following additional reasons. The ‘184 patent describes the memory stick as being attached to the transceiver bus (D6, D7) and also refers sending the Trncvrw signal “to all devices [i.e., including memory sticks] on the transceiver bus” 65, thereby indicating “valid data to a slave” (D7) (which may be on the memory stick primary bus or on the transceiver bus). (See D7, D8). And after referring to 11 See Order Clarifying the Court’s Construction of Memory Device, No C- 05-00334 RMW (N.D. Cal. Nov. 21, 2008) (attached to App. Br. App’x as Ex. I-2) (In related litigation involving the same “memory device” term in dispute here in related Rambus patents claiming priority to the same underlying application (07/510,898) as the patent here, the court defined “memory device.”). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 21 “memory devices on the transceiver bus as well as on primary bus units,” the 184 patent states that “[i]n general, each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices on an attached primary bus unit.” (D7.) In other words, the sentence indicates that, in general, a memory device can comprise, inter alia, other memory devices (which are distinct form “[o]ther devices, generically . . . peripheral devices” according to the immediately following sentence). (D7.) Accord Mangosoft, Inc. v. Oracle Corp., 525 F.3d 1327, 1331 (Fed. Cir. 2008) (“‘the persistent memory device will be understood to include a plurality of local persistent memory devices’”) (quoting U.S. Pat. No. 6,148,377). 12 With respect to the argument that the ‘184 patent’s memory devices do not have a controller (see P.O. Reb. Br. 4 n.5), Rambus notes that “the masters or controllers are ‘situated on the transceiver bus [65]’” (P.O. Reb. Br. 5) - in other words, off the memory stick. But in general, masters or controllers can be “on the transceiver bus as well as on primary bus units” - (D7) i.e., off or on the memory stick (D6, D7, D8), and in any event, the transceiver device on the memory stick also has control functions. 12 As a similar example of a device including other devices, a “dynamic random access memory (DRAM),” which Rambus contends is a memory device, includes several devices by at least one definition: “A volatile store in which the fundamental storage devices are capacitors arranged in matrix formation. Associated with each capacitor are field-effect . . . .” Newnes Dictionary of Electronics (1999) avail. at http://www.credoreference.com/entry/bhelec/dynamic_random_access_mem ory_dram (emphasis added). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 22 Rambus’s related argument that original claim 13, and another similar Rambus claim, separately reciting a transceiver device and a memory device, support a distinction between a memory device and a memory stick (which includes a transceiver device on it - see D7) , is not persuasive because a memory stick is not defined or recited in those claims. (See P.O. Reb. Br. 5-6 n. 6.) And even if “memory device” and “memory stick” were separately recited in a combination claim sufficiently to show a distinction between the two in such a claim, any distinction there would not flow to a broader claim such as claim 1 here where recitation of a memory device embraces both disclosed embodiments for that memory device, the chip and stick embodiments. To the extent that claim 13 requires a separate memory controller (claim 13 recites a master), the Examiner equates the iAPX BIU (Bus Interface Unit) with the ‘184 patent’s memory controller, reasoning that the iAPX memory module, including the MCU and DRAM chips, responds to the external BIU in a fashion similar to the response by the ‘184 patent’s disclosed memory devices to its disclosed external controllers/masters. (Ans. 61.) The Examiner’s rationale is sound since the claims fail to demarcate included or precluded MCU or BIU functions and the disclosed memory devices include all the functionality of prior art memory boards as discussed supra. (Implicitly, the transceivers and/or masters on the memory stick typically have more control functions than the DRAM interfaces, but even DRAM interface circuits require certain control functions. (See D4, D10).) And the iAPX’s memory module is similar to the ‘184 patent’s memory devices as follows: they each have predefined areas, connect to a Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 23 bus to respond to bus controller/master memory commands, and constitute autonomous units (i.e., subsystems which can be removed without affecting other such subsystems). (Compare A1-A3 with D4-D6; accord Ans. 61-62; 68.) Moreover, similar to the ‘184 memory device interface (see D9), including the transceiver (an interface for the memory stick) (see D7), the iAPX MCU also “interfaces memory storage arrays to the memory bus” (A2). Rambus’s assertion that the number of 40 or so chips of the iAPX module are “orders of magnitude” greater than the number of chips disclosed in the ‘184 patent’s memory devices or allocated to the term by the district court (P.O. App. Br. 16-17) fails to take into account that the ‘184 patent’s disclosed memory device subsystems can include from at least three devices, with the memory stick contemplating up to about thirty-two devices. (See Ans. 62, 67-68, 78; D6; D7; D10.) And as noted supra (see note 6), in a related Rambus patent having substantially the same original disclosure as the ‘184 patent, the Federal Circuit defined “the term ‘integrated circuit device’ [under] its ordinary meaning . . . as a ‘circuit constructed on a single monolithic substrate, commonly called a ‘chip.’” Infineon, 318 F.3d at 1091 (trade dictionaries and other citations omitted). While an integrated circuit device constitutes a chip by its ordinary meaning under Infineon, Rambus has not shown a memory device to have the same ordinary meaning (or a special meaning). And similarly, in a related reexamination proceeding (App. No. 2011- 013706, Reexamination Control No. 90/010,574), Rambus maintains that a “synchronous semiconductor memory device” constitutes a single chip - implying a broader meaning here for a memory device. Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 24 With respect to the prosecution history involving the related Rambus ‘918 patent, Rambus points out that they “submitted that the ‘memory devices or memory modules employed in Jackson do not receive the clock signal nor do they provide data synchronously with respect to that clock signal.’” (P.O. App. Brief 24-25.) This sentence, on its face, does not distinguish, but rather equates, a memory device with a memory module. Rambus’s argument that the memory module in Jackson does not provide synchronous data implies that if it does, the claims to a memory device would not have been allowable over such a module. 13 Rambus’s prosecution history arguments pertaining to the related Rambus ‘804 patent are equally unavailing. During prosecution thereof, the examiner amended one set of claims to include a “packet” and another set by changing “memory device” to “integrated circuit device.” (See ‘804 patent file, Notice of Allowability (with Examiner’s Amendment) (May 5, 1999; accord Micron Resp. Br. 13-14).) Despite Rambus’s arguments here to the 13 As explained further in the prior BPAI ‘1178 decision: But as the Examiner points out, the iAPX system at issue here, like the system in Jackson, also employs a BIU which is external to the iAPX memory module, and the Examiner here is not relying on the separate BIU as part of the claimed memory device - contrary to what the examiner relied upon (i.e., the separate Jackson BIU) during the underlying ‘918 patent prosecution. (Ans. 35 (“As acknowledged by the Patent Owner, a device outside of the memory module was relied upon [during the underlying patent prosecution] (i.e., the BIU). The Examiner agrees that a BIU is not part of a memory module and . . . it does not meet the Examiner’s interpretation of memory device.”).) (‘1178 BPAI Dec. 27.) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 25 contrary (P.O. App. Br. 27), whatever Rambus argued during prosecution, these examiner’s amendments made after Rambus’s arguments signify that the examiner was not persuaded by Rambus’s prosecution arguments, but rather, allowed the claims for reasons related to the examiner’s amendments. And those examiner’s amendments implicitly demonstrate that the examiner considered “memory device” to be broader than an “integrated circuit device” (which comports with Infineon’s holding indicating the latter is a chip as discussed supra). (Accord Ans. 74-76 (discussing examiner amendments, reasons for allowance, and differences between “memory” and “integrated circuit”); Micron Resp. Br. 13 (reasoning that the Examiner allowed claims based on amendments - signifying disagreement with any of Rambus’s argued distinctions).) Further, setting aside the examiner’s amendments for a moment, Rambus did not argue clearly or specifically during prosecution that the ‘804 patent claims were allowable because a memory card or module in Weymouth is not a memory device. For example, Rambus summed its argued reasons as follows: In sum, although Weymouth describes a technique for assigning identification numbers to interface cards or boards, Weymouth neither teaches nor suggests: (1) a memory device (or integrated circuit having memory) which includes an internal device identification register; or (2) comparison circuitry to determine whether the identification information in a read request corresponds to the identification value stored in the internal register in the memory devices; and/or (3) a memory device which corresponds to requests when the identification information corresponds to the identification value. (Supp. Pre. Amend. 16 (Feb. 3, 1999). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 26 As the above passage shows, like others advanced during prosecution (see P.O. App. Br. 27 (quoting other Weymouth distinguishing arguments)), Rambus relied on several arguments for patentability of the ‘804 claims. Many of the arguments mention an internal identification register of a memory device (and include other functional limitations) - implicitly signifying a register internal to a memory device or integrated device - as opposed to a register somewhere on a card but not “internal” to the card or module, for example. In other words, Rambus did not focus on a distinction between a device and a module in isolation. Based on the foregoing discussion, the intrinsic and extrinsic evidence shows that Rambus did not clearly limit the term “memory device” to a single memory chip device. Under analogous circumstances involving the related Rambus ‘918 patent, Infineon held that the ordinary term “bus” could not be read restrictively as a “multiplexed bus” even though Rambus described the “present invention” in terms of a “multiplexed bus” in isolated portions of the specification because “the remainder of the specification and the prosecution history shows that Rambus did not clearly disclaim or disavow such claim scope in this case.” Infineon, 318 F.3d at 1094-95 (emphasis added). Therefore, Rambus has not shown that the Examiner erred by finding and concluding that iAPX anticipates claims 1-10, 13, 15, 16, 18, 19, and 21. Obviousness With respect to the obviousness rejection of representative claims 11, 12, 14, 17, 20, and 23 involving iAPX and Inagaki, Rambus asserts that Inagaki “consistently . . . describ[es] the operation of what it terms ‘clocks,’ [but] Inagaki characterizes them as ‘shift pulses’,” and that “the signal is not Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 27 necessarily an ‘external clock signal’,” nor is it periodic. (P.O. App. Br. 40- 41.) Rambus’s assertions fail to demonstrate error in the combination. 14 Inagaki consistently discloses a clock as Rambus acknowledges. (Accord I1-I3). Moreover, Inagaki discloses creating clock signals from an external clock, i.e., “performing I/O [input/output] of data on every half- cycle of the external clock that drives the I/O shift register” (I3) (emphasis added). Rambus’s purported distinction that the claimed external clock “is not a signal that is asserted some of the time and not asserted at other times” (P.O. App. Br. 36) lacks persuasion because it implies the ‘184 patent’s clock is never off. Rambus does not direct attention to a disclosure for that implied argument or present persuasive evidence or argument that such a disclosure limits the clock recited in claims 11 or 23. Moreover, Micron persuasively stresses that whether or not Inagaki discloses an external periodic clock, iAPX teaches external periodic clock pulses and Inagaki teaches using dual edges of such clock pulses in order to increase speed or reduce the number of data paths. (Micron Resp. Br. 16-20 (citing, for example, reasons discussed by Inagaki for using dual edges such 14 Rambus presents a different section for claim 23, but primarily relies on arguments presented for claims 11, 12, 14, 17, and 20, and dependent claim 13 discussed supra with claim 1. (See P.O. App. Br. 46-47.) Rambus’s arguments that Inagaki does not suggest the limitations of claim 23 because Inagaki does not disclose or suggest an internal and external clock (id.) lacks merit where Rambus fails to define “internal” and “external,” and in any case, Inagaki discloses or at least suggests an external clock from which internal clock edges are derived. Or, the iAPX clock is external, and it would have been obvious in view of Inagaki to track the edges of that clock “internal” to other hardware. (See I1-I3; Micron Resp. Br. 21; Ans. 92-93.) Therefore, aside from this issue, claims 11, 12, 14, 17, 20, and 23 are treated together based on the arguments presented. Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 28 as improving speed without increasing frequency or widening the bus); BPAI Tr. 27; I1-I3).) 15 The Examiner reasons similarly and further reasons that Inagaki’s clock is periodic when it operates, but in any event, Inagaki suggests improving the speed of the Budde/iAPX external periodic clocks by using both edges thereof. (Ans. 82-85). Increased speed and compactness (by eliminating the bus width and pin number) while saving costs (see I1) constitute universal motivators. Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit motivation to combine exists … when the ‘improvement’ is technology-independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”) Rambus’s arguments that the iAPX devices would have been too slow to accept increased speed, the modification would have been too complicated, and other arguments for unobviousness, ignore those universal motivators. (See P.O. Br. 41-46.) Skilled artisans at the time of the invention expected and pushed for higher speeds (see I1), reduced bus sizes would have been desirable simply to minimize parts (id.), and even if the iAPX (modified) components (e.g., integrated DRAMS based on iRAM) could not have handled faster speeds prior to the invention, the iAPX system could have benefitted, at the time of the invention, from a slower clock’s 15 Micron’s counsel at oral argument explained that using a fewer number of bus lines would be possible because a 16 bit word could be clocked twice on an 8 bit bus instead of once on a 16 bit bus with the slower clock. (See BPAI Tr. 40-41; accord I1.) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 29 dual pulses to double speed as a mere substitute to a faster clock, as Inagaki teaches (see I1-I3). See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Rambus’s argument that the proposed modification would render the iAPX system inoperable because it uses two clocks to handle data transfers, such that doubling one clock would disrupt operations controlled by the other (see P.O. App. Br. 42-43), ignores the substitution rationale just discussed and another commonsensical solution of simply using both edges of both clocks - i.e., doubling clock rates for the both clocks, or modifying the response of one of the clocks. (See Micron Resp. Br. 18-19; BPAI Tr. 28-30.) Rambus also asserts that the iAPX designers “knew that they could use both edges of a clock signal” (P.O. App. Br. 43) and did so for another purpose, thereby teaching away from using both edges for data transfer. (See id. at 42-43.) To the contrary, teaching an alternative solution does not necessarily, without more, discourage or discredit the use of dual edges, or teach away, as Respondent and the Examiner persuasively maintain. (See ‘184 RAN 76-78; Micron Resp. Br. 19 n.9.) Rambus’s related arguments about existing device limitations based on speed (see P.O. App. Br. 44-45 (discussing 10 MHz operation)) fail to account for the mere substitution of a slower clock producing the same speed (by using its dual edges) or for the fact that as memory devices became faster, of course, faster speeds would have been universally desired, if not required. Rambus presents several other arguments (see P.O. Br. 35-47) that fail to demonstrate Examiner error. The Examiner’s findings and rationale (see Ans. 82-93) and Micron’s similar responses (see Micron Resp. Br. 15-21) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 30 are more persuasive than Rambus’s arguments. Based on the foregoing discussion, Rambus failed to show error in the obviousness rejection of claims 11, 12, 14, 17, 20, and 23 based on iAPX and Inagaki. With respect to the obviousness rejection of claim 22 based on iAPX and Lofgren, Rambus relies on inter alia, ‘184 patent’s Figure 12 to support the delay lock loop (DLL) recited in the claim. (See P.O. App. Br. 10.) Rambus describes the DLL as “circuitry, including a variable delay line, that uses feedback . . . to generate a signal having a controlled timing relationship relative to another signal.” (Id.) Micron points out that Rambus also states that Figure 12 supports a phase locked loop (PLL). Micron further contends that Rambus has introduced confusion about the difference between the two types of circuits (DLL and PLL) by prosecuting claims to both DLL and PLL based on the same Figure 12. (See Micron Resp. Br. 21- 22 (citations omitted).) The Examiner finds that inventor Farmwald has testified to the effect that the PLL and DLL circuits are essentially the same. (Ans. 94 (citing RAN at 49).) 16 The Examiner also finds that Lofgren discloses a delay line which produces “accurate” [internally clocked] delays” in an analogous fashion to a PLL. (See Ans. 94 (quoting Lofgren at col. 1, ll. 31-32 and 50- 54; citing Fig. 1; accord Resp. Br. 22).) The Examiner also finds that Lofgren discloses providing an accurate timer using a delay line 16 The Examiner cites “Exhibit F, Farmwald testimony March 20, 2008 Conduct Trial Tr. at 5519:15-22 and 5520:8-12” and finds that inventor Farmwald stated that a PLL and DLL “‘can both be used to accomplish the same thing.’” Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 31 compensating for variances in temperature and voltage. (Ans. 95 (citing Lofgren at col. 1, ll. 75-76).) The record supports the Examiner’s findings and Micron’s contentions. And whether Lofgren’s delay line is characterized as a DLL or PLL is not material here. Rambus’s prosecution arguments, proffered testimony, and characterization of the claimed DLL (see P.O. Br. 9) have, on this record, effectively equated the two or shown them to be mere substitutes for one another for purposes of this proceeding. Such delay loops simply provide finer tuning of clocks in the nature of an internal clock as produced from known external clocks, and would have been an obvious advantage in the iAPX clocked system, as Micron and the Examiner persuasively demonstrate (see Micron Resp. Br. 21-23; Ans. 93-96), contrary to Rambus’s arguments. Such a finely tuned clock known in the art would have been obvious to employ in the iAPX clocked systems simply to provide better timing. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”). Based on the foregoing discussion, Rambus did not show error in the rejection of claim 22. Secondary Considerations Rambus alleges secondary considerations of long-felt need, failure of others, skepticism, commercial success, and praise by others, as rebuttal to the obviousness finding by the Examiner “regarding claims 11, 12, 14, 17, 20, 22, and 23.” (P.O. App. Br. 64.) Rambus does specify which of these claims relate to these secondary considerations. Two representative claims rejected for obviousness, dependent claims 14 and 22, respectively include Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 32 limitations pertaining respectively to a method of using the rising and falling edges of a clock signal and a delay locked loop (with the method recited in independent claim 13). Rambus appears to focus on these features (and others in the independent claims as noted below). (See P.O. App. Br. 64, 65.) As such, claims 14 and 22 are deemed representative. Rambus argues that several features recited in the claims “both individually and in combination” address a long-felt need for higher performance. (P.O. App. Br. 65.) Rambus mentions the use of an external clock, block size information (both recited in claims 1 and 13 rejected for anticipation), the transfer of data with respect to both the rising and falling edges (e.g., claims 11 and 14), and a delay locked loop (e.g. claim 22). (See P.O. App. Br. 65.) Based on Rambus’s arguments, part of any alleged solution for long- felt need, the use of external clocks and block sized data, was not novel based on the anticipation of claims 1 and 13 by the iAPX Manual. As such, Rambus has not established a nexus between the claims and any alleged solution to a long-felt need. See Tokai Corp. v. Easton Enters., Inc., 632 F.3d 1358, 1369 (Fed. Cir. 2011) (“If commercial success is due to an element in the prior art, no nexus exists.”); Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299, 1312 (Fed. Cir. 2006) (“[I]f the feature that creates the commercial success was known in the prior art, the success is not pertinent.”). In a similar vein, Micron and the Examiner also contend that Rambus did not first invent synchronous chip devices. (See Micron Resp. Br. 30-31 (citing the Bennett patent and Intel MCS-4 Micro Computer Set); accord Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 33 Ans. 104).) 17 This contention similarly shows a lack of nexus since part of any alleged success was based on features already existing in the prior art. Rambus does not directly refute that contention and simply argues that “none of the prior art references asserted by the Examiner and Micron disclose a ‘memory device’ that receives an ‘external clock signal’.” (P.O. Reb. Br. 20 (citing Ans. at 104, Micron Resp. Br. at 30-31).) Rambus’s argument, a general denial at best, simply fails to rebut the findings by the Examiner and contentions of Respondent. Rambus also urges that Dr. Farmwald recognized that the speed problem “would become more acute over time.” See P.O. Reb. Br. 20 (citing Ex. E-5.) 18 However, according to Dr. Farmwald, “even up into the early part of the ‘90s, it [speed] wasn’t going to be a big problem.” (RMW Tr. at 267). The effective priority date for the ‘184 patent is in early 1990 so that there was no “big [speed] problem” at the time of filing. Hence, as Micron and the Examiner maintain (Micron Resp. Br. 30; Ans. 104 (both citing Pentec, Inc. v. Graphic Controls Corp., 776 F.2d 309, 316 (Fed. Cir. 1985) (long-felt need is not established in short time frames)), any predicted future problem does not constitute a long-felt problem. Similarly, the alleged failure of others to solve a mid-1990’s speed problem does not speak 17 The Examiner similarly points to an Intel MCS-4 Intel 4002 synchronous DRAM as a 1971 prior art “320 bit RAM controlled by two external clock signals.” (Ans. 53 (pointing to the Intel document as cited by Rambus in an IDS).) It does not appear that Rambus disputes this finding. 18 Ex. E-5 (attached to P.O. App. Br., C-00-20905 RMW Trial Transcript 146-149, 270-281, Dist. Ct. Cal. (Mar. 16, 2006) (Dr. Farmwald testimony)) (hereinafter “RMW Tr.”). Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 34 to common solutions at the time of effective filing, 1990. (See P.O. App. Br. 65.) And Dr. Farmwald’s testimony indicates that one apparent solution (i.e., not necessarily his) was simply to employ large numbers of DRAMs, but that solution would be expensive. (RMW Tr. 274-275 (see note 18).) Dr. Farmwald testifies he conceptualized a 500 MHz (high speed) solution before 1990 that would address this future (1994-95) speed problem in part by using smaller devices and eight data lines in a DRAM (more data lines are like more cars on a freeway) with a trade-off in cost and power lines as the number of data lines increase. (Id. at 276-282) Based on this observation, Dr. Farmwald characterizes the eight data lines as “just a trade- off we made for cost reasons.” (Id. at 280.) So even if there was a long-felt unsolved need in early 1990, the claims at issue here do not require Dr. Farmwald’s specifically touted solution of a set speed, size, or number of data lines, or DRAMs, let alone a limited number of DRAMs. And Dr. Farmwald’s testimony indicates that a known or (obvious but expensive) solution to the immediate 1990’s problem involved simply using more DRAMs (id. at 276), a solution not precluded by the claims at issue here (or the iAPX module). His testimony also shows that the solution incorporated market factors (a reduced number of DRAMs and data lines) but not necessarily technical challenges in terms of modifying the iAPX module. This market-based solution also fails to show unobviousness. Also, Rambus has not established that any commercial success is commensurate in scope with the broad reach of the claims. (RAN 122 (citing Application of Tiffin, 448 F.2d 791 (CCPA 1971) for the proposition Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 35 that commercial success evidence of thermoplastic foam cups is not commensurate in scope with broad claims directed to thermoplastic foam containers).) The Examiner’s Tiffin based rationale is persuasive because even if Rambus’s evidence does point to the unobviousness of using delay locked loops or dual internal clock edges inside of DRAMS, the proffered evidence does not rebut the obviousness of using these known features with a broadly claimed memory device such as the iAPX memory module. Rambus also alleges “significant sales of products embodying the claimed invention” and proffers licensing evidence for the “Farmwald Family.” (P.O. App. Br. 67.) But Rambus does not point the Board to the evidence of these sales and it is well established that competitors have many reasons for taking licenses which are not necessarily related to unobviousness (i.e., litigation costs, etc.). Also, the Examiner finds that the licenses pertain to DRAMs (Ans. 105), a finding Rambus does not dispute (see P.O. App. Br. 67; P.O. Reb. Br. 20-21). Claims 14 and 22 neither require nor are limited to DRAMs. Therefore, the proffered licensing evidence is not commensurate in scope with the claims and the proffered sales evidence lacks support (or a showing of nexus). Rambus also proffers other evidence related to the commercial success of double data rate DRAM s (produced by competitors Micron, Samsung, and Hynix) and evidence of praise for Dr. Horowitz, as a pioneer in high bandwidth memory-interface technology. (See (P.O. App. Br. 67- 69; P.O. Reb. Br. 20-21.) Rambus adds, as evidence of skepticism, that “‘it Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 36 was felt that . . . one could not put a phase locked loop or a delay locked loop on the DRAM itself.’” (P.O. App. Br. 66.) 19 But similar to the above discussion, as the Examiner reasons, the memory devices rejected for obviousness do not require DRAMs (RAN 121- 122; Ans. 105), let alone DRAMs with either phase or delay locked loops, or high bandwidth. It follows that the proffered evidence of praise, skepticism, and commercial success is not commensurate in scope with the claims. (See Ans. 105.) Also, the FTC decision relied upon by Rambus (supra note 19) does not clearly indicate a technical challenge: “For example, it was felt that putting registers on a DRAM was too expensive for a commodity part and that one could not put a phase locked loop or a delay locked loop [DLL] on the DRAM itself.” (FTC Init. Dec. at 22, ¶ 105 (see supra note 19).) Without a showing of a technical challenge related to the DLL of claim 22, and since the claims do not even require a DLL in a memory device, let alone a DRAM, Rambus fails to show unobviousness. In general, besides DRAMs, DRAMs having an internal DLL, eight data lines, and the small sizes discussed supra, the ‘184 patent and evidence of record reveal that numerous other unclaimed features are touted in support of the DRAM speeds alleged to have been conceptualized as an inventive solution before 1990. Some of these required but unclaimed features include multiplexed buses, packetized control, identification control 19 Quoting “(Ex. G-3 at 22, ¶ 105)” which is an attached FTC Initial Decision, In the Matter of Ramus Inc., A Corporation, (Docket No. 9302) (Feb. 23, 2004). The FTC Decision cites what appears to be testimony by inventor Horowitz. (See id. at 22, ¶ 105.) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 37 mechanisms, doubly terminated clocks, and time access schemes. (D4, D10.) 20 As such, the proffered evidence of success is 1) not commensurate in scope with the broad claims because they do not require these unclaimed features, and 2) lacks a nexus because any success appears to be due partly to these unclaimed features. Weak secondary considerations generally do not overcome a strong prima facie case of obviousness. See Media Techs. Licensing, LLC v. Upper Deck Co., 596 F.3d 1334 (Fed. Cir. 2010), cert. denied, 2010 WL 2897876 (Oct. 04, 2010) (“Even if [the patentee] could establish the required nexus, a highly successful product alone would not overcome the strong showing of obviousness.”). Rambus’s proffered secondary considerations fail to outweigh the evidence and rationale of record for combining known prior art DLL and dual edge clock features with known memory device methods to yield predictable results as set forth in the method claims at issue here. Non-Adopted Rejections and other Contentions Affirmance of the above-discussed anticipation and obviousness rejections for claims 1-23 renders it unnecessary to reach the propriety of the Examiner’s decision to refuse to adopt Requestor’s remaining proposed rejections, or to decide the adopted rejections based on Novak or Budde. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding anticipation). 20 See Infineon, 318 F.3d at 1095 (“the prosecution history shows that a [high speed] multiplexing bus [in related Rambus patents] is only one of many inventions disclosed in the ‘898 application”) Appeal 2011-008431 Reexamination Control 95/000,183 & 95/001,112 Patent 6,182,184 38 CONCLUSION Rambus did not demonstrate that the Examiner erred in deciding that iAPX anticipates claims 1-10, 13, 15, 16, 18, 19, and 21; APX and Inagaki, render obvious claims 11, 12, 14, 17, 20, and 23; and that iAPX, Inagaki, and Lofgren render claim 22 obvious. DECISION The Examiner’s decision to reject appealed claims 1-23 is affirmed. Requests for extensions of time in this inter partes reexamination proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79. AFFIRMED ak Finnegan, Henderson, Farabow, Garrett & Dunner, LLP 901 New York Avenue, NW Washington, DC 20001 Third Party Requester: Haynes and Boone, LLP IP Section 2323 Victory Avenue Suite 700 Dallas, TX 75219