EMC Corporationv.ACQIS LLC

Patent Trial and Appeal Board

Mar 8, 2016

12322858 (P.T.A.B. Mar. 8, 2016)

Trials@uspto.gov Paper 56
571–272–7822 Entered: March 8, 2016

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

EMC CORPORATION,
Petitioner,

v.

ACQIS LLC,
Patent Owner.
_______________

Case IPR2014-01469
Patent RE42,814 E
_______________

Before MICHAEL P. TIERNEY, MICHAEL J. FITZPATRICK, and
ROBERT J. WEINSCHENK, Administrative Patent Judges.

WEINSCHENK, Administrative Patent Judge.

FINAL WRITTEN DECISION
35 U.S.C. § 318(a) and 37 C.F.R. § 42.73

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I. INTRODUCTION
EMC Corporation (“Petitioner”) filed a Petition (Paper 2, “Pet.”)
requesting an inter partes review of claims 24 and 31–33 of U.S. Patent No.
RE42,814 E (Ex. 1001, “the ’814 patent”). ACQIS LLC (“Patent Owner”)
filed a Preliminary Response (Paper 7, “Prelim. Resp.”) to the Petition. On
March 11, 2015, we instituted an inter partes review of claims 24 and 31–33
(“the challenged claims”) of the ’814 patent on the following grounds:
Claim(s) Statutory Basis Applied References(s)
24 and 31–33 35 U.S.C. § 103(a) Robert W. Horst, TNet: A Reliable
System Area Network (Feb. 1995)
(Ex. 1009, “Horst”); U.S. Patent No.
6,012,145 (issued Jan. 4, 2000) (Ex.
1014, “Mathers”); and National
Semiconductor, LVDS Owner’s
Manual: Design Guide (Spring 1997)
(Ex. 1019, “LVDS Owner’s
Manual”)
31–33 35 U.S.C. § 103(a) A. Bogaerts et al., RD24 Status
Report: Application of the Scalable
Coherent Interface to Data
Acquisition at LHC (Oct. 1996) (Ex.
1011, “Bogaerts”); U.S. Patent No.
6,148,357 (issued Nov. 14, 2000)
(Ex. 1010, “Gulick”); Mathers; and
U.S. Patent No. 5,961,623 (issued
Oct. 5, 1999) (Ex. 1018, “James”)
Paper 11 (“Dec. on Inst.”), 23.
After institution, Patent Owner filed a Response (Paper 25, “PO
Resp.”) to the Petition, Petitioner filed a Reply (Paper 37, “Pet. Reply”) to
the Response, and Patent Owner filed a Surreply (Paper 49, “PO Surreply”).1

1 We authorized Patent Owner to file a surreply. Paper 42, 3.
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An oral hearing was held on December 8, 2015, and a transcript of the
hearing is included in the record. Paper 55 (“Tr.”).
We issue this Final Written Decision pursuant to 35 U.S.C. § 318(a)
and 37 C.F.R. § 42.73. For the reasons set forth below, Petitioner has not
shown by a preponderance of the evidence that claims 24 and 31–33 of the
’814 patent are unpatentable.
A. Related Proceedings
The parties indicate that the ’814 patent is at issue in the following
district court cases: ACQIS LLC v. Alcatel-Lucent USA, Inc., No. 6:13-cv-
00638 (E.D. Tex.); ACQIS LLC v. EMC Corp., No. 6:13-cv-00639 (E.D.
Tex.); ACQIS LLC v. Ericsson, Inc., No. 6:13-cv-00640 (E.D. Tex.); and
ACQIS LLC v. Huawei Technologies Co., No. 6:13-cv-00641 (E.D. Tex.).
Pet. 56; Paper 5, 2.
Petitioner identifies the following petitions for inter partes review as
being related to this case (Pet. 57):
Case No. Involved U.S. Patent No.
IPR2014-01452 RE43,171 E
IPR2014-01462 8,041,873 B2
B. The ’814 Patent
A typical computer system includes various components, such as a
central processing unit (“CPU”), memory, and peripheral devices (e.g., a
printer). Ex. 1001, col. 1, l. 50–col. 2, l. 7; Ex. 2021 ¶ 43. These
components often are connected to one another using buses. Ex. 1003 ¶¶ 25,
26; Ex. 2021 ¶¶ 43, 44. A bus can be parallel or serial. Ex. 1003 ¶¶ 25, 26;
Ex. 2021 ¶¶ 54, 56. A parallel bus transmits all the bits in a word at one
time. Ex. 1003 ¶ 25; Ex. 2021 ¶ 54. For example, to communicate a 32-bit
word, a parallel bus would have 32 lines so that it can transmit all the bits in
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the 32-bit word at one time. Ex. 1003 ¶ 25; Ex. 2021 ¶ 54. A serial bus, on
the other hand, does not transmit all the bits in a word at one time. Ex. 1003
¶¶ 26, 27; Ex. 2021 ¶ 56. For example, to communicate a 32-bit word, a
serial bus would have fewer than 32 lines. Ex. 1003 ¶ 27; Ex. 2021 ¶ 56.
The ’814 patent is a reissue of U.S. Patent No. 6,321,335 (“the ’335
patent”). See Ex. 1001. The reissue application that issued as the ’814
patent added Figures 8–18, the written description at column 11, line 49 to
column 25, line 51, and claims 24–53. Id. at col. 4, ll. 35–58, col. 11, l. 49–
col. 32, l. 50. The figures, written description, and claims added during
reissue relate to, inter alia, interfacing two Peripheral Component
Interconnect (“PCI”) buses. Id. at col. 19, ll. 31–33, Fig. 11.
According to the ’814 patent, prior systems for interfacing two PCI
buses used parallel connectors. Id. at col. 19, ll. 48–52, col. 19, ll. 63–67.
Parallel connectors, however, were bulky and expensive. Id. at col. 19, ll.
56–62. The ’814 patent explains that the system disclosed therein
overcomes these disadvantages by interfacing two PCI buses using a serial
connector. Id. at col. 19, ll. 63–67. Specifically, a PCI bus transaction is
encoded so it can be communicated in serial form over a low voltage
differential signal (“LVDS”) channel, which is smaller, faster, consumes less
power, and generates less noise than the parallel connectors used in prior
systems. Id. at col. 19, ll. 48–62, col. 20, ll. 60–65.
C. Illustrative Claim
Claims 24 and 31 are independent. Claim 24 is reproduced below.
24. A method for operating a computer system, said
method comprising:
inserting an attached computer module (“ACM”) into a
bay of a console in a modular computer system, the console
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comprising a first low voltage differential signal (LVDS)
channel comprising two unidirectional serial channels that
transmit encoded data of Peripheral Component Interconnect
(PCl) bus transaction in opposite directions; said ACM
comprising
a microprocessor unit coupled to a mass memory
storage device;
a north bridge to communicate address and data
bits of PCI bus transaction in serial form, said north
bridge directly coupled to said microprocessor unit;
a main memory coupled to said microprocessor
unit through said north bridge; and
a second LVDS channel comprising two
unidirectional serial channels that transmit data in
opposite directions, said second LVDS channel extending
from said north bridge to convey said address and data
bits of PCI bus transaction in serial form;
applying power to said computer system and said ACM
to execute a security program, said security program being
stored in said mass memory storage device; and
prompting for a user password from a user on a LCD
display coupled to the console.
Id. at col. 27, ll. 18–43.
II. ANALYSIS
A. Claim Construction
The claims of an unexpired patent are interpreted using the broadest
reasonable interpretation in light of the specification of the patent in which
they appear. 37 C.F.R. § 42.100(b); In re Cuozzo Speed Techs., LLC, 793
F.3d 1268, 1278–79 (Fed. Cir. 2015), cert. granted sub nom. Cuozzo Speed
Techs., LLC v. Lee, No. 15-446, 84 U.S.L.W. 3218 (Jan. 15, 2016). In
applying that standard, claim terms generally are given their ordinary and
customary meaning, as would be understood by one of ordinary skill in the
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art in the context of the specification. In re Translogic Tech., Inc., 504 F.3d
1249, 1257 (Fed. Cir. 2007). An applicant may provide a different
definition of the term in the specification with reasonable clarity,
deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
1994). In the absence of such a definition, limitations are not to be read into
the claims from the specification. In re Van Geuns, 988 F.2d 1181, 1184
(Fed. Cir. 1993).
1. Peripheral Component Interconnect (PCI) bus
transaction
Petitioner proposes construing the claim term “Peripheral Component
Interconnect (PCI) bus transaction” to mean “a data signal communication
with an interconnected peripheral component.” Pet. 13. Patent Owner
agrees with the construction in the Decision on Institution that the claim
term “Peripheral Component Interconnect (PCI) bus transaction” means
“Peripheral Component Interconnect (PCI) industry standard bus
transaction.” PO Resp. 21–22. We see no reason now to deviate from the
construction in the Decision on Institution. The evidence indicates that the
term “Peripheral Component Interconnect (PCI) bus transaction” refers to a
particular industry standard, not just any communication with an
interconnected peripheral component.
Industry literature and dictionaries use the proper noun “Peripheral
Component Interconnect” and the abbreviation “PCI” to refer to a particular
industry specification for a local bus. See, e.g., Ex. 2001, 1; Ex. 2002, 6–7;
Ex. 2003, 7–8. The challenged claims recite “Peripheral Component
Interconnect” as a proper noun and abbreviate it as “PCI,” indicating that the
challenged claims use those terms consistent with the understood industry
meaning. Ex. 1001, col. 27, ll. 24–25, col. 28, ll. 35–36; see Azure
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Networks, LLC v. CSR PLC, 771 F.3d 1336, 1348 (Fed. Cir. 2014). The
written description similarly uses the abbreviation “PCI” to refer to a
particular industry standard, and uses the common noun “peripheral bus” to
refer to a generic peripheral bus. Compare Ex. 1001, col. 19, ll. 31–33 (“the
present invention may interface two PCI or PCI-like buses”), with id. at col.
7, ll. 4–6 (“Additionally, the host controller is coupled to a clock control
logic, a configuration signal, and a peripheral bus.”) (emphasis added).
Petitioner and Petitioner’s declarant, Mr. Bruce Young, acknowledge
that the term “Peripheral Component Interconnect (PCI)” refers to an
industry standard. Ex. 1003 ¶ 58; Ex. 2006, 1, 3; Ex. 2031, 16:8–12. The
evidence Petitioner identifies in support of its proposed construction is the
claim construction order issued in ACQIS LLC v. Appro International, Inc.,
No. 6:09-cv-00148 (E.D. Tex. Feb. 3, 2011). Pet. 12–13 (citing Ex. 1013).
In that case, though, the parties did not appear to dispute that the term
“Peripheral Component Interconnect (PCI)” refers to an industry standard.
See Ex. 1013, 7 (“The parties’ primary dispute is whether the term is limited
to the conventional, parallel PCI Local Bus, and, therefore excludes PCI
Express bus architecture and bus transaction protocol.”). Moreover, the
district court subsequently reconsidered its construction and clarified that the
term “PCI bus transaction” refers to a PCI industry standard bus transaction.
Ex. 1030, 8–10.
Therefore, we construe the claim term “Peripheral Component
Interconnect (PCI) bus transaction” to mean “Peripheral Component
Interconnect (PCI) industry standard bus transaction,” and we construe the
claim term “PCI bus transaction” to mean “PCI industry standard bus
transaction.”
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B. Obviousness of Claims 24 and 31–33 Over Horst, Mathers, and
LVDS Owner’s Manual
Petitioner argues that claims 24 and 31–33 would have been obvious
over Horst, Mathers, and LVDS Owner’s Manual. Pet. 59. A claim is
unpatentable as obvious under 35 U.S.C. § 103(a) if the differences between
the claimed subject matter and the prior art are such that the subject matter
as a whole would have been obvious at the time the invention was made to a
person having ordinary skill in the art to which the subject matter pertains.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
obviousness is resolved on the basis of underlying factual determinations,
including: (1) the scope and content of the prior art; (2) any differences
between the claimed subject matter and the prior art; (3) the level of ordinary
skill in the art; and (4) any objective indicia of non-obviousness. Graham v.
John Deere Co., 383 U.S. 1, 17–18 (1966). We have considered the parties’
arguments and supporting evidence, and we determine that Petitioner has not
shown by a preponderance of the evidence that claims 24 and 31–33 would
have been obvious over Horst, Mathers, and LVDS Owner’s Manual.
1. Overview of Horst
Petitioner relies primarily on Horst as teaching the limitations of
independent claims 24 and 31. See Pet. 30–36. Horst describes a new
network called a TNet network, which is a “major departure from traditional
I/O systems.” Ex. 1009, 1. The TNet network “is not a direct replacement
for any existing type of local area network or I/O bus,” but, rather, “is a new
interconnection layer.” Id. Specifically, the TNet network allows hundreds
of CPUs and I/O devices to communicate over TNet links using TNet
transactions. Id. at 1, Figs. 2, 5. Figure 2 of Horst is reproduced below.
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Id. at Fig. 2. Figure 2 of Horst shows a CPU cluster connected to the TNet
network. Id.
Each CPU is connected to the TNet links by a TNet processor
interface that translates a CPU transaction into a TNet transaction. Id. at 6
(describing “Processor interface”), Fig. 7; Ex. 2021 ¶ 94. Each I/O device is
connected to the TNet links by a TNet bus interface that translates a TNet
transaction into a bus transaction for that I/O device. Ex. 1009, 7
(describing “Bus interface”), Fig. 8; Ex. 2021 ¶ 94. Figures 7 and 8 of Horst
are reproduced below.
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Ex. 1009, Figs. 7, 8. Figure 7 of Horst shows a TNet processor interface,
and Figure 8 of Horst shows a TNet bus interface. Id.
2. Address and Data Bits of PCI Bus Transaction in Serial
Form
As discussed above, the ’814 patent explains that prior systems for
interfacing two PCI buses used parallel connectors. Ex. 1001, col. 19, ll.
48–52, col. 19, ll. 63–67. The ’814 patent sought to overcome the
disadvantages associated with using a parallel connector by encoding a PCI
industry standard bus transaction so that it can be communicated on a serial
connector.2 Id. at col. 19, ll. 48–62, col. 20, ll. 60–65; Ex. 1003 ¶ 98. This
feature is reflected in independent claim 24, which recites an “attached
computer module” that comprises “a second LVDS channel comprising two

2 At the time of the ’814 patent, a PCI industry standard bus transaction
included a 32-bit address followed by one or more data phases. Ex. 2001,
25; Ex. 2021 ¶¶ 59, 62.
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unidirectional serial channels that transmit data in opposite directions . . . to
convey said address and data bits of PCI bus transaction in serial form.” Ex.
1001, col. 27, ll. 20–26, col. 27, ll. 34–38. Independent claim 31 similarly
recites an “attached computer module” that comprises “a peripheral
bridge . . . coupled to said second LVDS channel to communicate address
and data bits of PCI bus transaction in serial form over said second LVDS
channel.” Id. at col. 28, ll. 22–28, col. 28, ll. 34–39. Patent Owner argues
that Petitioner has not shown sufficiently that communicating address and
data bits of a PCI industry standard bus transaction in serial form would
have been obvious to a person of ordinary skill in the art. PO Resp. 27–41.
For the reasons discussed below, we agree with Patent Owner.
a. TNet processor interface
In the Petition, Petitioner argues that the TNet processer interface in
Horst outputs address and data bits of a PCI bus transaction in serial form
over the TNet links. Pet. 31–34. Petitioner’s argument is not persuasive.
The TNet processor interface in Horst translates a CPU transaction into a
TNet transaction. Ex. 1009, 5 (“The interface to the destination CPU or I/O
device provides mapping and validation hardware translating this virtual
TNet address to the appropriate physical memory address.”), Figs. 5, 7; Ex.
2021 ¶ 94 (“The TNet Processor Interface generates TNet transactions from
CPU front-side bus transactions.”). The TNet processor interface then
encodes the TNet transaction using an 8B/9B encoder so that it can be output
over the 9-bit serial TNet links. Ex. 1003 ¶¶ 48, 146; Ex. 1009, 3, Figs. 3, 4
(showing “8B/9B encoder”), Table 1; Ex. 2021 ¶ 105. Petitioner does not
identify persuasive evidence indicating that either the CPU transaction or the
TNet transaction is a PCI industry standard bus transaction. Pet. 31–34
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(citing Ex. 1009, 3–8, Figs. 2, 3, 5, 7–9, Table 1; Ex. 1003 ¶¶ 159[24C(i)],
159[24C(iv)], 159[24C(v)], 159[31B(i)], 159[31B(iii)]); Ex. 2021 ¶ 129.
Thus, the evidence identified in the Petition does not indicate that the
information output by the TNet processor interface over the TNet links
includes address and data bits of a PCI industry standard bus transaction in
serial form.
Petitioner points out that, after a TNet transaction is communicated
over the TNet links, a TNet bus interface in the console may use information
in the TNet transaction to create a PCI industry standard bus transaction if a
particular I/O device is connected to a PCI bus. Pet. 31–32 (citing Ex. 1009,
7, Fig. 8). But claims 24 and 31 require more than just communicating
information over serial channels that subsequently might be used in the
console to create a PCI industry standard bus transaction. Claims 24 and 31,
when read in light of the specification, require that the information actually
communicated over the serial channels includes address and data bits of a
PCI industry standard bus transaction in serial form. Ex. 1001, col. 20, ll.
60–65, col. 21, ll. 15–21, col. 27, ll. 34–38, col. 28, ll. 34–39; Ex. 2022,
15:12–16:2, 22:11–16. As discussed above, the evidence identified in the
Petition does not indicate that the information output by the TNet processor
interface over the TNet links includes address and data bits of a PCI industry
standard bus transaction in serial form.
In the Reply, Petitioner argues that the TNet transaction output by the
TNet processor interface includes PCI data bits. Pet. Reply 11. Petitioner
cites to certain portions of the deposition testimony of Patent Owner’s
declarant, Dr. Volker Lindenstruth, as evidence that Patent Owner “does not
dispute that PCI data bits are communicated over TNet links.” Id. (citing
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Ex. 1029, 316:24–317:6). Petitioner’s argument and evidence are not
persuasive. We are not persuaded that the TNet transaction output by the
TNet processor interface includes any data bits of a PCI industry standard
bus transaction because Petitioner does not identify persuasive evidence
indicating that any data bits of a PCI industry standard bus transaction exist
in the CPU, memory, or TNet processor interface. See Pet. Reply 11.
Further, the evidence identified by Petitioner is not an admission by Patent
Owner that a TNet transaction includes PCI data bits. The cited deposition
testimony of Dr. Lindenstruth relates to the teachings of a reference known
as Bogaerts, not the teachings of Horst. Ex. 1029, 312:13–317:19. Even if
the cited deposition testimony did relate to Horst, Dr. Lindenstruth simply
acknowledges that “some data” is communicated, not that PCI data bits are
communicated. Id. at 316:24–317:6.
Petitioner also argues in the Reply that the TNet transaction output by
the TNet processor interface includes PCI address bits. Pet. Reply 11–13.
Petitioner cites to the declaration testimony of its declarant, Mr. Young, as
evidence that the TNet transaction includes PCI address bits. Id. (citing Ex.
1031 ¶¶ 28–33). Mr. Young states that a person of ordinary skill in the art
would have known to place a 32-bit PCI address into the 32-bit TNet address
portion of a TNet transaction or, alternatively, to use typical one-to-one
mapping. Ex. 1031 ¶¶ 30, 32. Petitioner’s argument and evidence are not
persuasive. We are not persuaded that the TNet transaction output by the
TNet processor interface includes any address bits of a PCI industry standard
bus transaction because Petitioner does not identify persuasive evidence
indicating that any address bits of a PCI industry standard bus transaction
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exist in the CPU, memory, or TNet processor interface. See Pet. Reply 11–
13; Ex. 1031 ¶¶ 28–33.
Further, the cited declaration testimony of Mr. Young is not
persuasive because it is inconsistent with the express teachings of Horst.
Horst teaches that a TNet transaction includes a TNet virtual address. Ex.
1009, 5 (“virtual TNet address”), Fig. 5; Ex. 2021 ¶¶ 95, 103. A PCI
industry standard bus transaction, in contrast, includes a PCI physical
address. Ex. 2001, 25; Ex. 2021 ¶¶ 59, 62, 103. Horst teaches that the
physical address of a CPU or I/O device must be translated into a TNet
virtual address. Ex. 1009, 5 (“The interface to the destination CPU or I/O
device provides mapping and validation hardware translating this virtual
TNet address to the appropriate physical memory address.”). Thus, a PCI
physical address cannot simply be placed into the TNet address portion of a
TNet transaction. Id.; Ex. 2021 ¶¶ 103, 134, 135. Horst also teaches that
typical one-to-one mapping is not used for TNet transactions. Ex. 1009, 5
(“Typically, I/O devices use one-to-one mapping, but because TNet node
identifications differ for each I/O bus, each I/O node has its own
independent 32-bit address space.”); Ex. 2021 ¶ 102.
Petitioner also argues in the Reply that claims 24 and 31 do “not
require that a complete PCI bus transaction originate in the ACM (or a
complete PCI bus transaction exist at all)” because claims 24 and 31 only
require “two or more PCI address bits and two or more PCI data bits.” Pet.
Reply 3, 5, 17, 18. Petitioner’s argument is not persuasive. Petitioner does
not explain specifically how it would have been possible to communicate
two address bits and two data bits of a PCI industry standard bus transaction
if the PCI industry standard transaction never existed. See id. Moreover,
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even if we adopted Petitioner’s interpretation of claims 24 and 31,
Petitioner’s argument still is not persuasive. For the reasons discussed
above, Petitioner does not identify persuasive evidence indicating that any
address and data bits of a PCI industry standard bus transaction exist in the
CPU, memory, or TNet processor interface, or that any address and data bits
of a PCI industry standard bus transaction are included in the TNet
transaction output by the TNet processor interface over the TNet links.
b. TNet bus interface
Petitioner also argues that the TNet bus interface outputs address and
data bits of a PCI industry standard bus transaction over the TNet links. Pet.
Reply 18–19 (citing Ex. 1009, 7; Ex. 1031 ¶¶ 38, 39; Ex. 1026, 197:12–
198:25, 199:16–201:24, 202:15–204:6, 214:15–215:10, 217:4–17).
Specifically, Petitioner argues that “the PCI device creates a PCI bus
transaction, which is then serialized to be communicated over the TNet
channel.” Pet. Reply 18. Petitioner’s argument and evidence are not
persuasive. Horst teaches that the TNet bus interface translates an I/O bus
transaction, such as a PCI bus transaction, into a TNet transaction before the
transaction is encoded for serial communication over the TNet links. Ex.
1009, 3, 7, Fig 4 (showing TNet packet data as an input to the 8B/9B
encoder); Ex. 2021 ¶ 105. As a result, the TNet bus interface outputs a TNet
virtual address in serial form, not address bits of a PCI industry standard bus
transaction in serial form. Ex. 2021 ¶¶ 101, 105.
For the reasons discussed above, we determine that Petitioner has not
shown by a preponderance of the evidence that claims 24 and 31 would have
been obvious over Horst, Mathers, and LVDS Owner’s Manual. Because
claims 32 and 33 depend from claim 31, we also determine that Petitioner
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has not shown by a preponderance of the evidence that claims 32 and 33
would have been obvious over Horst, Mathers, and LVDS Owner’s Manual.
C. Obviousness of Claims 24 and 31–33 Over Bogaerts, Gulick,
Mathers, and James
Petitioner argues that claims 31–33 would have been obvious over
Bogaerts, Gulick, Mathers, and James. Pet. 59. Petitioner argues that
Bogaerts was published on October 2, 1996, and, thus, is a prior art printed
publication under 35 U.S.C. § 102(b). Pet. 58. We have considered the
parties’ arguments and supporting evidence, and we determine that
Petitioner has not shown by a preponderance of the evidence that Bogaerts is
a prior art printed publication.
“In order to qualify as a printed publication within the meaning of
§ 102, a reference ‘must have been sufficiently accessible to the public
interested in the art.’” In re Lister, 583 F.3d 1307, 1311 (Fed. Cir. 2009).
“A reference is considered publicly accessible if it was ‘disseminated or
otherwise made available to the extent that persons interested and ordinarily
skilled in the subject matter or art exercising reasonable diligence, can locate
it.’” Id. Petitioner does not argue that Bogaerts was disseminated to any
particular persons. Pet. Reply 21–25; cf. Suffolk Techs., LLC v. AOL Inc.,
752 F.3d 1358, 1365 (Fed. Cir. 2014). Petitioner instead argues that
Bogaerts generally was made available in the CERN3 Library and on the
RD24 project website. Pet. Reply 21–25. Patent Owner argues that
Petitioner has not shown sufficiently that Bogaerts was publicly accessible
prior to the critical date of the ’814 patent. PO Resp. 52–57. For the reasons
discussed below, we agree with Patent Owner.

3 CERN is the European Organization for Nuclear Research.
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1. CERN Library
Petitioner argues that Bogaerts was available in the CERN Library on
October 2, 1996. Pet. Reply 21–22. Specifically, Petitioner points out that
the first page of Bogaerts contains the date “2 October 1996,” the reference
“CERN/LHCC LHCC 96-33,” and a bar code from the CERN Library. Pet.
Reply 21; Ex. 1011, 1. Petitioner also relies on a CERN Document Server
record, created on December 18, 2014, that contains bibliographic
information for Bogaerts, including that it was “Submitted by 2 Oct 1996.”
Pet. Reply 21–22; Ex. 2011, 439.
Patent Owner argues that Petitioner has not shown sufficiently that
Boagerts was available in the CERN Library on October 2, 1996. PO Resp.
52–57. Dr. Lindenstruth, one of the authors of Bogaerts, states that the date
“2 October 1996” on Bogaerts is when it was submitted to the CERN/LHCC
committee, not necessarily when it was available in the CERN Library. Ex.
2021 ¶¶ 170, 171. To corroborate Dr. Lindenstruth’s testimony, Patent
Owner submits a version of Bogaerts that includes the date “2 October
1996” and the reference “CERN/LHCC LHCC 96-33,” but does not include
a bar code from the CERN Library. Ex. 2021 ¶ 173; Ex. 2026, 12.
The evidence identified by Patent Owner indicates that the date “2
October 1996” on Bogaerts is when it was submitted to the CERN/LHCC
committee. Ex. 2021 ¶¶ 170, 171, 173; Ex. 2026, 12. Although it is
possible that Bogaerts was available in the CERN Library at or around the
same time, Petitioner has not shown that by a preponderance of the
evidence. For example, Petitioner does not cite persuasive evidence
indicating that the “Submitted by 2 Oct 1996” entry in the CERN Document
Server record means that Bogaerts was available in the CERN Library on
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that date. Tr. 23:1–12, 25:5–25; Pet. Reply 21–25. In addition, Petitioner
acknowledges that the CERN Document Server record itself was not created
until December 18, 2014. Tr. 25:5–25; Ex. 2011, 439. Therefore, Petitioner
has not shown sufficiently that Bogaerts is a prior art printed publication
based on its availability in the CERN Library.
2. RD24 Project Website
Petitioner argues that Bogaerts was available on the RD24 project
website in 1996. Pet. Reply 22–25. Specifically, the RD24 project website
contained a link to the “RD24 Status Report 1996.” Ex. 2026, 6–7. That
link led to another website that contained a series of eight postscript files,
named “RD2496_1.ps” through “RD2496_8.ps,” which could have been
combined to create Bogaerts. Ex. 2026, 3–5. Petitioner identifies evidence
indicating that the postscript files were available on that website on
November 29, 1996. Pet. Reply 22; Ex. 2026, 1, 5.
Although the evidence indicates that Bogaerts was available as a
collection of postscript files on the RD24 project website in 1996, Petitioner
does not cite persuasive evidence indicating that “persons interested and
ordinarily skilled in the subject matter or art exercising reasonable
diligence” could have located it. Pet. Reply 22–25; see SRI Int’l, Inc. v.
Internet Security Sys., Inc., 511 F.3d 1186, 1194, 1196–97 (Fed. Cir. 2008).
Petitioner argues that the RD24 project website was “well-known” because
two other CERN documents mention the website.4 Pet. Reply 24–25; Ex.
1027, 19; Ex. 1038, 25. Petitioner, however, does not cite persuasive
evidence indicating that either CERN document was disseminated or

4 Petitioner also cites a third document (Ex. 1037), but that document does
not mention the RD24 project website (see id. at 1).
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Patent RE42,814 E

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otherwise made available such that others would have known about or could
have located the RD24 project website based on those two CERN
documents. Pet. Reply 24–25. Further, the two CERN documents identified
by Petitioner are dated March 1, 1997, and January 30, 1998, and evidence
identified by Patent Owner indicates that the Bogaerts postscript files may
no longer have been available on the RD24 project website in 1997 and
1998. Ex. 1027, 1; Ex. 1038, 1; Ex. 2021 ¶ 176. Thus, we are not persuaded
that persons of ordinary skill in the art would have been independently
aware of the RD24 project website at the time Bogaerts was available on that
website. See SRI, 511 F.3d at 1196–97; Blue Calypso, LLC v. Groupon,
Inc., No. 2015-1391, 2016 WL 791107, at *13–14 (Fed. Cir. Mar. 1, 2016);
cf. Voter Verified, Inc. v. Premier Election Solutions, Inc., 698 F.3d 1374,
1380–81 (Fed. Cir. 2012).
In addition, Petitioner does not cite persuasive evidence indicating
that the RD24 project website was indexed by any search engine or database
in 1996 such that a diligent researcher would have been able to locate the
RD24 project website or the Bogaerts postscript files using keyword
searches.5 Tr. 57:8–58:2; Pet. Reply 22–25; see Blue Calypso, 2016 WL
791107, at *13; cf. Lister, 583 F. 3d at 1315–16. Petitioner also does not
cite persuasive evidence indicating that CERN’s website (www.cern.ch)
contained any search functions in 1996 that would have allowed a diligent
researcher to locate the RD24 project website or the Bogaerts postscript
files. Tr. 57:8–58:2; Pet. Reply 22–25; cf. Voter Verified, 698 F.3d at 1381.

5 The Internet Archive is searchable only by website addresses. Ex. 2026, 1.
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Therefore, Petitioner has not shown sufficiently that Bogaerts was publicly
accessible on the RD24 project website.
D. Patent Owner’s Motion to Exclude
Patent Owner filed a Motion to Exclude (Paper 47, “PO Mot.”), to
which Petitioner filed an Opposition (Paper 50), and Patent Owner filed a
Reply (Paper 52). Patent Owner argues that Exhibits 1011, 1027, 1037,
1038, and 2026, and portions of Exhibit 1031 should be excluded. PO Mot.
1, 6, 11, 13. We have considered the parties’ arguments, and, for the reasons
discussed below, Patent Owner’s Motion to Exclude is denied.
1. Exhibit 1011
Exhibit 1011 is Bogaerts. Patent Owner argues that Exhibit 1011
should be excluded for lack of authentication under Fed. R. Evid. 901. PO
Mot. 2–6. Federal Rule of Evidence 901 requires that the proponent produce
evidence sufficient to support a finding that an item is what the proponent
claims it is. Here, Patent Owner does not dispute that Exhibit 1011 is what
Petitioner claims it is, namely a reference entitled “RD24 Status Report:
Application of the Scalable Coherent Interface to Data Acquisition at LHC.”
Id. What Patent Owner disputes is whether Petitioner has shown by a
preponderance of the evidence that Bogaerts is prior art with respect to the
’814 patent. Id. Patent Owner attempts to characterize this dispute as a
question of authentication, arguing that Petitioner has not produced
“evidence that [Exhibit 1011] is a true and correct copy of a publication that
was publicly available as of the date asserted by Petitioner.” Id. at 3. But
this is a question of sufficiency of proof, not admissibility. Therefore, Patent
Owner’s Motion to Exclude Exhibit 1011 is denied.
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2. Exhibit 1031
Exhibit 1031 is the Reply Declaration of Mr. Bruce Young. Patent
Owner argues that paragraphs 6–19, 27–33, and 36–41 of Exhibit 1031
should be excluded as irrelevant and prejudicial because Petitioner relies on
those paragraphs to support improper arguments in the Reply. PO Mot. 11–
15. Petitioner argues in the Reply that the TNet transaction in Horst and the
SCI transaction in Bogaerts include PCI address bits, and that claims 24 and
31 only require communicating two address bits of a PCI bus transaction.
Id. at 12–13. Patent Owner contends that both arguments exceed the scope
of a proper reply, as set forth in 37 C.F.R. § 42.23(b), and that the portions
of Exhibit 1031 that Petitioner relies upon to support those arguments should
be excluded as irrelevant and prejudicial under Fed. R. Evid. 401(b) and
Fed. R. Evid. 403. PO Mot. 13, 15. Patent Owner’s argument is not
persuasive.
Patent Owner argues in the Response that the TNet transaction in
Horst and the SCI transaction in Bogaerts do not include PCI address bits.
PO Resp. 27–33, 43–47. As such, Petitioner’s argument in the Reply that
the TNet transaction in Horst and the SCI transaction in Bogaerts include
PCI address bits is responsive to an argument raised in the Response. See 37
C.F.R. § 42.23(b) (generally permitting a reply to respond to arguments
raised in a response). Patent Owner also argues in the Response that claims
24 and 31 require communicating a 32-bit PCI address. PO Resp. 9–13. As
such, Petitioner’s argument in the Reply that claims 24 and 31 only require
communicating two address bits of a PCI bus transaction is responsive to an
argument raised in the Response. See 37 C.F.R. § 42.23(b). Because we are
not persuaded that the identified arguments in the Reply are improper, the
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premise of Patent Owner’s Motion to Exclude Exhibit 1031 fails. Therefore,
Patent Owner’s Motion to Exclude paragraphs 6–19, 27–33, and 36–41 of
Exhibit 1031 is denied.
3. Exhibits 1027, 1037, and 1038
Exhibit 1027 is a document entitled “SCI implementation study for
LHCb Data Acquisition,” Exhibit 1037 is a document entitled “An Animated
Graphical Simulator for the IEEE 1596 Scalable Coherent Interface With
Real-Time Extensions,” and Exhibit 1038 is a document entitled “Ideas on a
1st level multi-track r-Φ vertex trigger processor.” Patent Owner argues that
Exhibits 1027, 1037, and 1038 should be excluded as irrelevant because they
do not show that Bogaerts is prior art with respect to the ’814 patent. PO
Mot. 9–11. Patent Owner’s argument is not persuasive because it raises a
question of sufficiency of proof, not admissibility. Therefore, Patent
Owner’s Motion to Exclude Exhibits 1027, 1037, and 1038 is denied.
4. Exhibit 2026
Exhibit 2026 was submitted by Patent Owner and is the Affidavit of
Christopher Butler. Patent Owner argues that Exhibit 2026 should be
excluded as irrelevant because it does not show that Bogaerts is prior art
with respect to the ’814 patent. PO Mot. 7–9. Patent Owner’s argument
raises a question of sufficiency of proof, not admissibility. Indeed, Patent
Owner argues that Exhibit 2026 is relevant to whether Petitioner has shown
that Bogaerts is prior art. PO Resp. 52–57. Specifically, as discussed above,
Patent Owner relies on Exhibit 2026 to corroborate Dr. Lindenstruth’s
testimony that the date on Bogaerts is when it was submitted to the
CERN/LHCC committee, not necessarily when it was available in the CERN
Library. See supra Section II.C.1. Therefore, Patent Owner’s Motion to
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Exclude Exhibit 2026 is denied.
E. Patent Owner’s Motion for Observations
Patent Owner filed a Motion for Observation on cross examination
(Paper 46) of Mr. Bruce Young, to which Petitioner filed a Response (Paper
51). We have considered Patent Owner’s observations and Petitioner’s
responses, and we have given Mr. Young’s testimony the appropriate weight
in making our determination in this case.
III. CONCLUSION
Petitioner has not shown by a preponderance of the evidence that
claims 24 and 31–33 of the ’814 patent are unpatentable.
IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that claims 24 and 31–33 of the ’814 patent are not shown
unpatentable;
FURTHER ORDERED that Patent Owner’s Motion to Exclude is
denied; and
FURTHER ORDERED that, because this is a Final Written Decision,
parties to the proceeding seeking judicial review of the decision must
comply with the notice and service requirements of 37 C.F.R. § 90.2.
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Patent RE42,814 E

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PETITIONER:

Brian Buroker
Blair Silver
GIBSON, DUNN & CRUTCHER LLP
bburoker@gibsondunn.com
bsilver@gibsondunn.com

PATENT OWNER:

Wayne Stacy
Britton Davis
Joseph M. Drayton
COOLEY LLP
wstacy@cooley.com
bdavis@cooley.com
ACQIS-IPR@cooley.com