EATON CORPORATION

Patent Trials and Appeals Board

Dec 20, 2021

2020006681 (P.T.A.B. Dec. 20, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/625,230 06/16/2017 Jian JIAO 16-MCB-1253 2359
101730 7590 12/20/2021
ECKERT SEAMANS CHERIN & MELLOTT, LLC
EATON CORPORATION
600 GRANT STREET
44TH FLOOR
PITTSBURGH, PA 15219
EXAMINER
THOMAS, LUCY M
ART UNIT PAPER NUMBER
2836
NOTIFICATION DATE DELIVERY MODE
12/20/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipmail@eckertseamans.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JIAN JIAO and ADONNA ANGELIKA ANDERSON
Appeal 2020-006681
Application 15/625,230
Technology Center 2800
Before LINDA M. GAUDETTE, N. WHITNEY WILSON, and
LILAN REN, Administrative Patent Judges.
GAUDETTE, Administrative Patent Judge.
DECISION ON APPEAL1
The Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision finally rejecting claims 1–20.3
We reverse.

1 The following documents are of record: Specification filed June 16, 2017
(“Spec.”); Final Office Action dated Nov. 1, 2019 (“Final Act.”); Appeal
Brief filed Apr. 3, 2020 (“Appeal Br.”), citations to pages 15–19 are to the
Claims Appendix; Examiner’s Answer dated July 24, 2020 (“Ans.”); and
Reply Brief filed Sept. 24, 2020 (“Reply Br.”).
2 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. The
Appellant identifies the real party in interest as Eaton Intelligent Power
Limited. Appeal Br. 2.
3 We have jurisdiction under 35 U.S.C. § 6(b).
Appeal 2020-006681
Application 15/625,230

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CLAIMED SUBJECT MATTER
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. A circuit interrupter structured to protect a
protected circuit, the circuit interrupter comprising:
a ground fault current sensor structured to sense a ground
fault current in the protected circuit;
a processor including a routine structured to perform a
ground fault output self-test, the ground fault output self-test
including:
to output a trip signal within a predetermined
phase angle of a zero-crossing of current flowing through the
protected circuit;
to stop outputting the trip signal before the zero-
crossing;
to determine whether the trip signal caused a pulse
in the ground fault current; and
to determine whether the circuit interrupter passed
the ground fault output self-test based on whether the trip signal
caused a pulse in the ground fault current.
Appeal Br. 15 (Claims App.).
REJECTIONS
1. Claims 1, 2, 6–12, and 16–204 are rejected under 35 U.S.C.
§102(a)(1) as anticipated by Haines (US 2014/0254050 A1, pub. Sept. 11,
2014). Final Act. 3–7.
2. Claims 3–5 and 13–15 are rejected under 35 U.S.C. § 103 as
unpatentable over Haines. Final Act. 7–9.

4 See Ans. 3; discussion of the status of the rejection of claims 19 and 20
infra.
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OPINION
Before discussing the merits of the rejections, we address the
Appellant’s argument that the Examiner did not properly reject claims 19 and
20. See Appeal Br. 6; Reply Br. 1–2. The Appellant acknowledges that the
Final Office Action Summary lists claims 1–20 as rejected, but argues that
because the Examiner did not include claims 19 and 20 in the statement of the
rejection, the Examiner failed to fully and clearly set forth a ground of
rejection for claims 19 and 20 as required by MPEP § 707.07(d). Appeal Br.
6. The Appellant argues that it requested clarification of the claims rejected in
an Amendment dated September 26, 2019, but the Examiner did not change
the statement of the rejection.
MPEP § 707.07(d) states:
Where a claim is refused for any reason relating to the merits
thereof it should be “rejected” and the ground of rejection fully
and clearly stated, and the word “reject” must be used. The
examiner should designate the statutory basis for any ground of
rejection by express reference to a section of 35 U.S.C. in the
opening sentence of each ground of rejection.
Other than requiring use of the word “reject,” MPEP § 707.07(d)
merely provides guidelines for what an Examiner’s rejection should state. In
any event, we determine that the Examiner followed MPEP § 707.07(d)’s
guidelines. See Ans. 3 (citing Final Act. 7). In particular, the Final Office
Action includes the following language: “Claims 1–2, 6–12, 16–18 are
rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haines.” (Final
Act. 3); “Claims 11–12 . . . recite method steps corresponding to Claims 1–2 .
. . . Therefore, Claims 11–12 . . . are rejected at least for the same reasons as
for Claims 1–2 . . . .” (Final Act. 7); and “Claims 19–20 recite[] a non-
transitory computer readable medium storing . . . instructions, which when
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executed by a computer, cause[] the computer to perform the method of
Claims 11–12) . . . . Haines discloses . . . a non-transitory computer readable
medium including the instruction. Therefore Claims 19–20 are rejected at
least for the same reasons as for Claims 11–12.” (Final Act. 7). Because the
Examiner’s obviousness conclusion as to claims 19 and 20 is clear from the
body of the rejection, and given the Appellant’s statement in the September
26, 2019 Amendment that it “would proceed under the assumption that claims
19 and 20 were included in the rejection under 35 U.S.C. § 102” (see Appeal
Br. 6), we view the omission of claims 19 and 20 from the rejection statement
as harmless error.
We now turn to the merits of the anticipation rejection. The Appellant
argues that the Examiner reversibly erred in rejecting independent claim 1.
See generally Appeal Br. 7–12. The Appellant does not make separate
arguments in support of patentability of claims 2, 6–12, and 16–20. See id. at
12–13. Likewise, the Appellant relies on the same arguments in traversing the
rejection of dependent claims 3–5 and 13–15 as obvious over Haines. See id.
at 13. The Examiner relies on substantially the same fact finding and
reasoning in rejecting each of the independent claims: claims 1, 11 and 19.
See Final Act. 7.
The Appellant does not dispute the Examiner’s findings (see Final Act.
3) that Haines paragraph 67 teaches “a ground fault current sensor structured
to sense a ground fault current in [a] protected circuit” (claim 1) and that
Haines paragraphs 75 and 89 teach “a processor including a routine structured
to perform a ground fault output self-test” (claim 1). See generally Appeal Br.
7–12. Rather, the Appellant’s sole argument is that the Examiner relied on
“improper picking, choosing, and combining various disclosures not directly
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related to each other by the teachings of Haines” in finding that Haines
describes a ground fault output self-test having the claimed combination of
features. Id. at 7; see also Reply Br. 2. The Appellant’s arguments are
persuasive of reversible error for the reasons discussed below.
Figure 1, reproduced below, “is a schematic diagram of a circuit
interrupter 10 in accordance with an example embodiment” of the invention.
Spec. 4:14–15.

Figure 1, above, illustrates the arrangement of components in circuit
interrupter 10. Power from a power source (not shown) is conducted through
circuit interrupter 10 to the load via line and neutral conductors 12, 14. Id. at
4:17–19. Separable contacts 18, disposed along the line conductor 12, can be
tripped open by operating mechanism 20 (e.g., a solenoid) to stop current flow
through line conductor 12. Id. at 4:20–26. Operating mechanism 20 and
silicon controller rectifier (SCR) 22 are electrically connected in series
between line and neutral conductors 12, 14. Id. at 5:2–3. When processor 30
outputs a trip signal to SCR 22’s gate via one or both of trip outputs 24, 26,
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SCR 22 turns “on,” allowing current to flow between line and neutral
conductors 12, 14 through operating mechanism 20 and SCR 22. Id. at 5:6–8,
28–30. This, in turn, causes operating mechanism 20 to activate and trip open
separable contacts 18. Id. at 5:8–9.
As further illustrated in Figure 1, ground fault detection circuit 34 is
electrically connected between ground fault current sensor 16 and processor
30. Spec. 5:21–23. Ground fault current sensor 16 is structured to sense the
difference in current flowing between line and neutral conductors 12, 14. Id.
at 5:20–21. “[C]ircuit interrupter 10 is structured to perform a ground fault
self-test by performing a ground fault input self-test . . . and a ground fault
output self-test (i.e., self-test the circuit interrupter’s 10 ability to trip open the
separable contacts 18 in response to detecting the ground fault).” Id. at 6:23–
27; see also id. at 4:8–13 (defining the terms “ground input self-test” and
“ground output self-test”). Processor 30 is structured to perform the ground
output self-test by outputting a “trip signal during a positive half-cycle within
a predetermined phase angle before a zero-crossing of the current flowing
through the protected circuit.” Id. at 7:5–8 (emphasis added). This allows
current to flow between the line and neutral conductors 12, 14 through
operating mechanism 20 and SCR 22. Id. at 7:13–15. Processor 30 is
structured “to stop outputting the trip signal before the zero-crossing.” Id. at
7:5–8. By outputting the trip signal for only this short time period, the current
passing through operating mechanism 20 is not sufficient to activate operating
mechanism 20 and cause separable contacts 18 to trip open. Id. at 7:15–18.
However, the current flowing through operating mechanism 20 and SCR 22 is
sufficient to cause a difference in the currents flowing through line and neutral
conductors 12, 14 that may be sensed by ground fault current sensor 16. Id. at
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7:20–22. Specifically, turning on SCR 22 for this short time period causes a
pulse in the ground fault current provided at processor 30’s ground fault
current input 32. Id. at 7:23–24. “During the ground fault output self-test, the
processor 30 monitors for and determines whether the pulse in the ground
fault current is present.” Id. at 7:25–26. If processor 30 detects the pulse, then
circuit interrupter 10 passes the ground fault output self-test, which is
“indicative of proper operation and/or integrity of the diodes 24, 26, the SCR
22, the operating mechanism 20, and/or the separable contacts 18.” Id. at
7:28–8:3.
Similar to the Appellant’s circuit interrupter, Haines describes a circuit
that includes differential transformer 120, configured to sense the differential
current between phase conductor 102 and neutral conductor 104 to determine
the presence of a ground fault. Haines ¶ 65. The signal from differential
transformer 120 is provided to GFCI detector 124, which, in turn, provides an
output signal to processor 126 to trip relay drive 128 when the differential
current exceeds a predetermined limit. Id. Processor 126 outputs an
independent signal to trip relay drive 128, which signals trip actuator 129 to
trip circuit interrupter 130. Id. Trip relay 128 may includes an SCR in
combination with a trip (solenoid) actuator 129. Id. ¶ 94.
Haines discloses a self-test circuit (150) that is “configured to detect an
end of life condition by generating a test signal in response to a test command
signal generated by processor 126.” Haines ¶ 88. “[P]rocessor 126 monitors
the system response to the test signal to determine the operational state of
differential transformer 120, grounded neutral transformer 122, GFCI detector
124, trip relay drive 128, actuator 129, circuit interrupter 130, relay test 148,
or a subset thereof.” Id. ¶ 89.
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The Examiner relies on Haines paragraphs 91–94 “to meet the recited
elements of the ground fault output self-test.” Ans. 4. The Appellant has
persuasively argued that the self-tests described in these paragraphs, whether
considered individually or as a single, sequential routine, do not include all of
the claim 1 ground fault output self-test features. See Reply Br. 2. Several
claim 1 limitations absent from Haines’s self-test protocol are discussed
below.
Claim 1 requires that the processor is configured to output a trip signal
within a limited time frame: within a predetermined phase angle of a zero-
crossing of current flowing through the protected circuit, but ending before the
zero-crossing. As discussed in the Specification, outputting the trip signal
within this time frame prevents activation of operating mechanism 20 so that
separable contacts 18 do not trip open, but allows sufficient current flow
through operating mechanism 20 and SCR 22 to cause a detectable difference
in the currents flowing through line and neutral conductors 12, 14. See supra
pp. 6–7 (citing Spec. 7:15–22). The Examiner relies on Haines paragraphs 92
and 94 for teachings of these limitations. See Final Act. 3–4. Claim 1 also
requires that the processor is configured “to determine whether the trip signal
caused a pulse in the ground fault current.” The Examiner relies on Haines
paragraphs 91 and 92 for a teaching of this limitation. See Final Act. 4.
In paragraph 92, Haines teaches that “[p]rocessor 126 directs an output
pulse to actuator 129 during a zero-crossing of the AC power source,” or
“provide[s] a short duration pulse” (Haines ¶ 92 (emphasis added). See Ans.
9–10. In paragraph 94, Haines discloses a self-test signal that can be “timed to
occur during a predetermined portion of the AC cycle when the processor
126, trip relay drive 128, and/or actuator 129 are unable to generate a trip
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signal.” Haines ¶ 94 (emphasis added). Haines further discloses that when trip
relay 128 includes an SCR, the self-test signal is transmitted during the AC
source’s negative half cycles when the SCR is non-conductive and incapable
of energizing actuator 129 to trip circuit interrupter 130. Id. ¶ 94 (emphasis
added).
As argued by the Appellant, although Haines paragraph 92 describes a
trip signal, there is no description of stopping output of that trip signal before
the zero-crossing. See Appeal Br. 9–10. Conversely, paragraph 94 indicates
that the self-test signal is stopped before a zero-crossing, but that signal is not
a trip signal. Id. at 11. As further argued by the Appellant, although paragraph
92 describes sending a trip signal to actuator 129, the “detectable response”
from actuator 129 (Haines ¶ 92) is not described as indicating that “the trip
signal caused a pulse in the ground fault current” as required by claim 1.
Appeal Br. 10. Paragraph 91, also relied on by the Examiner for a teaching of
a processor configured “to determine whether the trip signal caused a pulse in
the ground fault current” (claim 1), discloses that self-test circuit 150
generates a voltage pulse and ground fault detector 124 responds with a pulsed
test acceptance signal. Haines explicitly states that “processor 126 does not
generate a trip signal” (Haines ¶ 91 (emphasis added)), and does not describe
the pulsed acceptance signal as indicating that a “trip signal caused a pulse in
the ground fault current” (claim 1). See Appeal Br. 9.
In sum, the Appellant’s arguments in the Appeal and Reply Briefs
persuasively demonstrate reversible error in the Examiner’s finding that
Haines paragraphs 91–94 describe the claimed ground fault output self-test.
As discussed above, each paragraph describes a distinct type of signal output
and response. See Reply Br. 2–3. The Examiner’s findings are insufficient to
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establish that the ordinary artisan, when looking at Haines as a whole, would
have recognized a description of “all elements of the claimed invention
arranged as in the claim,” Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359,
1369 n.5 (Fed. Cir. 2008). Nor has the Examiner explained how the ordinary
artisan would have combined these teachings to achieve the claimed
invention. Therefore, we do not sustain the rejection of claims 1, 2, 6–12, and
16–20 as anticipated by Haines. Because the Examiner’s rejection of claims
3–5 and 13–15 as obvious in view of Haines is based on the same unsupported
fact finding (see generally Final Act. 8–9), we likewise do not sustain that
rejection.

CONCLUSION
The Examiner’s decision to reject claims 1–20 is reversed.

DECISION SUMMARY

Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 2, 6–12,
16–20
102(a)(1) Haines 1, 2, 6–12,
16–20
3–5, 13–15 103 Haines 3–5, 13–15
Overall
Outcome:

1–20
REVERSED