Cadence Design Systems, Inc.

Patent Trials and Appeals Board

Jul 7, 2020

2019002318 (P.T.A.B. Jul. 7, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/199,951 06/30/2016 Ying Li 16PA022US01 9094
55497 7590 07/07/2020
Vista IP Law Group, LLP (Cadence)
2160 Lundy Avenue
Suite 230
San Jose, CA 95131
EXAMINER
THAI, TUAN V
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
07/07/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@viplawgroup.com
ttn@viplawgroup.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte YING LI, XIAOFEI LI, YANJUAN ZHAN,
ZHEHONG QIAN, and BUYING DU
____________

Appeal 2019-002318
Application 15/199,951
Technology Center 2100
____________

Before KARA L. SZPONDOWSKI, SCOTT B. HOWARD, and
STEVEN M. AMUNDSON, Administrative Patent Judges.

SZPONDOWSKI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
Non-Final Rejection of claims 1–20, which constitute all of the claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as Cadence
Design Systems, Inc. Appeal Br. 3.
Appeal 2019-002318
Application 15/199,951

2
STATEMENT OF THE CASE
Appellant’s invention relates to “the field of memory controllers.”
Spec. ¶ 1. Claim 1, reproduced below, is representative of the claimed
subject matter:
1. A memory controller comprising at least:
a per-bank refresh interface, the per-bank refresh
interface receiving one or more per-bank refresh commands
from a requesting apparatus external to the memory controller;
a system bus interface, the system bus interface receiving
one or more memory access commands from the requesting
apparatus external to the memory controller, the requesting
apparatus generating the one or more per-bank refresh
commands and the one or more memory access commands; and
a command queue, the command queue comprising at
least one or more storage elements, the storage elements storing
one or more per-bank refresh commands and one or more
memory access commands from the requesting apparatus
external to the memory controller.

REJECTIONS ON APPEAL
Claims 1, 3–8, 11, 13–18, and 20 stand rejected under 35 U.S.C. § 102
as anticipated by Kim (US 2017/0228175 A1; published Aug. 10, 2017).
Final Act. 4.
Claims 2 and 12 stand rejected under 35 U.S.C. § 103 as unpatentable
over Kim and Irish et al. (US 2008/0126641 A1; published May 29, 2008)
(“Irish”). Final Act. 14.
Claims 9, 10, and 19 stand rejected under 35 U.S.C. § 103 as
unpatentable over Kim and Lim et al. (US 2010/0037014 A1; published
Feb. 11, 2010) (“Lim”). Final Act. 17.
Appeal 2019-002318
Application 15/199,951

3
ANALYSIS
Appellant contends Kim does not disclose a
a per-bank refresh interface, the per-bank refresh interface
receiving one or more per-bank refresh commands from a
requesting apparatus external to the memory controller; a
system bus interface, the system bus interface receiving one or
more memory access commands from the requesting apparatus
external to the memory controller, the requesting apparatus
external to the memory controller and the one or more memory
access commands
as recited in independent claim 1 (emphasis added), and commensurately
recited in independent claim 11. Appeal Br. 11–12.
The Examiner finds that Kim teaches a memory controller receiving a
request “from the host which is OUTSIDE and external from the memory
controller.” Final Act. 4–5 (citing Kim Fig. 1, ¶ 27) (emphasis omitted); see
Ans. 27–28, 31. According to the Examiner, Kim teaches that “memory
controller 300 may manage memory operations for respective banks
according to the address received from the EXTERNAL device (for
example, a HOST).” Ans. 30 (citing Kim ¶¶ 122–123) (emphasis omitted).
The Examiner finds the memory controller’s “refresh manager is operated
under controller of the EXTERNAL HOST (figure 1) which is known for
initiating or generating the refresh command.” Ans. 28.
Appellant argues that “Kim discloses (i) generating per-bank refresh
commands only internally to the memory controller, and (ii) and does
NOT disclose receiving per-bank refresh commands from a source external
to the memory controller.” Appeal Br. 12; see id. at 12–15 (citing Kim
Fig. 2, ¶¶ 39, 55, 57). Appellant also argues that Kim “does not disclose that
the ‘HOST’ generates or transmits per-bank refresh commands – let alone a
memory controller receiving pre-bank refresh commands from a ‘HOST’
Appeal 2019-002318
Application 15/199,951

4
external to the memory controller.” Id. at 15–16 (citing Kim ¶ 43).
Specifically, Appellant argues that none of the cited sections “disclose a
source (requesting apparatus) external to the memory controller from
which per-bank refresh commands are received.” Reply Br. 6; see id. at 4.
Appellant argues “a mere request for access of an address does not
necessarily include a per-bank refresh command.” Id. at 5.
We are persuaded by Appellant’s arguments. Kim discloses:
For example, the memory controller 100 accesses data DATA of
a memory cell array 210 by providing a command CMD and an
address ADD to the memory device 200. The command CMD
may include commands related to various memory operations
such as data writing/reading. Furthermore, the command CMD
may include specific operations related to the DRAM, for
example, a refresh command in order to refresh memory cells
when the memory device 200 includes DRAM cells.
Kim ¶ 39 (emphasis added). Kim also discloses that “memory controller
100 may access the memory device 200 according to a request from a host
HOST,” and “memory controller 100 includes an access predictor 110 and a
refresh manager 120.” Kim ¶¶ 41, 43 (emphasis added). In other words,
Kim describes a memory controller that includes a refresh manager and
sends a refresh command. Kim also describes a host sending a request.
We do not see, and the Examiner has not sufficiently explained, how
Kim’s memory controller, that generates and sends refresh commands,
describes the claimed requesting apparatus, that sends refresh commands
and is external to the memory controller. Rather, in Kim, although the host,
which is external to the memory controller, sends a request, it is the memory
controller –– not the host –– which cannot be external to itself, that
generates and sends a refresh command.
Appeal 2019-002318
Application 15/199,951

5
Because we agree with at least one of the arguments advanced by
Appellant, we need not reach the merits of Appellant’s other arguments.
Accordingly, on this record, we do not sustain the Examiner’s § 102
rejection of independent claims 1 and 11, and dependent claims 3–8, 13–18,
and 20.
Moreover, because the Examiner has not shown that the additional
references cure the foregoing deficiencies regarding the rejection of the
independent claims 1 and 11, we will not sustain the obviousness rejections
of dependent claims 2, 9, 10, 12, and 19.
CONCLUSION
We reverse the Examiner’s rejection of claims 1, 3–8, 11, 13–18, and
20 under 35 U.S.C. § 102.
We reverse the Examiner’s rejections of claims 2, 9, 10, 12, and 19
under 35 U.S.C. § 103.
In summary:
Claims
Rejected
35 U.S.C. § Basis Affirmed Reversed
1, 3–8, 11,
13–18, 20
102 Kim 1, 3–8, 11,
13–18, 20
2, 12 103 Kim, Irish 2, 12
9, 10, 19 103 Kim, Lim 9, 10, 19
Overall
Outcome
1–20

REVERSED