ATI Technologies ULC et al.

Patent Trials and Appeals Board

Jan 27, 2021

2019003950 (P.T.A.B. Jan. 27, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/747,944 06/23/2015 Gongxian Jeffrey Cheng 1458-140371 7545
109712 7590 01/27/2021
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
6836 Austin Center Blvd.
Suite 320
Austin, TX 78731
EXAMINER
YU, JAE UN
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
01/27/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
AMD@DS-patent.com
docketing@ds-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GONGXIAN JEFFREY CHENG, MARK FOWLER,
PHILIP J. ROGERS, BENJAMIN T. SANDER,
ANTHONY ASARO, MIKE MANTOR, and RAJA KODURI

Appeal 2019-003950
Application 14/747,944
Technology Center 2100

Before JEAN R. HOMERE, CARL W. WHITEHEAD JR., and
JAMES B. ARPIN, Administrative Patent Judges.
HOMERE, Administrative Patent Judge.

DECISION ON APPEAL
I. STATEMENT OF THE CASE1
Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the
Examiner’s decision rejecting claims 1–7 and 9–20, all of the claims
pending.2 Appeal Br. 7. The Examiner objects to claim 8 as dependent
upon a rejected base claim, but claim 8 would otherwise be allowable if

1 We refer to the Specification filed June 23, 2015 (“Spec.”); the Final
Office Action, mailed June 6, 2018 (“Final Act.”); the Appeal Brief, filed
Nov. 5, 2018 (“Appeal Br.”); the Examiner’s Answer, mailed Feb. 26, 2019
(“Ans.”); and the Reply Brief, filed Apr. 25, 2019 (“Reply Br.”).
2 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42(a). Appellant identifies Advanced Micro Devices, Inc. as
the real party-in-interest. Appeal Br. 1.
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rewritten in independent form to include the limitations of the base claim
any intervening claims. Final Act. 7. We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.
II. CLAIMED SUBJECT MATTER
According to Appellant, the claimed subject matter relates to a
method and system for sharing a common virtual address space between a
central processing unit (CPU) and a graphical processing unit (GPU) within
processor (100). Spec. ¶¶ 1, 4, 5, Fig. 1.
Figure 1, reproduced and discussed below, is useful for
understanding the claimed subject matter:

Figure 1 above illustrates processor (100) including memory management
units (MMUs 107–109) for mapping a common virtual address space to a
corresponding physical address of CPU core (102) and to a corresponding
physical address of GPU core (104). Id. ¶¶ 4, 18.
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In particular, upon receiving a memory access request, MMUs (107–
109) translate a virtual address associated therewith to a corresponding
physical address based on CPU page tables (120). Id. ¶¶ 18–20. Likewise,
MMUs (107–109) translate the same virtual address to another physical
address based on GPU page tables (125). Id.
Claims 1, 10, and 14 are independent. Claim 1, reproduced below
with disputed limitations emphasized, is illustrative:
1. A method comprising:
translating, at a processor, virtual addresses for a virtual
address space to a first set of physical addresses for a first
processing unit of the processor; and
translating, at the processor, the same virtual addresses
for the virtual address space to a second set of physical
addresses for a second processing unit of the processor, the
second processing unit of a different processing unit type than
the first processing unit.
Appeal Br. 13 (Claims App.).
III. REFERENCES
The Examiner relies upon the following references.3
Name Reference Date
Olarig US 2002/0093507 A1 July 18, 2002
Zane US 2005/0022051 A1 Jan. 27, 2005
Dolan  US 8,972,694 B1  Mar. 3, 2015 
AAPA4  Spec. ¶ 2 June 23, 2015 

3 All reference citations are to the first named inventor only.
4 Appellant’s Admitted Prior Art.
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IV. REJECTIONS
The Examiner rejects claims 1–7 and 9–20 as follows:
Claims 1–7 and 10–20 are rejected under 35 U.S.C. § 103 as obvious
over the combined teachings of AAPA, Dolan, and Olarig. Final Act. 2–5.
Claim 9 is rejected under 35 U.S.C. § 103 as obvious over the
combined teachings of AAPA, Dolan, Olarig and Zane. Id. at 5–6.
V. ANALYSIS
Appellant argues that the combination of AAPA, Dolan and Olarig
Klein does not teach or suggest the limitations of “translating, at the
processor, the same virtual addresses for the virtual address space to a
second set of physical addresses for a second processing unit of the
processor,” as recited in independent claim 1. Appeal Br. 4–6.
As a preliminary matter, it is undisputed that AAPA discloses a
processor employing a CPU core for executing general purpose instructions
and a GPU core for executing graphics and display operations. Id. at 4;
Ans. 3 (citing Spec. ¶ 2).5 Likewise, Appellant does not dispute the
Examiner’s finding that Dolan discloses thin devices that appear to a host
device as logical volumes containing virtually provisioned data blocks and
pointers identifying physical data devices according to entries in a track
table. Appeal Br. 5 (citing Dolan 14:7–13, 59–63, Figs. 5B, 5C). Therefore,
Appellant acknowledges that Dolan teaches using a track table to map
virtual addresses of thin devices to physical addresses of disk drives
associated with a CPU. Id. Additionally, Appellant acknowledges that

5 Due to a pagination mistake in the Answer, page 3 should be 2.

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Olarig discloses remapping a graphic controller device address to a physical
address. Id. (citing Olarig ¶¶ 86, 87).
Nevertheless, Appellant disputes the Examiner’s finding that the
combined teachings of AAPA, Dolan, and Olarig would have resulted in
mapping the same virtual address to the physical address of the CPU and the
separate physical address of the GPU. Id. Appellant’s arguments are
persuasive of reversible Examiner error.
We agree with Appellant that the proposed combined teachings would
not have resulted in the disputed limitations. Apart from relying on
impermissible hindsight, the Examiner does not provide sufficient rationale
to map the same virtual address to the physical address of the CPU and the
separate physical address of the GPU, as required by the claim. Final Act. 3
(citing Olarig ¶ 19, Fig. 9). In particular, we find the Examiner’s proffered
rationale that doing so would enhance the efficiency of the system is as best
speculative. Id. Although the cited portion of Olarig discusses efficiency, it
is merely in the context of using the GART table to facilitate translation of a
page address to physical memory when implementing APG-3D graphics.
Olarig ¶ 19. Otherwise, the record before us is devoid of evidence sufficient
to motivate the ordinarily skilled artisan to map the same virtual address to a
physical address of a CPU and a separate physical address of the GPU
within a computing system.
Because Appellant shows at least one reversible error in the
Examiner’s obviousness rejection of independent claim 1, we do not reach
Appellant’s remaining arguments. Accordingly, we do not sustain the
Examiner’s obviousness rejection of independent claims 1, 10, and 14, each
of which includes the argued disputed limitations. Likewise, we do not
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sustain the rejections of dependent claims 2–7, 9, 11–13, and 15–20, which
also recite the disputed limitations.
VI. CONCLUSION
We reverse the Examiner’s rejections of claims 1–7 and 9–20.
VII. DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–7, 10–20 103 AAPA, Dolan, Olarig 1–7, 10–20
9 103 AAPA, Dolan, Olarig, Zane 9
Overall
Outcome 1–7, 9–20

REVERSED