Annamraju, Venu et al.

Patent Trials and Appeals Board

Jan 3, 2020

14571477 - (D) (P.T.A.B. Jan. 3, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/571,477 12/16/2014 Venu Annamraju 070852.000078 1061
125968 7590 01/03/2020
Vorys, Sater, Seymour and Pease LLP
(ImgTec)
1909 K St., N.W.
Ninth Floor
Washington, DC 20006
EXAMINER
HODGES, SUSAN E
ART UNIT PAPER NUMBER
2425
NOTIFICATION DATE DELIVERY MODE
01/03/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
jbucks@potomaclaw.com
patlaw@vorys.com
vmdeluca@vorys.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte VENU ANNAMRAJU and HARISH RAJAMANI
____________

Appeal 2019-000432
Application 14/571,477
Technology Center 2400
____________

Before JOHN A. JEFFERY, JAMES W. DEJMEK, and
STEPHEN E. BELISLE, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Under 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s
decision to reject claims 1–16. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42 (2017). Appellant identifies the real party in interest as
Imagination Technologies Limited of Kings Langley, United Kingdom.
Appeal Br. 1.
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STATEMENT OF THE CASE
Appellant’s invention encodes a stream of media data blocks using
(1) an encoder pipeline comprising a series of modules that process a stream
of media data blocks, and (2) a “pipeline configurator” that switches the
pipeline from first to second encode parameters. Abstract; Spec. 9–10;
Fig. 1. To this end, the pipeline configurator transmits signals to the
pipeline’s modules downstream from the first module (i.e., the subsequent
modules) to enter a trigger mode such that they wait for a media frame with
an associated trigger flag indicating to the module to switch from current to
updated encode parameters. Spec. 12. The pipeline’s first module also
enters a mode where it adopts the updated encode parameters such that the
next frame is processed according to those parameters. Id. Upon receiving a
media frame with a trigger flag, the pipeline’s subsequent modules
immediately process that frame according to updated encode parameters.
See id. Claims 1 and 14 are illustrative:

1. A media encoder for encoding a stream of media data blocks,
the media encoder comprising:
an encoder pipeline configured to process a stream of media data
blocks in accordance with one or more first encode parameters, the encoder
pipeline comprising a sequence of processing modules including a first
processing module and one or more subsequent processing modules; and
a pipeline configurator configured to, in order to effect a switch in the
encoder pipeline from the one or more first encode parameters to one or
more second encode parameters, cause the subsequent processing modules
of the pipeline to enter a trigger mode and cause the first processing module
to adopt the second encode parameters;

the first processing module being configured to, on adopting the
second encode parameters, associate a trigger value with at least a first
media data block processed at the first processing module in accordance
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with the second encode parameters; and in trigger mode, each of the
subsequent processing modules being configured to, in response to receiving
the trigger value, adopt the second encode parameters.

14. A method of switching encode configurations at an encoder
pipeline for processing a stream of media data blocks in accordance with one
or more encode parameters, the encoder pipeline comprising a sequence of
processing modules including a first processing module and one or more
subsequent processing modules, the method comprising, in order to switch
the encoder pipeline from one or more first encode parameters to one or
more second encode parameters:
causing the subsequent processing modules of the pipeline to enter a
trigger
mode;
causing the first processing module of the pipeline to adopt the second
encode parameters;
the first processing module, on adopting the second encode
parameters:
associating a trigger flag with at least a first media data block
processed at the first processing module in accordance with the second
encode parameters; and each of the subsequent processing modules in
response to receiving the trigger flag associated with the first media data
block:
adopting the second encode parameters; and
processing the first media data block in accordance with the second
encode parameters.

THE REJECTIONS
The Examiner rejected claims 1–14 under 35 U.S.C. § 112(b) as
indefinite. Final Act. 5–6.2

2 Throughout this opinion, we refer to (1) the Final Rejection mailed
January 10, 2018 (“Final Act.”); (2) the Appeal Brief filed June 11, 2018
(“Appeal Br.”); (3) the Examiner’s Answer mailed August 23, 2018
(“Ans.”); and (4) the Reply Brief filed October 23, 2018 (“Reply Br.”).
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The Examiner rejected claims 1–16 under 35 U.S.C. § 101 as directed
to ineligible subject matter. Final Act. 6–8.
The Examiner rejected claims 1–16 under 35 U.S.C. § 102(a)(1) as
anticipated by Raveendran (US 2007/0074266 Al; published Mar. 29, 2007).
Final Act. 8–15.

THE INDEFINITENESS REJECTION
Regarding independent claim 1, the Examiner interprets the recited
“encoder pipeline configured to process a stream of media data blocks in
accordance with one or more first encode parameters” as a means-plus-
function limitation under 35 U.S.C. § 112(f). Final Act. 5–6; Ans. 3–5.
According to the Examiner, the recited “pipeline” is a “generic placeholder”
equivalent to the term “means” that is not preceded by a structural modifier,
and the pipeline performs a specific function, namely processing the stream
of media data blocks. Ans. 4. Because Appellant’s written description is
said to lack the corresponding structure, material, or acts to perform this
recited function, the Examiner concludes that the claim is indefinite. Final
Act. 4–5; Ans. 4–5.
Appellant argues that the Specification discloses the corresponding
structure for the recited encoder pipeline, including its processing modules
and their associated functions and, therefore, the claim is definite. Appeal
Br. 6–8; Reply Br. 1–4. According to Appellant, Figure 1 of the present
application and the associated description in the Specification disclose a
pipeline 102 comprising a preprocessor 103, encoder 104, and packetizer
105 that collectively perform the recited function, namely process a stream
of media data blocks. See Appeal Br. 6–8; Reply Br. 2–4.
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ISSUE
Has the Examiner erred in rejecting claim 1 as indefinite under
§ 112(b) by finding that the recited “encoder pipeline configured to process
a stream of media data blocks in accordance with one or more first encode
parameters” (the “encoder pipeline limitation”) is a means-plus-function
limitation that lacks corresponding structure, material, or acts in the
Specification to perform the recited function?

ANALYSIS
As noted above, this dispute turns on whether the encoder pipeline
limitation is equivalent to a means-plus-function limitation under § 112(f),
for if it is, it must be construed in light of the corresponding structure in the
Specification and its equivalents. See In re Donaldson Co., Inc., 16 F.3d
1189, 1193 (Fed. Cir. 1994) (en banc). For computer-related inventions so
construed, the application must disclose enough of an algorithm to provide
the requisite structure—a disclosure that can be expressed in any
understandable terms (e.g., a mathematical formula, in prose, or as a
flowchart). See Finisar Corp. v. DirecTV Group, Inc., 523 F.3d 1323, 1341
(Fed. Cir. 2008); see also Aristocrat Techs. Australia Pty Ltd. v. Int’l Game
Tech., 521 F.3d 1328, 1333 (Fed. Cir. 2008).
As noted above, the Examiner interprets the encoder pipeline
limitation as a means-plus-function limitation under § 112(f) because the
term “pipeline” is said to be a “generic placeholder” that is not preceded by
a structural modifier, where this “generic placeholder” performs a specific
function, namely processing the media data block stream. See Ans. 4.
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We see no error in this means-plus-function interpretation. Apart
from reciting that the encoder pipeline is configured to perform this
function, the claim recites no particular structure to achieve that end apart
from recited sequence of processing modules.
Although omitting the term “means” in a claim element creates a
rebuttable presumption that § 112(f) does not apply, such an omission does
not automatically prevent that element from being construed as a means-
plus-function element. See Williamson v. Citrix Online, LLC, 792 F.3d
1339, 1348 (Fed. Cir. 2015) (en banc). In such a case, § 112(f) will apply if
the claim term fails to recite sufficiently definite structure, or else recites
function without reciting sufficient structure for performing that function.
See id. at 1349.
That is the case here. First, we agree with the Examiner that the term
“encoder pipeline” is merely a generic description for software or hardware
that performs the specified functions, despite the encoder pipeline
comprising a sequence of processing modules—modules that are likewise
described in terms of their function. That is, the term “encoder pipeline” is
merely a nonce word or “non-structural generic placeholder” that is
tantamount to the term “means” because it fails to connote sufficiently
definite structure and, in the context of claim 1, invokes § 112(f). Cf. id. at
1350 (discussing similar nonce words).
We reach this conclusion despite the fact that the recited encoder
pipeline comprises a sequence of processing modules. Like the recited
“pipeline,” the recited modules are merely nonce words or “non-structural
generic placeholders” that are tantamount to the term “means” because they
fail to connote sufficiently definite structure. Nor do their respective
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modifying terms add sufficient structure to the recited elements to preclude
§ 112(f) construction, for they merely identify the elements’ recited
functions. Cf. Ex parte Lakkala, No. 2011-001526 (PTAB Mar. 13, 2013)
(expanded panel) (informative); Ex parte Erol, No. 2011-001143 (PTAB
Mar. 13, 2013) (expanded panel) (informative); Ex parte Smith, No. 2012-
007631 (PTAB Mar. 14, 2013) (expanded panel) (informative)).3 That the
Manual of Patent Examining Procedure (MPEP) includes “module for” as an
exemplary non-structural generic placeholder only bolsters this conclusion.
See MPEP § 2181(I)(A) (9th ed. Rev. 08.2017, Jan. 2018).
Our means-plus-function interpretation is consistent with the broad
and functional meaning of the term “pipeline” in the art, namely “a principle
employed to improve the efficiency of many kinds of processing task, such
as the arithmetic units in most modern microprocessors. It involves dividing
the task into several discrete stages and overlapping these in time by passing
them through a sequence of independently operating units.” Dick Pountain,
THE PENGUIN CONCISE DICTIONARY OF COMPUTING 335 (2003) (“Penguin
Computer Dictionary”). That dictionary explains that “pipelining is the
same principle employed in a factory production line where many workers
simultaneously fit different parts to a moving line of cars.” Id. The
dictionary adds that “[t]he pipeline does not reduce the overall time to
complete one item (each car might still take an hour to pass through the line)
but more items can be completed in a given time: with 10 workstations a
finished car emerges every 6 minutes.” Id.

3 These three informative Opinions are available from the Board’s web page
at https://www.uspto.gov/patents-application-process/appealing-patent-
decisions/decisions-and-opinions/informative-opinions-0#heading-8.
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Another computer dictionary defines the term “pipeline” to mean “[i]n
computer processor design, an ‘assembly line’ in the processor that
dramatically speeds the processing of instructions through retrieval,
execution, and writing data back to the memory.” That dictionary explains
that “[w]ithin the pipeline, each step constitutes a functional unit that is
optimally designed to perform one task, such as fetching instructions,
decoding instructions, fetching arguments, performing arithmetic operations,
or storing results.” Bryan Pfaffenberger, WEBSTER’S NEW WORLD
COMPUTER DICTIONARY 284 (10th ed. 1993). That dictionary adds that
“[b]ecause each of the pipeline’s functional units can work simultaneously, a
processor can, in effect, process more than one instruction at a time.” Id. at
284–85.
The clear import of these authorities is that a pipeline has multiple
processing units that work together to complete a task. This feature is not
only common to both dictionary definitions, but is also consistent with the
recited sequence of processing modules and the corresponding description of
those modules, namely the preprocessor 103, encoder 104, and packetizer
105, in Figure 1 and pages 9 and 10 of the Specification.
Although the term “pipeline” connotes multiple processing units, that
alone does not impart sufficient structure to avoid means-plus-function
treatment under § 112(f). That is, merely reciting plural non-structural
generic placeholders does not, without more, avoid functional claiming
where, as here, the pipeline’s multiple processing modules are recited solely
in terms of their functions, namely what they do—not what they are
structurally to achieve these functions.
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Although the recited “pipeline” is modified by the word “encoder,”
this modifier does not add sufficient structure to the recited element to
preclude § 112, sixth paragraph construction, for it merely identifies the
element’s recited function. The term “encoder” is defined in the art, quite
broadly, as “any hardware or software that encodes information—that is,
converts the information to a particular form or format.” MICROSOFT
COMPUTER DICTIONARY 192 (5th ed. 2002) (“Microsoft Computer
Dictionary”) (emphasis added). Therefore, the Examiner’s finding that the
“generic placeholder,” namely the pipeline, is not preceded by a structural
modifier (Ans. 4) has merit, given this definition that refers, quite broadly, to
any hardware or software that performs the specified function, namely
converting information to particular form or format.
Therefore, we agree with the Examiner that the recited “encoder
pipeline configured to process a stream of media data blocks in accordance
with one or more first encode parameters” is a means-plus-function
limitation under § 112(f). Indeed, Appellant does not dispute this means-
plus-function interpretation, but rather argues that the claim is definite when
read in light of the corresponding description in the Specification. See
Appeal Br. 6–8; Reply Br. 1–4.
We agree with Appellant. As shown in Appellant’s Figure 1
reproduced below, media encoder 100 includes encoder pipeline 102 with
preprocessor 103, encoder 104, and packetizer 105. See Spec. 9.

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Appellant’s Figure 1 showing encoder pipeline with preprocessor,
encoder and packetizer

As explained on page 9 of the Specification, the encoder pipeline’s
preprocessor 103 processes a stream of media buffers from media source
101 before encoding. Then, the pipeline’s encoder module 104 encodes the
media buffers into an encoded media stream that is then formed into data
packets by packetizer 105. Spec. 9. This sequence is shown graphically in
Figure 1 above, where the arrow indicating the preprocessor’s output is
directed to the encoder’s input, and the encoder’s output is directed to the
packetizer’s input. See Spec. 9–10.
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It is well settled that for computer-related inventions construed under
§ 112(f), the application must disclose enough of an algorithm to provide the
requisite structure—a disclosure that can be expressed in any
understandable terms (e.g., a mathematical formula, in prose, or as a
flowchart). See Finisar, 523 F.3d at 1341; see also Aristocrat, 521 F.3d at
1333.
As the Federal Circuit has explained, an “‘algorithm’ in computer
systems has a broad meaning, for it encompasses “in essence a series of
instructions for the computer to follow . . . whether in mathematical formula,
or a word description of the procedure to be implemented by a suitably
programmed computer.” Typhoon Touch Techs., Inc. v. Dell, Inc., 659 F.3d
1376, 1384 (Fed. Cir. 2011). The Federal Circuit further noted its
predecessor court’s preferred definition of “algorithm” in the computer art as
“[a] fixed step-by-step procedure for accomplishing a given result; usually a
simplified procedure for solving a complex problem, also a full statement of
a finite number of steps.” Id. at 1384–85 (quoting In re Freeman, 573 F.2d
1237, 1245 (CCPA 1978)).
The Federal Circuit emphasized that a patent need only disclose
sufficient structure for an ordinarily skilled artisan to provide an operative
software program for the specified function, and that “[t]he amount of detail
that must be included in the specification depends on the subject matter that
is described and its role in the invention as a whole, in view of the existing
knowledge in the field of the invention.” Typhoon Touch, 659 F.3d at 1385.
The court added that “[f]or computer-implemented procedures, the computer
code is not required to be included in the patent specification.” Id.
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Here, although the encoder pipeline’s preprocessor, encoder, and
packetizer are described at a high level of generality, their respective
functions nevertheless set forth an algorithm given the disclosed sequence
shown in Figure 1—a fixed step-by-step procedure for accomplishing a
given result, namely processing a media data block stream. We reach this
conclusion noting that the broad functions of each processing module in this
regard, namely pre-processing, encoding, and packetizing, are well known in
the art to achieve these results and, therefore, need not be described in detail,
at least with respect to these well-known functions that can be performed by
general-purpose computers. See Typhoon Touch, 659 F.3d at 1385; see also
Spec. 1–2 (describing known video stream encoding systems); Microsoft
Computer Dictionary, at 192 (defining “encoder” as “any hardware or
software that encodes information—that is, converts the information to a
particular form or format”); Penguin Computer Dictionary, at 317 (defining
“Packet Assembler/Disassembler” as “a hardware or software device that
splits up a stream of data into packets for transmission over a network . . .
and recombines them at the receiving end”).
Therefore, we agree with Appellant that the Specification reasonably
supports the encoder pipeline limitation, at least with respect to its ability to
process of a stream of media data blocks and, therefore, the claim is definite
under § 112(b).4 Accordingly, we are persuaded that the Examiner
indefiniteness rejection of claims 1–14 is erroneous.

4 Nevertheless, to the extent that Appellant contends that the Examiner erred
by rejecting the claim as indefinite merely because the Examiner found the
encoder pipeline limitation is anticipated by Raveendran (see Appeal Br. 8),
such an argument is unavailing. Despite the Examiner’s error in the
indefiniteness rejection, the Examiner’s overall approach, namely rejecting
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THE INELIGIBILITY REJECTION
The Examiner determines that the claimed invention is directed to an
abstract idea, namely organizing data, and more specifically, organizing
which encoded parameter is used for video encoding and changing the order
in which the coding process is performed. See Final Act. 6–8; Ans. 5–6.
The Examiner adds that the claims do not include elements that add
significantly more than the abstract idea, but merely describe (1) a trigger
mode; (2) adopting a second set of parameters; and (3) processing the data
blocks. See Final Act. 7–8; Ans. 6.
Appellant argues that not only did the Examiner fail to analyze the
claim language in the rejection, the claims are nevertheless eligible because,
among other things, they are directed to a specific technical improvement
that switches encode parameters of a media data encoder responsive to
changes in network conditions. Appeal Br. 9–10; Reply Br. 4–6. This
improvement is said to prevent excessive buffering delays and packet loss
that (1) disrupts the encoded data stream; (2) freezes frames; and
(3) produces frame artifacts during playback. Reply Br. 5.

ISSUE
Under § 101, has the Examiner erred in rejecting claims 1–16 as
directed to ineligible subject matter? This issue turns on whether the claims

the claim under both sections 112(b) and 102, comports with established
examination guidelines promoting compact prosecution. See MPEP
§ 2173.06 (instructing Examiners to reject indefinite claims over prior art, if
appropriate, and articulate the claim construction clearly on the record with
respect to the prior art applied in the rejection).

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are directed to an abstract idea and, if so, whether the recited elements—
considered individually and as an ordered combination—transform the
nature of the claims into a patent-eligible application of that abstract idea.

PRINCIPLES OF LAW
An invention is patent eligible if it claims a “new and useful process,
machine, manufacture, or composition of matter.” 35 U.S.C. § 101.
However, the Supreme Court has long interpreted 35 U.S.C. § 101 to include
implicit exceptions: “[l]aws of nature, natural phenomena, and abstract
ideas” are not patentable. See, e.g., Alice Corp. v. CLS Bank Int’l, 573 U.S.
208, 216 (2014).
In determining whether a claim falls within an excluded category, we
are guided by the Supreme Court’s two-step framework, described in Mayo
and Alice. Id. at 217–18 (citing Mayo Collaborative Servs. v. Prometheus
Labs., Inc., 566 U.S. 66, 75–77 (2012)). In accordance with that framework,
we first determine what concept the claim is “directed to.” See Alice, 573
U.S. at 219 (“On their face, the claims before us are drawn to the concept of
intermediated settlement, i.e., the use of a third party to mitigate settlement
risk.”); see also Bilski v. Kappos, 561 U.S. 593, 611 (2010) (“Claims 1 and 4
in petitioners’ application explain the basic concept of hedging, or protecting
against risk.”).
Concepts determined to be abstract ideas, and thus patent ineligible,
include certain methods of organizing human activity, such as fundamental
economic practices (Alice, 573 U.S. at 219–20; Bilski, 561 U.S. at 611);
mathematical formulas (Parker v. Flook, 437 U.S. 584, 594–95 (1978)); and
mental processes (Gottschalk v. Benson, 409 U.S. 63, 67 (1972)). Concepts
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determined to be patent eligible include physical and chemical processes,
such as “molding rubber products” (Diamond v. Diehr, 450 U.S. 175, 191
(1981)); “tanning, dyeing, making water-proof cloth, vulcanizing India
rubber, smelting ores” (id. at 187 n.7 (quoting Corning v. Burden, 56 U.S.
(15 How.) 252, 267–68 (1854))); and manufacturing flour (Benson, 409 U.S.
at 69 (citing Cochrane v. Deener, 94 U.S. 780, 785 (1876))).
In Diehr, the claim at issue recited a mathematical formula, but the
Supreme Court held that “[a] claim drawn to subject matter otherwise
statutory does not become nonstatutory simply because it uses a
mathematical formula.” Diehr, 450 U.S. at 176; see also id. at 191 (“We
view respondents’ claims as nothing more than a process for molding rubber
products and not as an attempt to patent a mathematical formula.”). That
said, the Supreme Court also indicated that a claim “seeking patent
protection for that formula in the abstract . . . is not accorded the protection
of our patent laws, . . . and this principle cannot be circumvented by
attempting to limit the use of the formula to a particular technological
environment.” Id. (citing Benson and Flook); see, e.g., id. at 187 (“It is now
commonplace that an application of a law of nature or mathematical formula
to a known structure or process may well be deserving of patent
protection.”).
If the claim is “directed to” an abstract idea, we turn to the second
step of the Alice and Mayo framework, where “we must examine the
elements of the claim to determine whether it contains an ‘inventive
concept’ sufficient to ‘transform’ the claimed abstract idea into a patent-
eligible application.” Alice, 573 U.S. at 221 (quotation marks omitted). “A
claim that recites an abstract idea must include ‘additional features’ to
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ensure ‘that the [claim] is more than a drafting effort designed to
monopolize the [abstract idea].’” Id. (alterations in original) (quoting Mayo,
566 U.S. at 77). “[M]erely requir[ing] generic computer implementation[]
fail[s] to transform that abstract idea into a patent-eligible invention.” Id.
In January 2019, the United States Patent and Trademark Office
(“USPTO”) published revised guidance on the application of § 101. See
USPTO’s 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed.
Reg. 50 (Jan. 7, 2019) (“Guidance”). Under that guidance, we first look to
whether the claim recites:
(1) any judicial exceptions, including certain groupings of
abstract ideas (i.e., mathematical concepts, certain methods of
organizing human activity such as a fundamental economic
practice, or mental processes); and
(2) additional elements that integrate the judicial exception into
a practical application (see MANUAL OF PATENT EXAMINING
PROCEDURE (MPEP) § 2106.05(a)–(c), (e)–(h) (9th ed. Rev.
08.2017, Jan. 2018)).
Only if a claim (1) recites a judicial exception, and (2) does not integrate that
exception into a practical application, do we then look to whether the claim:
(3) adds a specific limitation beyond the judicial exception that
is not well-understood, routine, and conventional in the field
(see MPEP § 2106.05(d)); or
(4) simply appends well-understood, routine, and conventional
activities previously known to the industry, specified at a high
level of generality, to the judicial exception.
See Guidance, 84 Fed. Reg. at 56.
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ANALYSIS
Claims 1–16: Alice/Mayo Step One
Representative independent claim 14 recites:
A method of switching encode configurations at an encoder pipeline
for processing a stream of media data blocks in accordance with one or more
encode parameters, the encoder pipeline comprising a sequence of
processing modules including a first processing module and one or more
subsequent processing modules, the method comprising, in order to switch
the encoder pipeline from one or more first encode parameters to one or
more second encode parameters:

causing the subsequent processing modules of the pipeline to enter a
trigger mode;

causing the first processing module of the pipeline to adopt the second
encode parameters;

the first processing module, on adopting the second encode
parameters:

associating a trigger flag with at least a first media data block
processed at the first processing module in accordance with the second
encode parameters; and each of the subsequent processing modules in
response to receiving the trigger flag associated with the first media data
block:

adopting the second encode parameters; and

processing the first media data block in accordance with the second
encode parameters.

As the disclosure explains, Appellant’s invention encodes a stream of
media data blocks using (1) an encoder pipeline comprising a series of
modules that process a stream of media data blocks, and (2) a “pipeline
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configurator” that switches the pipeline from first to second encode
parameters. Abstract; Spec. 9–10; Fig. 1. These parameters determine the
nature of the encoding for a given source media stream, and can define, for
example, (1) the encoding format; (2) target bitrate; (3) compression level;
or (4) settings particular to the encoding format used. Spec. 10.
As explained on page 9 of the Specification, the encoder pipeline’s
preprocessor 103 processes a stream of media buffers from media source
101 before encoding. Then, the pipeline’s encoder module 104 encodes the
media buffers into an encoded media stream that is then formed into data
packets by packetizer 105. Spec. 9. This sequence is shown graphically in
Figure 1, where the arrow indicating the preprocessor’s output is directed to
the encoder’s input, and the encoder’s output is directed to the packetizer’s
input. See Spec. 9–10.
Pipeline configurator 106 transmits signals to the encoder 104 and
packetizer 105 to cause those modules to enter a trigger mode such that
those modules wait for a media frame with an associated trigger flag
indicating to the module to switch from current to an updated encode
parameters. Spec. 12. The pipeline configurator also signals to the
preprocessor to enter an “immediate” mode where the preprocessor adopts
the updated encode parameters such that the next frame is processed
according to those parameters. Id. Upon receiving a media frame with a
trigger flag, the encoder and packetizer immediately process that frame
according to updated encode parameters. Id. 13.
This frame-based configuration switching functionality not only
ensures that all frames of the media stream are processed according to the
updated encode parameters, but that all previous frames are processed
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according to the previous parameters, thus ensuring seamless dynamic
parameter switching. Spec. 14. This technique thus avoids some modules
processing a frame according to one parameter set, but other modules
processing that frame according to another parameter set. See Spec. 14. As
a result, the viewer will not notice any glitches or freezing during playback.
Id.
Turning to claim 14, we first note that the claim recites a method and,
therefore, falls within the process category of § 101. But despite falling
within this statutory category, we must still determine whether the claim is
directed to a judicial exception, namely an abstract idea. See Alice, 573 U.S.
at 217. To this end, we must determine whether the claim (1) recites a
judicial exception, and (2) fails to integrate the exception into a practical
application. See Guidance, 84 Fed. Reg. at 52–55. If both elements are
satisfied, the claim is directed to a judicial exception under the first step of
the Alice/Mayo test. See id.
In the rejection, the Examiner determines that claim 14 is directed to
an abstract idea, namely organizing data, and more specifically, organizing
which encoded parameter is used for video encoding and changing the order
in which the coding process is performed. See Final Act. 6–8; Ans. 5–6.
To determine whether a claim recites an abstract idea, we (1) identify the
claim’s specific limitations that recite an abstract idea, and (2) determine
whether the identified limitations fall within certain subject matter
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groupings, namely, (a) mathematical concepts5; (b) certain methods of
organizing human activity6; or (c) mental processes.7
Here, none of the recited steps of the recited encode configuration
switching method fall within any of the above categories of the USPTO’s
guidelines. That is, the recited “causing the subsequent processing modules
of the pipeline to enter a trigger mode”; “causing the first processing module
of the pipeline to adopt the second encode parameters” and the first
processing module’s “associating a trigger flag with at least a first media
data block processed at the first processing module in accordance with the
second encode parameters” upon “adopting the second encode parameters”
(1) cannot be performed mentally; (2) are not reasonably analogous to the
certain methods of organizing human activity under the agency’s guidelines,
including managing personal behavior or relationships or interactions
between people or fundamental economic practices; or (3) do not recite
mathematical concepts include mathematical relationships, mathematical

5 Mathematical concepts include mathematical relationships, mathematical
formulas or equations, and mathematical calculations. See Guidance, 84
Fed. Reg. at 52.
6 Certain methods of organizing human activity include fundamental
economic principles or practices (including hedging, insurance, mitigating
risk); commercial or legal interactions (including agreements in the form of
contracts; legal obligations; advertising, marketing or sales activities or
behaviors; business relations); managing personal behavior or relationships
or interactions between people (including social activities, teaching, and
following rules or instructions). See Guidance, 84 Fed. Reg. at 52.
7 Mental processes are concepts performed in the human mind including an
observation, evaluation, judgment, or opinion. See Guidance, 84 Fed. Reg.
at 52.
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formulas or equations, and mathematical calculations. See Guidance, 84
Fed. Reg. at 52.
We reach the same conclusion regarding the recited functionality of
the subsequent processing modules, namely that each of those modules,
responsive to receiving the trigger flag associated with the first media data
block, (1) “adopt[s] the second encode parameters; and (2) process[es] the
first media data block in accordance with the second encode parameters.”
In short, because the foregoing recited limitations do not fit in any of
the categories of abstract ideas in the USPTO’s guidelines, they do not recite
an abstract idea. See id. at 54. Accordingly, the claimed invention, when
considered as a whole, is not directed to an abstract idea and is, therefore,
eligible under § 101 for that reason alone.
Nevertheless, even if the recited limitations could somehow fit into
one of the above categories, such as mental processes or the certain methods
of organizing human activity categories by merely automating a manual
process of switching encode configurations—which they do not—the recited
limitations nonetheless integrate the exception into a practical application
and are, therefore, eligible for that additional reason.
To be sure, the Federal Circuit has held that encoding and decoding
information are processes that can—and have been—performed in the
human mind. See Return Mail, Inc. v. U.S. Postal Service, 868 F.3d 1350,
1368 (Fed. Cir. 2017). In addition, migrating data, including configuration
settings, between two computers automatically has also been held to be an
abstract idea. See Tranxition, Inc. v. Lenovo (United States) Inc., 664 F.
App’x 968, 970–972 (Fed. Cir. 2016) (unpublished) (holding ineligible
recited method for preparing configuration settings for transfer from a
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source computing system to a target computing system by, among other
things, (1) retrieving extracted configuration settings identified as active
configuration settings of a generated transition plan, and (2) transitioning the
retrieved settings from a format used on the source computing system to
format used on the target computing system as directed to the abstract idea
of migrating or transitioning settings).
But unlike the invention in Tranxition that merely automated data
migration between two computers, the claimed invention here achieves a
technical improvement by specifying a particular way in which encode
configurations are switched at an encoder pipeline. Among other things, the
Appellant’s claimed invention specifies a particular sequence beginning with
the pipeline’s first processing module first adopting the updated
parameters—a machine-based adoption that then triggers the subsequent
processing modules that have entered a “trigger mode” to adopt those
parameters using a trigger flag that is associated with the first media data
block.
As the Specification explains, this configuration switching
functionality not only ensures that all frames of the media stream are
processed according to the updated encode parameters, but that all previous
frames are processed according to the previous parameters. Spec. 14. This
technique ensures seamless dynamic parameter switching, thus avoiding
some modules processing a frame according to one parameter set, but other
modules processing that frame according to another parameter set. See id.
As a result, the viewer will not notice any glitches or freezing during
playback. Id.
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This seamless dynamic parameter switching, made possible by the
particular machine-oriented technique claimed, realizes a specific technical
improvement that prevents excessive buffering delays and packet loss, thus
avoiding (1) encoded data stream disruptions; (2) frame freezing; and
(3) frame artifact production during playback as Appellant indicates. Reply
Br. 5. As was the case in in McRO, Inc. v. Bandai Namco Games America,
Inc., 837 F.3d 1299, 1314–16 (Fed. Cir. 2016), the claimed invention here
uses a combined order of specific rules in a process designed specifically to
achieve an improved technological result, namely switching encode
configurations seamlessly between modules in an encoder pipeline for
processing a media data block stream. Notably, the claimed invention
avoids the above-noted problems encountered during playback without the
recited configuration switching technique.
Therefore, given this technological improvement, even if claim 14
were construed to recite an abstract idea as the Examiner proposes, the
claim’s additional elements, when considered individually and as an ordered
combination, integrate the abstract idea into a practical application. See
Guidance, 84 Fed. Reg. at 55 (citing MPEP § 2106.05(a)). Accordingly, the
claimed invention, when considered as a whole, is not directed to an abstract
idea and is, therefore, eligible under § 101. Because this issue is dispositive
regarding our reversing the Examiner’s ineligibility rejection, we need not
address whether any additional recited elements add significantly more to
the abstract idea to provide an inventive concept under Alice/Mayo step two.
Therefore, we are persuaded that the Examiner erred in rejecting
(1) independent claim 14; (2) independent claims 1, 15 and 16 that recite
commensurate limitations; and (3) the dependent claims for similar reasons.
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THE ANTICIPATION REJECTION
Regarding independent claim 1, the Examiner finds that Raveendran
discloses an encoder pipeline comprising a first processing module, namely
pre-processor 226, and one or more subsequent processing modules, namely
encoder 228. Final Act. 8–9. Raveendran is also said to disclose a pipeline
configurator, namely mode decision module 715, by providing information,
causes (1) the subsequent processing modules to enter a trigger mode, and
(2) the first module to adopt second encode parameters. Final Act. 9. The
Examiner adds that Raveendran’s first processing module, namely the pre-
processor 226, is configured to associate a trigger value with at least a first
media data block processed at the first module according to the second
encode parameters. Final Act. 9–10.
Appellant argues that Raveendran fails to disclose the recited pipeline
configurator functionality, as well as the first processing module’s recited
trigger value association functionality. Appeal Br. 11–16; Reply Br. 6–9.
According to Appellant, the Examiner’s rejection is deficient because,
among other things, the Examiner’s mapping various elements in
Raveendran to the recited processing modules and pipeline configurator is
inconsistent. Appeal Br. 15–16; Reply Br. 9–10.

ISSUE
Under § 102, has the Examiner erred in rejecting claim 1 by finding
that Raveendran discloses the functionality of the recited pipeline
configurator and first processing module?

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ANALYSIS
We begin by noting that claim 1 recites a media encoder with two
distinct structural elements, namely (1) an encoder pipeline, and (2) a
pipeline configurator. The encoder pipeline includes (1) a first processing
module, and (2) one or more subsequent processing modules, where (a) the
first processing module associates a trigger value with a first media data
block processed according to second encode parameters, and (b) the
subsequent processing modules adopt those parameters responsive to
receiving that value.
Turning to the rejection, the Examiner’s mapping these elements to
corresponding elements in Raveendran is not a model of clarity. For
example, the Examiner in the rejection and the Answer refers to the
functionality of mode decision module 715 in connection with the recited
pipeline configurator, yet also refers to transcoder control 231 in connection
with that element in the Final Rejection’s Response to Arguments—a
mapping that that was not articulated in the rejection itself nor repeated in
the Answer. Compare Final Act. 4 (mapping Raveendran’s transcoder
control 231 to the recited pipeline configurator in the Final Action’s
Response to Arguments) with Final Act. 9 (referring to Raveendran’s mode
decision module 715 in connection with the recited pipeline configurator in
the rejection); Ans. 8, 10 (referring to Raveendran’s mode decision module
715 in connection with the recited pipeline configurator’s parameter
switching functionality). Accord Appeal Br. 10–11 (noting this inconsistent
mapping).
Despite this inconsistency, we nevertheless presume that the
Examiner intended to map the pipeline configurator alternatively to either
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Raveendran’s mode decision module 715 or transcoder control 231, despite
the Examiner’s silence regarding the transcoder control mapping in the
rejection or the Answer.
For clarity, then, we summarize the Examiner’s mapping (see Final
Act. 4, 9–10; Ans. 8, 10–11) as follows:

Claim Element

Corresponding Element in
Raveendran

“first processing module”

pre-processor 226

“subsequent processing modules”

encoder 228

“pipeline configurator”

1. mode decision module 715
(Final Act. 9; Ans. 8, 10–11)

2. transcoder control 231
(Final Act. 4)

Based on this mapping, we agree with Appellant (Appeal Br. 11–16;
Reply Br. 6–10) that the Examiner’s anticipation rejection is problematic on
this record. As shown in Figure 1A, Raveendran discloses a transcoder 200
that (1) processes incoming multimedia data; (2) encodes that data; and
(3) prepares it for transmission. Raveendran ¶ 75. Raveendran’s transcoder
is detailed in Figure 2 reproduced below.

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Raveendran’s transcoder in Figure 2

As shown above, Raveendran’s transcoder includes pre-processor 226
that sends data to encoder 228, where the encoder includes first pass encoder
230, second pass encoder 232, and re-encoder 234. See Raveendran ¶¶ 93–
94, 181. Al
Based on this functionality, pre-processor 226 and encoder 228 that
correspond to the recited first and subsequent processing modules,
respectively, under the Examiner’s mapping, collectively correspond to an
“encoder pipeline” given the multiple processing units that work together to
complete a task consistent with the term’s commonly understood meaning in
the art as noted previously in connection with the written description
rejection.
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But the Examiner’s mapping the recited pipeline configurator to
Raveendran’s mode decision module 715 (Final Act. 9) is inconsistent with
the Examiner’s above-noted mapping for the modules of the recited encoder
pipeline—a pipeline whose constituent modules are separate and distinct
from the pipeline configurator under the terms of the claim.
Raveendran’s Figure 7 details encoder 228 that includes mode
decision module 715 that receives data from, among other things, slice/MB
ordering module 722 that likewise receives data from error resilience
module 740. See Raveendran ¶¶ 181–182, 205–207, 252. Raveendran’s
encoder 227 detailed in Figure 7 is reproduced below:

Raveendran’s encoder 228 in Figure 7

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As shown above, mode decision module 715 is part of encoder 228—
the very element that the Examiner maps to the subsequent processing
modules of the encoder pipeline. See Final Act. 9. In other words, the
Examiner maps a component of the subsequent module of the recited
encoder pipeline, namely encoder 228, to the pipeline configurator—a
separate and distinct element in the claim. Accord Appeal Br. 15–16; Reply
Br. 9 (noting this mapping inconsistency).
It is well settled that where, as here, a claim requires two separate
elements, namely an encoder pipeline and pipeline configurator, one element
construed as having two separate functions will not suffice to meet the
claim’s terms. See Lantech, Inc. v. Keip Mach. Co., 32 F.3d 542, 547 (Fed.
Cir. 1994); see also In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999)
(claims requiring three separate means not anticipated by structure
containing only two means using one element twice). Therefore, the
Examiner’s anticipation rejection based on the Examiner’s first pipeline
configurator mapping as corresponding to Raveendran’s mode decision
module 715 is problematic for that reason alone.
The Examiner’s mapping the recited pipeline configurator
alternatively to Raveendran’s transcoder control 231, however, is a closer
question. Still, we cannot say—nor has the Examiner shown—that the
transcoder control necessarily causes the subsequent processing modules,
namely the encoder 228 under the Examiner’s mapping, to enter a trigger
mode, where each such module adopts the second encode parameters
responsive to receiving the trigger value as claimed.
As the Specification explains, the pipeline configurator transmits
signals to the pipeline’s modules downstream from the first module (i.e., the
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subsequent modules) to enter a trigger mode such that they wait for a media
frame with an associated trigger flag indicating to the module to switch from
current to updated encode parameters. Spec. 12. The pipeline’s first module
also enters a mode where it adopts the updated encode parameters such that
the next frame is processed according to those parameters. Id. Upon
receiving a media frame with a trigger flag, the pipeline’s subsequent
modules immediately process that frame according to updated encode
parameters. See id.
Even assuming, without deciding, that the Examiner interprets the
recited trigger mode alternatively as a “best mode” or “providing
information” (Ans. 8), we fail to see—nor has the Examiner shown—how
Raveendran’s subsequent processing modules are necessarily caused to
enter a trigger mode when the claim is read in light of the Specification. As
the Specification explains, when modules enter a trigger mode, they wait for
a media frame with an associated trigger flag indicating to the module to
switch from current to updated encode parameters. Spec. 12.
To the extent that the Examiner finds that the first pass encoder 230’s
receiving data from transcoder control in Figure 2 somehow causes the
encoder 228 to enter a trigger mode (see Ans. 8), such an interpretation is
inconsistent with that mode’s description in the Specification and is,
therefore, improper. Although we recognize that we must not import
limitations from the Specification into the claims, we must nevertheless give
claims their broadest reasonable construction consistent with the
Specification. In re Suitco Surface, Inc., 603 F.3d 1255, 1260 (Fed. Cir.
2010); see also Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir. 2005)
(en banc). Where, as here, the Examiner’s construction is not only
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inconsistent with the Specification, but also the claim language when read as
a whole, the Examiner’s rejection based on that construction is erroneous.
In short, the Examiner fails to show that Raveendran’s transcoder
control necessarily causes the encoder 228 to enter a trigger mode—a crucial
requirement for inherent anticipation. See In re Robertson, 169 F.3d 743,
745 (Fed. Cir. 1999). Accordingly, we find the Examiner’s alternative
mapping of the recited pipeline configurator to Raveendran’s transcoder
control 231 problematic as well. To the extent that causing the subsequent
processing modules to enter a trigger mode would have been obvious in
view of Raveendran either alone or in combination with other prior art is a
question not before us, nor will we speculate in that regard here in the first
instance on appeal.
Therefore, we are persuaded that the Examiner erred in rejecting
(1) independent claim 1; (2) independent claims 14–16 that recite
commensurate limitations;8 and (3) the dependent claims for similar reasons.
Because this issue is dispositive regarding our reversing the Examiner’s
rejection of these claims, we need not address Appellant’s other associated
arguments.

8 Although independent claims 14 and 16 lack the recited pipeline
configurator, the recited switching functionality is nonetheless
commensurate with that of the pipeline configurator in claims 1 and 15.
Because the Examiner rejects claims 14 and 16 as anticipated for same
reasons as indicated in connection with the rejection claim 1 (Final Act. 15),
the Examiner’s anticipation rejection of claims 14 and 16 is problematic for
similar reasons.
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CONCLUSION
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/
Basis
Affirmed Reversed
1–14 112(b) Indefiniteness 1–14
1–16 101 Ineligibility 1–16
1–16 102(a)(1) Raveendran 1–16
Overall
Outcome
1–16

REVERSED