ACQIS LLC

Patent Trials and Appeals Board

Sep 20, 2021

IPR2021-00669 (P.T.A.B. Sep. 20, 2021)

Trials@uspto.gov Paper 8
571-272-7822 Entered: September 20, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

SAMSUNG ELECTRONICS CO., LTD. and
SAMSUNG ELECTRONICS AMERICA, INC.,
Petitioner,
v.
ACQIS LLC,
Patent Owner.
____________

IPR2021-00669
Patent RE44,654 E
____________

Before THU A. DANG, JONI Y. CHANG, and PATRICK M. BOUCHER,
Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
35 U.S.C. § 314

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I. INTRODUCTION
A. Background
Samsung Electronics Co., Ltd. and Samsung Electronics America,
Inc. (collectively, “Petitioner”) filed a Petition requesting an inter partes
review (“IPR”) of claims 14–31, 35, and 36 (“the challenged claims”) of
U.S. Patent No. RE44,654 E (Ex. 1001, “the ’654 patent”). Paper 3 (“Pet.”),
1. ACQIS LLC (“Patent Owner”) filed a Preliminary Response (Paper 7,
“Prelim. Resp.”).
Institution of an inter partes review may not be authorized “unless . . .
the information presented in the petition . . . and any response . . . shows that
there is a reasonable likelihood that the petitioner would prevail with respect
to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
Upon consideration of the Petition and the Preliminary Response, we
are not persuaded Petitioner demonstrated a reasonable likelihood of
prevailing in establishing unpatentability of the challenged claims of the
’654 patent. Accordingly, no trial is instituted.
B. Related Matters
The parties indicate that the ’654 patent is involved in Acqis LLC v.
Samsung Electronics Co., Ltd., No. 2:20-cv-00295 (EDTX); Acqis LLC v.
MITAC Holding Corporation, et al., No. 6:20-cv-00962 (WDTX); Acqis
LLC v. Inventec Corporation, No. 6:20-cv-00965 (WDTX); Acqis LLC v.
ASUSTek Computer Inc., No. 6:20-cv-00966 (WDTX); Acqis LLC v. Lenovo
Group Ltd., et al., No. 6:20-cv-00967 (WDTX); and Acqis LLC v. Wistron
Corporation, et al., No. 6:20-cv-00968 (WDTX). Pet. 1–2; Paper 5, 1–2.
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Petitioner also concurrently challenges claims of the ’654 patent in
IPR2021-00608.
C. The ’654 Patent
The ’654 patent, titled “Data Security Method and Device for
Computer Modules,” issued on December 17, 2013, from Application No.
13/649,078 (“the ’078 application”), filed on October 10, 2012, is a reissue
of Application No. 09/312,199 (“the ’199 application”), filed on May 14,
1999, now U.S. Patent No. 6,634,777 (“the ’777 patent”), and which is a
continuation of Application No. 13/562,210 (“the ’210 application”), filed
on July 30, 2012, which in turn is a continuation of Application No.
13/294,108 (“the ’108 application”), filed on November 10, 2011, now U.S.
Patent No. RE43,602 E (“the ’602 patent”), which in turn is a continuation
of Application No. 12/561,138 (“the ’138 application”), filed on September
16, 2009, now U.S. Patent No. RE42,984 E (“the ’984 patent”), which in
turn is a continuation of Application No. 11/545,056 (“the ’056
application”), filed on October 6, 2006, now U.S. Patent No. RE43,171 E
(“the ’171 patent”), which then in turn is a continuation of Application No.
11/056,604 (“the ’604 application”), filed on February 10, 2005, now U.S.
Patent No. RE41,092 E (“the ’092 patent”). Ex. 1001, codes (54), (45), (22),
(64), (63).
The ’654 patent generally relates to a technique for securing a
computer module in a computer system, which includes providing “a
security system for an attached computer module (‘ACM’),” wherein the
ACM is “insert[ed] into a computer module bay (CMB) within a peripheral
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console to form a functional computer.” Ex. 1001, 3:43−49. An illustration
of one embodiment of the ’654 patent’s computer system is depicted in
Figure 13, reproduced below.

Figure 13 shows a block diagram of a computer system using an
interface. Id. at 18:35−36. As shown in Figure 13, computer system 1300
includes ACM 1305 and peripheral console 1310. Id. at 18:37−42. ACM
1305 and peripheral console 1310 are interfaced through exchange interface
system (XIS) bus 1315. Id. at 18:42−44. XIS bus 1315, which is also
referred to as an interface channel, includes power bus 1316, video bus 1317
and peripheral bus (XPBus) 1318. Id. at 18:44−47.
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Peripheral controller interconnect (PCI) signals are encoded into
control bits and the control bits, rather than the control signals that they
represent, are transmitted on the interface channel. Id. at 17:20–24. At the
receiving end, the control bits representing control signals are decoded back
into PCI control signals prior to being transmitted to the intended PCI bus.
Id. at 17:24–26. The fact that control bits rather than control signals are
transmitted on the interface channel allows using a smaller number of signal
channels and a correspondingly smaller number of conductive lines in the
interface channel than would otherwise be possible. Id. at 17:27–31. This
relatively small number of signal channels used in the interface channel
allows using low voltage differential signal (LVDS) channels for the
interface. Id. at 15:59–63.
In an embodiment, the XP Bus includes bit lines (“[bit lines] PCK,
PD0 to PD3, and PCN”), which are unidirectional LVDS lines for
transmitting clock signals and bits (id. at 20:33–34) (emphasis omitted),
wherein “[a] bit based line (i.e., a bit line) is a line for transmitting serial
bits.” Id. at 20:66–67 (emphasis omitted). Bit based lines “typically
transmit bit packets and use a serial data packet protocol,” wherein examples
of bit lines include “an LVDS line, an IEEE 1394 line, and a Universal
Serial Bus (USB) line.” Id. at 20:67–21:3 (emphasis omitted).
A. Illustrative Claim
Of the challenged claims, claims 14, 17, 20, 23, 26, 29, and 35 are
independent. Claims 15 and 16 depend from claim 14; claims 18 and 19
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depend from claim 17; claims 21 and 22 depend from claim 20; claims 24
and 25 depend from claim 23; claims 27 and 28 depend from claim 26;
claims 30 and 31 depend from claim 29; and claim 36 depends from claim
35. Claim 17 is illustrative:
17. A method of increasing external peripheral data communication
speed of a computer, comprising:
providing an integrated Central Processing Unit (CPU) and graphics
controller in a single chip, on a printed circuit board of a computer;
providing digital video signals directly from the integrated CPU and
graphics controller;
connecting a first Low Voltage Differential Signal (LVDS) channel
directly to the peripheral bridge on the printed circuit board, the first
LVDS channel comprising two unidirectional, serial channels that
transmit data in opposite directions;
providing a connector for the computer that connects to a console;
providing a second LVDS channel to couple to the console through
the connector, the second LVDS channel comprising two
unidirectional, serial channels that transmit data in opposite
directions; and
enabling encoded address and data bits of a Peripheral Component
Interconnect (PCI) bus transaction to be conveyed in serial form over
the second LVDS channel to preserve the PCI bus transaction; and
enabling the PCI bus transaction to be conveyed serially through the
second LVDS channel to the console to improve peripheral data
communication speed between the computer and the console.
Ex. 1001, 23:4–29.
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B. Prior Art Relied Upon
Petitioner relies upon the references listed below (Pet. 5−6):
Name Reference Date Exhibit No.
Gulick U.S. Patent No. 6,690,676 B1 Feb. 10, 2004 1004
Goodrum U.S. Patent No. 5,822,571 Oct. 13, 1998 1006
McAlear U.S. Patent No. 6,389,029 B1 May 14, 2002 1007
Hart U.S. Patent No. 6,041,372 Mar. 21, 2000 1008

Petitioner also relies on the testimony of Stephen A. Edwards, Ph.D.
Ex. 1003. Patent Owner relies on, inter alia, the testimony of Marc E.
Levitt, Ph.D. Ex. 2001.
C. Asserted Grounds of Unpatentability
Petitioner asserts the following grounds of unpatentability (Pet. 6):
Claims Challenged 35 U.S.C. §1 References
17−19 103(a) Gulick, Goodrum (“Ground 1”)

1 For purposes of this Decision, we assume the challenged claims have an
effective filing date prior to March 16, 2013, the effective date of the Leahy
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Claims Challenged 35 U.S.C. §1 References
20–22 103(a) Gulick, Goodrum, McAlear (“Ground 2”)
14–16, 26, 27, 35, 36 103(a) Hart, Goodrum (“Ground 3”)
23–25, 28–34 103(a) Hart, Goodrum, McAlear (“Ground 4”)
II. ANALYSIS
A. Claim Construction
We construe each claim “in accordance with the ordinary and
customary meaning of such claim as understood by one of ordinary skill in
the art and the prosecution history pertaining to the patent.” 37 C.F.R.
§ 42.100(b) (2020). Under this standard, claim terms are generally given
their plain and ordinary meaning as would have been understood by a person
of ordinary skill in the art (POSITA) at the time of the invention and in the
context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d
1303, 1313 (Fed. Cir. 2005) (en banc).
Only those terms in controversy need to be construed, and only to the
extent necessary to resolve the controversy. See Nidec Motor Corp. v.
Zhongshan Broad Ocean Motor Co. Matal, 868 F.3d 1013, 1017 (Fed. Cir.
2017) (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795,
803 (Fed. Cir. 1999)).

Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011)
(“AIA”), and we apply the pre-AIA versions of 35 U.S.C. §§ 102, 103 and
112.
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Petitioner proposes a construction for “peripheral bridge.” Pet. 9–15.
Patent Owner proposes constructions for “terms reciting ‘serial’ data
transmission.” Prelim. Resp. 20. For purposes of this Decision, we find it
necessary to address only the claim terms identified below.
1. “serial form,” “serially,” “serial channels,” or “Universal Serial
Bus (USB) protocol” (all independent claims)
Independent claims 14, 17, 26, 29, 32, and 35 each require an LVDS
channel to convey “address and data bits of a [PCI] bus transaction in [a]
serial form” or a similar limitation. See, e.g., Ex. 1001, 22:56−59,
23:22−25, 24:33–35, 24:58–60, 15:17–19, 26:20–22 (emphasis added).
Independent claims 14, 17, 26, 29, 32 and 35 also recite an LVDS channel
comprises two “unidirectional, serial channels” that transmit data in
opposite directions. Id. at 22:47–49, 22:53–55, 23:13–15, 23:19–21, 24:26–
28, 24:52–54, 25:11–13, 26:14–16 (emphasis added). Independent claim 17
further recites that the PCI bus transaction is to be conveyed “serially”
through an LVDS channel. Id. at 23:26–29. Independent claims 20 and 23
further require an LVDS channel comprising a “unidirectional, serial
channels that transmit data” wherein “Universal Serial Bus (USB) protocol
data” is enabled to be conveyed. Id. at 23:43–45, 23:49–53, 23:67–24:2,
24:6–10 (emphasis added).
Petitioner does not propose express constructions for terms reciting
“serial” transmission (conveyance) of data. See generally Pet. However,
Patent Owner proposes that “terms reciting ‘serial’ data transmission have
an ordinary meaning,” wherein “[i]n data transmission, ‘serial’ means ‘one
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bit at a time on a single path.’” Prelim. Resp. 20 (quoting Ex. 2002, 11
(IEEE Dictionary) (defining “serial transmission”); citing Ex. 1001,
20:66−21:3 (“describing ‘bit based line’ ‘for transmitting serial bits’”); Ex.
2001 ¶ 76). Based on the evidence before us, we agree with Patent Owner’s
proposed claim construction. Ex. 1001, 20:66−21:3; Ex. 2001 ¶ 76; Ex.
2002, 9, 11.
In particular, Patent Owner’s proposed claim interpretation is
consistent with the term’s “ordinary and customary meaning.” Phillips, 415
F.3d at 1312−13. As Dr. Levitt testifies, the IEEE Dictionary similarly
defines “serialization” as “the process of transmitting coded characters one
bit at a time,” and defines “serial interface” as “[a]n interface that transmits
data bit by bit rather than in whole bytes.” Ex. 2001 ¶ 76 (citing Ex. 2002,
11) (alteration in original). Dr. Levitt further testifies that the IEEE
Dictionary indicates that “serial” means the opposite of “parallel”
transmission, which “transmits multiple bits simultaneously.” Id. (citing Ex.
2002, 9 (“defining ‘parallel transmission’ as ‘simultaneous transmission of
all the bits making up a character or byte where each bit travels on a
different path’ and contrasting to ‘serial transmission’”), 11 (“defining
‘serial transmission’ and contrasting to ‘parallel transmission’”)).
Further, Patent Owner’s proposed claim construction is also consistent
with the Specification. In particular, the Specification discloses that “[a] bit
based line (i.e., a bit line) is a line for transmitting serial bits,” and that “[b]it
based lines typically transmit bit packets and use a serial data packet
protocol.” Ex. 1001, 20:66−21:1 (emphasis omitted). The Specification
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also discloses that “[e]xamples of bit lines include an LVDS line, an IEEE
1394 line, and a Universal Serial Bus (USB) line.” Id. at 21:1−3 (emphasis
omitted).
In view of the foregoing, for purposes of this Decision, we adopt
Patent Owner’s proposed claim construction—namely, “[i]n data
transmission, ‘serial’ means ‘one bit at a time on a single path.’” Prelim.
Resp. 20. That is, we adopt Patent Owner’s proposed claim construction of
“serial” transmission or transmitting “serially” or transmitting via “serial
channels” to mean the opposite of “parallel” transmission, which “transmits
multiple bits simultaneously.” Id.; Ex. 2001 ¶ 76; Ex. 2002, 9, 11.
2. “graphics controller” (claims 17, 20)
Claims 17 recites “an integrated Central Processing Unit (CPU) and
graphics controller in a single chip” (Ex. 1001, 23:6−8), and claim 20 recites
“an integrated Central Processing Unit (CPU) and graphics controller on a
printed circuit board.” Id. at 23:38−40.
In its Petition, Petitioner does not expressly propose a construction for
the term “graphics controller.” See generally Pet. In its Preliminary
Response, referencing Dr. Levitt’s declaration, Patent Owner points out that
“[t]he ‘graphics controller’ of the ’654 patent has graphics processing
functionality and is not just a connection to a separate component for
processing graphics.” Prelim. Resp. 13 (citing Ex. 2001 ¶¶ 72–74). Patent
Owner contends that the ’654 patent’s Figure 19, for example, “shows an
exemplary embodiment with, inter alia, an integrated CPU and graphics
controller, which includes a ‘graphics accelerator.’” Id. Based on the
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evidence before us, we agree with Patent Owner that a “graphics controller”
has graphics processing functionality. Id.
Figure 20 of the ’654 patent, for example, further supports Patent
Owner’s contention and is reproduced below with yellow highlightings
added.

Figure 20 of the ’654 patent above shows an “Attached Computer
Module with Single Chip fully integrated: Integrated CPU with core logic,
Graphics Accelerator & Interface Controller” on a single chip 2025. Ex.
1001, Fig. 20, item 2025 (emphasis added). The Specification describes
Figure 20 as showing “an attached computer module with single chip [] fully
integrated: CPU, Cache, Core Logic, Graphics controller and Interface
controller.” Id. at 5:27−29; 19: 6−9, Fig. 20 (emphasis added). Hence, the
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’654 patent clearly equates a graphics controller with a graphics accelerator
(highlighted in yellow), which has graphics processing functionality. Id.
In light of the Specification and the evidence before us, we construe
“graphics controller” as a processing unit having graphics processing
functionality (e.g., producing graphical video output). See Phillips, 415 F.3d
at 1312−13; cf. In re Smith Int’l, Inc., 871 F.3d 1375, 1382−83 (Fed. Cir.
2017) (“The correct inquiry . . . is an interpretation that corresponds with
what and how the inventor describes his invention in the specification, i.e.,
an interpretation that is consistent with the specification.”).
3. “peripheral bridge” (claims 14, 17, 23, 26, 29, 32, 35)
Claims 14, 23, 26, 29, 32, and 35, each require connecting a CPU
“directly to a peripheral bridge” on a printed circuit board. See, e.g., Ex.
1001, 22:42−44.
Petitioner points out that U.S. Application No. 09/149,548 (now U.S.
Patent No. 6,216,185 (“the ’185 patent”) was “incorporated by reference into
the ’654 Patent,” but “[t]he ’185 patent repeatedly identifies only one
component as a ‘peripheral bridge’ – peripheral bridge 246” which “is
clearly labeled as a ‘south bridge.’” Pet. 10 (citing Ex. 1001, 5:63–67; Ex.
1010, 14:53–15:23. Fig. 7). According to Petitioner, “[c]onsistent with
classification as a ‘south bridge,’ the ‘[p]eripheral bridge 246 couples PCI
peripheral bus 241 with peripheral buses of other formats.” Id. at 11 (citing
Ex. 1010, 14:57–59; Ex. 1003 ¶ 53). Petitioner contends that bus
connections couple peripheral devices to the peripheral bridge. Id. (citing
Ex. 1010, 14:53–15:10, Fig. 7; Ex. 1003 ¶ 53).
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Petitioner takes the position that “[a] ‘peripheral bridge’ is not a north
bridge,” wherein the ’185 patent “makes a clear distinction” between the
north and south bridges. Pet. 13 (citing Ex. 1010, 7:1–3, Fig. 4; Ex. 1003
¶ 56). As Dr. Edwards testifies, a person of ordinary skill in the art would
have would have understood that the ’654 patent’s “peripheral bridge” is “a
component that interfaces with peripheral buses or peripheral devices,”
wherein “‘peripheral bridge’ is not a north bridge.” Ex. 1003 ¶¶ 55–56.
We credit Dr. Edwards’ testimony that the ’654 patent’s “peripheral
bridge” is not a north bridge, as it is consistent with the Specification and the
general knowledge of an ordinarily skilled artisan. See, e.g., Ex. 1001,
18:66−19:4, Figs. 18 (showing “North Bridge” as a component that links the
“CPU” to “Main Memory” and “Graphic Subsystem,” and “S[outh] Bridge”
as a component that connects to “PCI” and “Other” buses), 11–13.
Figure 12 of the ’654 patent is reproduced below:
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Figure 12 of the ’654 patent shows a peripheral console (PCON). Ex.
1001, 5:8–9. As shown in Figure 12, interface and support component 1240
of PCON functional circuitry 1201 comprises peripheral bridge 1246 (shown
as “South Bridge”) that couples PCI peripheral bus 1241 with peripheral
buses of other formats such as peripheral buses 1245, 1247.
Figure 18 of the ’654 patent is reproduced below:
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Figure 18 of the ’654 patent shows a computer system that includes
North Bridge 1805 being connected to a peripheral system that includes
South Bridge 1810. As shown, North Bridge 1805 is separate and distinct
from South Bridge 1810, wherein North Bridge 1805 links the “CPU” to
“Main Memory” and “Graphic Subsystem,” while South Bridge connects to
“PCI” and “Other” buses.
In light of the Specification and the evidence before us, for purposes
of this Decision, we construe, “peripheral bridge” as a bridge in a peripheral
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system that connects to PCI and other buses, and is not a “north bridge” in a
computer system that links a CPU to main memory and/or a graphic
subsystem. See Phillips, 415 F.3d at 1312−13.
B. Principles of Law
“In an [inter partes review], the petitioner has the burden from the
onset to show with particularity why the patent it challenges is
unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
petitions to identify “with particularity . . . the evidence that supports the
grounds for the challenge to each claim”)); see also 37 C.F.R. § 42.104(b)
(requiring a petition for inter partes review to identify how the challenged
claim is to be construed and where each element of the claim is found in the
prior art patents or printed publications relied on). Petitioner cannot satisfy
its burden of proving obviousness by employing “mere conclusory
statements.” In re Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed.
Cir. 2016).
A claim is unpatentable under 35 U.S.C. § 103 if the differences
between the claimed subject matter and the prior art are such that the subject
matter, as a whole, would have been obvious at the time the invention was
made to a person having ordinary skill in the art to which the subject matter
pertains. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 406 (2007). The
question of obviousness is resolved on the basis of underlying factual
determinations including (1) the scope and content of the prior art; (2) any
differences between the claimed subject matter and the prior art; (3) the level
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of ordinary skill in the art; and (4) objective evidence of nonobviousness.
Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
C. Level of Skill in the Art
In determining the level of ordinary skill in the art, various factors
may be considered, including the “type of problems encountered in the art;
prior art solutions to those problems; rapidity with which innovations are
made; sophistication of the technology; and educational level of active
workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir.
1995)(quoting Custom Accessories, Inc. v. Jeffrey–Allan Indus., Inc., 807
F.2d 955, 962 (Fed. Cir. 1986)). In that regard, relying on the declaration of
Dr. Edwards, Petitioner contends that a person of ordinary skill in the art at
the time of the ʼ654 patent’s invention would have had “at least a Master’s
Degree in, or a related subject, or a Bachelor’s Degree in electrical
engineering, computer science, or a related subject and three years of
experience working with computer architecture, computer busses, and
related technologies.” Pet. 9; Ex. 1003 ¶¶ 46–47.
In its Preliminary Response, Patent Owner does not dispute
Petitioner’s proposed the level of ordinary skill in the art. See Prelim.
Resp. 5. Based on the current record, for purposes of this Decision, we
apply Petitioner’s proposed level of ordinary skill in the art. We also note
that the prior art of record currently in the instant proceeding is consistent
with this level of ordinary skill in the art. See Okajima v. Bourdeau, 261
F.3d 1350, 1354–55 (Fed. Cir. 2001) (holding that absent evidence to the
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contrary, “the prior art itself reflects an appropriate level” of ordinary skill in
the art).
D. Obviousness Over Gulick and Goodrum
Petitioner alleges that claims 17−19 would have been obvious over
Gulick in view of Goodrum (Pet. 15–36); and that claims 20–22 would have
been obvious over Gulick and Goodrum, in further view of McAlear (id. at
36–49).
1. Gulick
Gulick, titled “Non-Addressed Packet Structure Connecting Dedicated
End Points on a Multi-Pipe Computer Interconnect Bus,” issued on February
10, 2004, from Application No. 09/330,635, filed on June 11, 1999. Ex.
1004, codes (54), (45), (21), (22). Gulick discloses a computer system
having a high speed communication link having multiple pipes operating on
the communication link. Id. at 1:15–18. In particular, Gulick discloses a
“multi-pipe interconnection bus [that] includes the ability to send a non-
addressed read or write transaction request over one of the pipes of a multi-
pipe computer interconnect bus.” Id., at code (57).
Figure 1 of Gulick is reproduced below.
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Gulick’s Figure 1 above (labeled “Prior Art”) illustrates a traditional
personal computer architecture that uses PCI bus 101 as a connection
between “north bridge” integrated circuit 103 and “south bridge” integrated
circuit 105. Id. at 1:20–31.
As shown in Figure 1, north bridge 103 functions generally as a
switch connecting CPU 107, graphics bus 109, PCI bus 101 and main
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memory 111. Id. at 1:26–63. North bridge 103 also contains a memory
controller function. Id.
In Figure 1, south bridge 105 generally provides the interface to the
input/output (I/O) portion of the system. Id. Specifically, south bridge 105
provides a bridge between PCI bus 101 and legacy PC-AT (Advanced
Technology) logic, also providing a bridge to legacy ISA bus 115, Integrated
Device Electronics (IDE) disk interface 117, and Universal Serial Bus
(USB) 119. Id. PCI bus 101 also functions as the major input/output bus for
add-in functions such as network connection 121. Id.
Gulick explains that the PCI bus in the prior art causes a lack of
determinism in the system because any function on the PCI bus can become
master of the bus and tie up the bus, wherein PCI bus load fluctuations can
result in uncertain and irregular quality of service. Id. Therefore, “having a
PCI bus as the major input/output bus means that the major input/output bus
of present day computer systems does not provide proper support for both
isochronous and asynchronous data.” Id.
Figure 3 of Gulick, illustrating a portion of a personal computer
system that utilizes a link to communicate between two integrated circuits, is
reproduced below (id. 3:7–9):

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Figure 3 of Gulick above shows a portion of a personal computer
system that utilizes a communication link. Id. As shown, link 205
communicates between processor module 301 and interface module 303. Id.
at 5:5−8. In the embodiment shown in Figure 3, link 205 has replaced a PCI
bus as the primary interface and also carries both isochronous and
asynchronous data. Id. at 5:15–20.
Bus 205 provides guaranteed bandwidth and latency to each
isochronous stream such as random access memory digital-to-analog
converter (RAMDAC) data, audio data, and IEEE 1394 isochronous streams
while also attempting to minimize latency to asynchronous accesses such as
central processing unit (CPU) initiated accesses and PCI initiated accesses.
Id. at 5:10−14.
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Processor module 301 includes link interface 305 which is coupled to
link interface 307 in interface module 303. Id. at 5:8−10. Processor module
301 provides the major process function in the computer system and
includes system memory controller 309, CPU 311, and graphics interface
306. Id. at 5:21−25. “Interface module 303 provides an interface between
various input/output devices such as video monitors, hard drives, scanners,
printers, network connections, modems, and the processor module.” Id. at
5:25−28.
2. Goodrum
Goodrum, titled “Synchronizing Data Between Devices,” issued on
October 13, 1998, from Application No. 659,142, filed on June 5, 1996. Ex.
1006, codes (54), (45), (21), (22). Goodrum discloses transmission of data
between a first device and a second device connected by the
communications channel in a computer system. Id. at code (57). In
particular, Goodrum relates to data synchronization, wherein data
“transferred over a compute bus is synchronized to a bus clock, which
ensures that devices connected to the bus receive valid data.” Id. at 1:6–9.
Figure 1 of Goodrum is reproduced below.
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Figure 1 above shows a block diagram of a computer system. Ex.
1006, 2:21. As shown in Figure 1, computer system 10 includes primary
PCI bus 24 interfaced to local bus 22 through system controller/host bridge
circuit 18 that controls access to system memory 20 coupled to local bus 22
along with CPU 14 and level two (L2) cache 16. Id. at 5:7–11. “PCI-
Extended Industry Standard Architecture (EISA) bridge 15 interfaces the
PCI bus 24 to an EISA bus 17 [coupled to] keyboard controller 21 and a
Read Only Memory (ROM) 23.” Id. at 5:12−15. “PCI bus 24 [] is coupled
to a bridge chip 26a and bridge chip 26b, wherein chip 26 is coupled to
bridge chip 48a through cable 31 and a bridge chip 26b . . . is coupled to the
bridge chip 48b through a cable 28.” Id. at 4:65–5:3.
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One type of cable 28 that can be used is a cylindrical 50-pair shielded
cable designed to support the High Performance Parallel Interface (HIPPI)
standard. Id. at 57:22−24. Twenty wire pairs of cable 28 are used for
downstream communication and twenty pairs for are used for upstream
communication. Id. at 58:8−9. For the remaining ten pairs in cable 28, error
detection and correction is not implemented. Id. at 58:10−14.
3. McAlear
McAlear, titled “Local Area Network Incorporating Universal Serial
Bus Protocol,” issued on May 14, 2002, from Application No. 09/188,297,
filed on November 10, 1998. Ex. 1007, codes (54), (45), (21), (22).
McAlear discloses local area networks (LAN) comprising a plurality of
outer hub devices connected to a LAN hub and a plurality of universal serial
bus (USB) devices and/or LAN computers connected to the plurality of outer
hub devices, the out end hubs communicating with the USB devices and
LAN computers using USB protocol. Id. at code (57). In one of the
embodiments, McAlear discloses that “LAN computer 130 can also
communicate with a USB device 100 or 180 by addressing the LAN hub 10
in the IP (or Ethernet) protocol and encapsulating the USB protocol within
the IP (or Ethernet) protocol,” i.e., “[a] plurality of USB packets destined to
the USB device 100 or 180 (“USB device packets”) are sent in a plurality of
IP (or Ethernet) packets.” Id. at 40:35-41.
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4. Analysis
a. Claims 17−19 over Gulick and Goodrum
(Ground 1)
i. “providing an integrated Central Processing Unit (CPU) and
graphics controller in a single chip” (claim 17)
As discussed above, claim 17 requires “an integrated Central
Processing Unit (CPU) and graphics controller in a single chip” (Ex. 1001,
23:6−8). By virtue of their dependency, dependent claims 18 and 19 also
require this limitation. As discussed above in our claim construction
analysis, we construe “graphics controller” as a processing unit having
graphics processing functionality (e.g., producing graphical video output).
In its Petition, Petitioner relies on Gulick’s “graphics interface 306” to
teach the claimed “graphics controller,” citing Dr. Edwards’ testimony for
support. Pet. 22−23 (citing Ex. 1004, 5:21–25, 23:54–57; Ex. 1003 ¶¶ 72–
73). However, as discussed above in our claim construction analysis, in the
context of the ’654 patent, a “graphics controller” is a processing unit having
graphics processing functionality (e.g., producing graphical video output),
and thus, not merely a graphics interface. As Dr. Levitt testifies, a person of
ordinary skill in the art would have recognized that a graphics interface is
not a graphic controller, because “the graphics interface is simply the
interface for connecting an external graphics processor to the processor
module,” wherein “[t]he graphics interface itself provides no actual graphics
processing functionality.” Ex. 2001 ¶ 72. We credit Dr. Levitt’s testimony
as it is consistent with the Specification and the general knowledge of an
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ordinarily skilled artisan. See, e.g., Ex. 1001, 7:4−17, 19:4−9, Figs. 3, 19,
20.
Furthermore, Gulick discloses that a graphics interface, such as
Advanced Graphics Port (AGP) interface, is separate and distinct from a
video/graphics processing unit. Figure 1 of Gulick is reproduced below
(with high-lightings added by Patent Owner). Prelim. Resp. 16.

Figure 1 of Gulick above shows north bridge 103 with AGP interface
(yellow) separate and distinct from the video/graphics processing unit (blue),
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the AGP interface and the video/graphics processing unit being connected
by graphics bus 109 (green). See Ex. 1004, 1:25−30.
We also note that Petitioner’s arguments are conclusory, not
supported by sufficient evidence. In particular, neither Petitioner nor
Dr. Edwards explains sufficiently how Gulick’s “graphics interface 306”
implements any graphics functions of a graphics controller. Pet. 22−23; Ex.
1003 ¶¶ 72–73. Instead, Dr. Edwards’ testimony merely states that Gulick
discloses “central processing unit (CPU) [311] . . . and graphics interface
306,” wherein “graphics interface 306 implements a graphics function on the
processor module 301,” without providing any explanation. Ex. 1003 ¶¶ 72–
73 (citing Ex. 1004, 5:21−25, 23:54−57, Fig. 3). Dr. Edwards’ testimony is
inconsistent with Gulick, conflating a graphics interface with a graphics
controller. See Ex. 1004, 5:21−25, 23:54–57, Fig. 3. As Patent Owner
points out, the portion of Gulick relied upon by Petitioner “is simply the
interface for connecting an external graphics processor to the processor
module,” wherein “the interface itself has no graphics processing
capability.” Prelim. Resp. 15.
In light of the foregoing, we determine that Petitioner fails to show
that the combination of Gulick and Goodrum teaches or suggests “an
integrated Central Processing Unit (CPU) and graphics controller in a single
chip,” as required by claims 17–19.
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ii. “unidirectional, serial channels that transmit data in opposite
directions,” enabling “address and data bits of a [PCI] bus
transaction to be conveyed in [a] serial form,” “the PCI bus
transaction to be conveyed serially” (claim 17)
As discussed above in our claim construction analysis, independent
claim 17 also requires LVDS channels comprising “two unidirectional,
serial channels that transmit data in opposite directions,” enabling “address
and data bits of a [PCI] bus transaction to be conveyed in [a] serial form”
over an LVDS channel, and enabling “the PCI bus transaction to be
conveyed serially” through the LVDS channel. Ex. 1001, 23:13–15
(emphasis added), 23:19−29 (emphasis added). By virtue of their
dependency, dependent claims 18 and 19 also require these respective
limitations. As discussed above in our claim construction analysis, we adopt
Patent Owner’s proposed claim construction of “serial” transmission or
transmitting “serially” or transmitting via “serial channels” to mean the
opposite of “parallel” transmission, which “transmits multiple bits
simultaneously.” Prelim. Resp. 20; Ex. 2001 ¶ 76; Ex. 2002, 9, 11.
In its Petition, Petitioner contends that Gulick discloses “[l]ink 205
[that] is used by the modules 301, 303 to e.g., convey PCI transactions,” but
acknowledges that “Gulick does not disclose the link 205 as comprising a
first LVDS channel or a first LVDS channel comprising two unidirectional,
serial channels that transmit data in opposite directions.” Pet. 28. Thus,
Petitioner relies on Goodrum to “explicitly” disclose “using LVDS signaling
over the cable,” and “operating in a serial mode.” Id. at 29 (citing Ex. 1006,
6:25−31, 57:45−49, 106:16−31). According to Petitioner, Goodrum
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discloses “conveying PCI transactions using differential signaling over a
cable (e.g., cable 28) connected between cable interfaces (e.g., interfaces
104, 130) of a PCI-to-PCI bridge,” and that “[t]wenty wire pairs of the cable
28 are used for downstream communication and 20 more for upstream
communication.” Id. at 28–29 (citing Ex. 1006, 4:65−5:6, 5:44−51,
6:25−27, 57:30−49, 58:8−9). According to Petitioner, a POSITA would
have understood that “Gulick’s link interface 305 and link 205 (and link
interface 307) could have been modified to incorporate Goodrum’s cable
interface, cable and LVDS signaling of PCI bus transaction.” Id. (citing Ex.
1003 ¶ 78).
Petitioner further explains that Goodrum discloses that transactions,
including PCI transactions, are encoded into multiple time-multiplexed
messages, wherein “60 bits are multiplexed onto 20 cable lines and are
transmitted each 10 ns over the cable 28.” Id. at 31 (citing Ex. 1006,
50:33−41, 55:14−16). According to Petitioner, “[t]hese bits include address
bits, data bits, and byte enable information bits of a PCI bus transaction.”
Id. (citing Ex. 1006, 55:25−31, 55:65−56:3, Fig. 15A).
Petitioner asserts that a POSITA would have understood that Gulick’s
link interface 305, link 205, link interface 307 could have been modified to
incorporate Goodrum’s “cable interface, cable and LVDS signaling of PCI
bus transactions to achieve a first, or any numbered . . . LVDS channel,
comprising a first unidirectional, differential signal pair to convey data in a
first direction and a second unidirectional, differential signal pair to convey
data in a second, opposite direction.” Id. at 32−33 (citing Ex. 1003 ¶ 83).
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In its Preliminary Response, Patent Owner counters that the Petition
does not establish a reasonable likelihood that Gulick or Goodrum discloses
“transmitting address or data bits ‘in serial form.’” Prelim. Resp. 19−24.
Patent Owner points out that “[t]he Petition does not assert that Gulick
discloses transmitting PCI bits in serial form” (id. at 20 (citing Pet. 25−29)),
and contends that “[t]he Petition does not identify anything in Goodrum
describing serial transmission of address and data bits.” Id. at 21. In fact,
according to Patent Owner, “Goodrum not only offers only a parallel cable,
it promotes using that parallel interface instead of ‘serial methods’ to
transmit address and data bits.” Id. at 23 (citing 2001 ¶ 79). We agree with
Patent Owner.
Although Petitioner cites to portions of Goodrum for teaching “a
serial mode” (Pet. 29 (citing Ex. 1006, 6:25−31, 106:16−31)), these portions
disclose transmitting “interrupts” in a serial mode, not address bits or data
bits of a PCI bus transaction, as required by the challenged claims at issue.
See Ex. 1006, 6:25−31 (describing “a serial stream” for interrupts),
106:16−31 (describing “serial mode” for “interrupt request signals” on
“interrupt request lines”).
Further, although Petitioner contends that Goodrum discloses PCI
transactions that are conveyed “using differential signaling over a cable
(e.g., cable 28) connected between cable interfaces (e.g., interfaces 104, 130)
of a PCI-to-PCI bridge” (Pet. 28–29), Goodrum discloses that such
differential signaling transmits signals in parallel over a “cable designed to
support the High Performance Parallel Interface (HIPPI) standard” and “the
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HIPPI cable specifications.” See Ex. 1006, 57:22−49, 58:8−14, Fig. 16
(emphasis added). That is, Goodrum makes clear that cable 28 is a “50 pair
HIPPI cable” (a parallel cable). See Ex. 1006, 57:22−24 (“a cylindrical 50-
pair shielded cable designed to support the High Performance Parallel
Interface (HIPPI) standard”), 58:10 (“the 50-pair HIPPI cable 28”). In other
words, the signals do not include address and data bits of a PCI bus
transaction conveyed “in a serial form” or “serially” or via “serial channels”
as required by the challenged claims at issue. Id.
As Patent Owner explains in its Preliminary Response, and as Dr.
Levitt testifies, Goodrum describes “only one embodiment for transmitting
address and data bits: a ‘cable designed to support the High Performance
Parallel Interface (HIPPI) standard,’” wherein “Goodrum teaches sending a
60-bit message—including address and data bits—over the parallel cable in
three time-multiplexed phases of 20 parallel bits each.” Prelim. Resp.
22−23; Ex. 2001 ¶ 79 (citing Ex. 1006, 52:22−45, 55:14−56:3, 57:22−48,
Figs. 14, 15A). In particular, “Goodrum promotes the benefits of its parallel
cable interface over ‘serial methods,’ such as fiber optics . . . to transmit
address and data bits.” Ex. 2001 ¶ 79 (citing Ex. 1006, 57:36−39 (“less
expensive than fiber optics for this short distance and less complex to
interface than other serial methods”)). Here, Petitioner’s reason to combine
Goodrum with Gulick (Pet. 20–21 (“less expensive, better noise immunity,
minimized EM radiation etc.”)) relies on those advantages disclosed in
Goodrum that are for transmitting data in parallel over a HIPPI cable, not for
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serial transmissions as required by the challenged claims at issue. See Ex.
1006, 57:30–44.
We credit Dr. Levitt’s testimony because it is consistent with
Goodrum’s disclosure and the general knowledge of an ordinarily skilled
artisan. See, e.g., Ex. 1006, , 55:14−56:3, 57:22−49, 58:8−14, Figs. 14, 15A
16; Ex. 2002, 9 (defining “parallel transmission” as “[s]imultaneous
transmission of all the bits making up a character or byte where each bit
travels on a different path” and contrasting to “serial transmission”), 11
(defining “serial transmission” as “one bit at a time on a single path” and
“serial interface” as “[a]n interface that transmits data bit by bit rather than
in whole bytes”).
More significantly, neither Petitioner nor Dr. Edwards explains why
one of ordinary skill in the art would have modified Goodrum’s “true
differential” signaling that transmits data in parallel over a HIPPI cable “to
convey address bits, data bits, and byte enable information bits of a [PCI]
bus transaction in a serial bit stream” or “in serial form” or “serially” as
required by the challenged claims at issue. Pet. 28−33; Ex. 1003 ¶¶ 78, 83.
In light of the foregoing, we determine that Petitioner fails to show
that the combinations based on Gulick and Goodrum disclose the above
mentioned “serial” transmission limitation, as required by claims 17–19.
iii. Conclusion on obviousness based on Gulick and Goodrum
For the reasons discussed above, we conclude that Petitioner has not
demonstrated a reasonable likelihood of prevailing in showing that claims
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17−19 are unpatentable under § 103(a) as obvious over Gulick and
Goodrum.
b. Claims 20–22 over Gulick and Goodrum, in
further view of McAlear (Ground 2)
Petitioner asserts that claims 20–22 are unpatentable under § 103(a) as
obvious over Gulick and Goodrum, in further view of McAlear (Pet. 36–49).
As discussed above in our claim construction analysis, similar to claim 17,
independent claim 20 requires, for example, “an integrated [CPU] and
graphics controller on a printed circuit board” (Ex. 1001, 23:38−40). By
virtue of their dependency, dependent claims 21 and 22 also require these
limitations.
Petitioner does not rely on McAlear to remedy the deficiencies
discussed above with respect to Ground 1, but rather relies upon its
arguments in Ground 1 with respect to Gulick. See Pet. 39–46. We already
addressed those arguments, and we find those arguments unavailing here for
the reasons stated above. In particular, we find that Petitioner fails to show
that the combinations based on Gulick and Goodrum disclose an “integrated
[CPU] and graphics controller on a printed circuit board,” as recited in the
claims.
On this record, we determine that Petitioner has not demonstrated a
reasonable likelihood of prevailing on its assertion that claims 20–22 are
unpatentable over Gulick and Goodrum in further view of McAlear.
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E. Obviousness Over Hart and Goodrum
Petitioner alleges that claims 14−16, 26, 27, 35, and 36 would have
been obvious over Hart and Goodrum (Pet. 49–67); and that claims 23–25,
and 28–34 would have been obvious over Hart and Goodrum, in further
view of McAlear (id. at 67–80).
1. Hart
Hart, titled “Method and Apparatus for Providing a Processor Module
for a Computer System,” issued on March 21, 2000, from Application No.
08/774,515, filed on December 30, 1996. Ex. 1008, codes (54), (45), (21),
(22). Hart discloses a “method and apparatus for converting a signal from a
first voltage level to a second voltage level before providing the signal to a
processor.” Id. at code (57). In particular, Hart discloses processor module
220 that “includes a circuit board containing processor 200, voltage
regulator 201, primary bridge A 203, clock 202, and associated signal lines
and interfaces.” Id. at 3:37−42. Figure 2 of Hart is reproduced below.
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Figure 2 above shows a block diagram of a computer system. Id. at
2:48–49. As shown, processor 200 is coupled to primary bridge 203 by way
of host bus 208. Id. at 3:49−50. Primary bridge 203 is also coupled to two
other buses, PCI bus 206 and memory bus 209. Id. at 3:53−58.
2. Analysis
a. Claims 14−16, 26, 27, 35, and 36 over Hart
and Goodrum (Ground 3)
Independent claims 14, 26 and 35 each requires “connecting a Central
Processing Unit (CPU) directly to a peripheral bridge on a printed circuit
board,” LVDS channels that comprise “two unidirectional, serial channels
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that transmit data in opposite directions,” and conveying “address and data
bits of a [PCI] bus transaction in serial form” over an LVDS channel. See,
e.g., Ex. 1001, 22:47–49, 22:53−63. By virtue of their dependency,
dependent claims 15, 16, 27, and 36 also require these limitations.
i. “connecting a Central Processing Unit (CPU) directly to a
peripheral bridge on a printed circuit board”
In its Petition, Petitioner relies on Hart’s “primary bridge [203]” to
teach the claimed “peripheral bridge,” citing Dr. Edwards’ testimony for
support. Pet. 53−54 (citing Ex. 1008, 3:37–56, 5:8–19, Fig. 2; Ex. 1003
¶¶ 121–122). However, as discussed above in our claim construction
analysis, we construe “peripheral bridge” as a bridge in a peripheral system
that connects to PCI and other buses, and is not a “north bridge” in a
computer system that links a CPU to main memory and/or a graphic
controller.
Here, Hart discloses that primary bridge 203 is included in processor
module that is connected a system memory. Ex. 1008, 3:36–48. As Patent
Owner points out, relying on Dr. Levitt’s testimony, “[a] POSITA would
recognize that in Hart Figure 2 . . . , the ‘primary bridge,’ . . . is a north
bridge, not a south bridge.” Prelim. Resp. 51 (citing Ex. 2001 ¶ 111).
According to Patent Owner, Hart’s primary bridge 203 “is used to connect
the processor 200 to memory 204, which indicates to a POSITA that bridge
[] 203 is a north bridge.” Id. In other words, primary bridge 203 “has all the
typical characteristics that a POSITA would recognize correspond to a north
bridge, which Petitioners contend is not the same as the claimed ‘peripheral
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bridge’ of the ’654 patent.” Id. at 51–52 (citing Ex. 2001 ¶ 111). We credit
Dr. Levitt’s testimony as it is consistent with the Specification and the
general knowledge of an ordinarily skilled artisan.
In light of our claim construction that “peripheral bridge” is not a
“north bridge” in a computer system that links a CPU to main memory
and/or a graphic subsystem,” we determine that Petitioner fails to show that
the combination of Hart and Goodrum teaches a “connecting a [CPU]
directly to a peripheral bridge on a printed circuit board,” as required by
claims 14−16, 26, 27, 35, and 36.
ii. LVDS channels that comprise “two unidirectional, serial
channels that transmit data in opposite directions,” and conveying
“address and data bits of a [PCI] bus transaction in serial form” over
an LVDS channel
As discussed above in our claim construction analysis, we adopt
Patent Owner’s proposed claim construction that, “[i]n data transmission,
‘serial’ means ‘one bit at a time on a single path,’” wherein “serial”
transmission means the opposite of “parallel” transmission.” Prelim. Resp.
20; Ex. 2001 ¶ 76; Ex. 2002, 9, 11.
In its Petition, Petitioner admits that Hart does not disclose “an LVDS
channel comprising two unidirectional, serial channels that transmit data in
opposite directions.” Pet. 55. Petitioner then relies on Goodrum to disclose
“conveying PCI transactions using differential signaling over a cable (e.g.,
cable 28) connected between cable interfaces (e.g., interfaces 104, 130) of a
PCI to PCI bridge,” and that “[t]wenty wire pairs of the cable 28 are used for
downstream communication and 20 more for upstream communication.” Id.
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(citing Ex. 1006, 4:65−5:6, 5:44−51, 6:25−27, 57:30−49, 58:8−9).
According to Petitioner, Goodrum teaches “using LVDS signaling over the
cable” and “operating in a serial mode.” Id. (citing Ex. 1006, 6:25−31,
57:45−49, 106:16−31).
Petitioner contends that Goodrum discloses “how to communicate PCI
bus transactions over LVDS links,” wherein it “is less expensive than fiber
optics,” is “less complicated to interface than other serial methods,”
“provides significant common mode noise immunity,” “is faster than TTL,”
“when using twisted pair and shielding, it minimizes electromagnetic
radiation,” and “when using low voltage swings, it minimizes power
dissipation.” Pet. 51–52 (quoting Ex. 1006, 57:37−45). Petitioner explains
that Goodrum discloses “encoding transactions, including PCI transactions,
into multiple time-multiplexed messages,” wherein “60 bits are multiplexed
onto 20 cable lines and are transmitted each 10 ns over the cable 28.” Id. at
57 (citing Ex. 1006, 50:33−41, 55:14−16). According to Petitioner, “[t]hese
bits include address bits, data bits, and byte enable information bits of a PCI
bus transaction.” Id. (citing Ex. 1006, 55:25−31, 55:65−56:3, Fig. 15A).
Petitioner asserts that a POSITA would have understood that “Hart’s link
primary bridge 203 and socket interface 223 could have been modified to
incorporate Goodrum’s cable interface, cable and LVDS signaling of [a] PCI
bus transaction.” Id. at 55 (citing Ex. 1003 ¶ 125).
In its Preliminary Response, Patent Owner counters that the
combination of Hart and Goodrum does not disclose conveying “address and
data bits. . . in serial form.” Prelim. Resp. 53. Patent Owner points out that
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“[t]he Petition does not assert that Hart discloses conveying PCI bits in serial
form” (id. at 53–54 (citing Pet. 57–59) (“addressing Hart’s alleged
contributions to claim limitation without mentioning serial transmission”),
and also avers that Goodrum does not disclose “conveying any address or
data bits ‘in serial form’ either.” Id. We agree with Patent Owner.
As we discussed above, the portions of Goodrum cited by Petitioner
for support to teach “a serial mode” (Pet. 29) disclose transmitting
“interrupts,” not for address or data bits of a PCI bus transaction, as required
by the challenged claims at issue. See Ex. 1006, 6:25−31, 106:16−31. In
addition, Goodrum’s differential signaling, relied upon by Petitioner (Pet.
29), transmits signals in parallel over a “cable designed to support the High
Performance Parallel Interface (HIPPI) standard” and “the HIPPI cable
specifications,” not “in a serial bit stream” or “in serial form” as required by
the challenged claims at issue. See Ex. 1006, 57:22−49, 58:8−14, Fig. 16
(emphasis added). Goodrum makes clear that cable 28 is a “50 pair HIPPI
cable.” Id. at 57:22−24, 58:10.
Neither Petitioner nor Dr. Edwards explains why one of ordinary skill
in the art would have modified Goodrum’s “true differential” signaling that
transmits data in parallel over a HIPPI cable to convey “address and data bits
of a PCI bus transaction in serial form,” as required by claims 14−16, 26, 27,
35, and 36. Pet. 50–51, 54−55; Ex. 1003 ¶¶ 113–115, 125. Petitioner’s
reason to combine Goodrum with Hart relies on those advantages disclosed
in Goodrum that are for transmitting data in parallel over a HIPPI cable, not
for serial transmissions as required by the challenged claims at issue. Id.
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In light of the foregoing, we determine that Petitioner fails to show
that the combination of Hart and Goodrum discloses the above-mentioned
“serial transmission” limitation, as required by claims 14−16, 26, 27, 35, and
36.
iii. Conclusion on obviousness based on Hart and Goodrum
For the reasons discussed above, we conclude that Petitioner has not
demonstrated a reasonable likelihood of prevailing in showing that claims
14−16, 26, 27, 35, and 36 are unpatentable under § 103(a) as obvious over
Hart and Goodrum.
b. Claims 23–25 and 28–34 over Hart, Goodrum, and
McAlear (Ground 4)
Petitioner asserts that claims 23–25 and 28–34 are unpatentable under
§ 103(a) as obvious over Hart and Goodrum, in further view of McAlear
(Pet. 67–80). As discussed above in our claim construction analysis, similar
to claims 14, 26 and 35, independent claims 23, 29, and 32 each requires
“connecting a Central Processing Unit (CPU) directly to a peripheral bridge
on a printed circuit board” (see, e.g., Ex. 1001, 23:63−65). By virtue of their
dependency, dependent claims 24, 25, 28, 30, 31, 33, and 34 also require
these limitations.
Petitioner does not rely on McAlear to remedy the deficiencies
discussed above with respect to Ground 3, but rather relies upon its
arguments in Ground 3 with respect to Hart. See Pet. 68. We already
addressed those arguments, and we find those arguments unavailing here for
the reasons stated above. In particular, we find that Petitioner fails to show
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that the combinations based on Hart and Goodrum disclose an “integrated
[CPU] and graphics controller on a printed circuit board,” as recited in the
claims.
On this record, we determine that Petitioner has not demonstrated a
reasonable likelihood of prevailing on its assertion that claims 23–25 and
28–34 are unpatentable over Hart and Goodrum in further view of McAlear.
III. CONCLUSION
For the foregoing reasons, we conclude that Petitioner has not
demonstrated a reasonable likelihood of prevailing with respect to at least
one claim of the ’654 patent challenged in the Petition.
IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that the Petition is denied as to all challenged claims of
the ’654 patent, and no trial is instituted.

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FOR PETITIONER:

Gianni Minutoli
Harpreet Singh
Alan Limbach
DLA PIPER LLP (US)
gianni.minutoli@dlapiper.com
harpreet.singh@dlapiper.com
alan.limbach@dlapiper.com

FOR PATENT OWNER:
Cyrus Morton
Derrick Carman
ROBINS KAPLAN LLP
cmorton@robinskaplan.com
dcarman@robinskaplan.com