VMware, Inc.Download PDFPatent Trials and Appeals BoardFeb 11, 20222021000029 (P.T.A.B. Feb. 11, 2022) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 16/048,180 07/27/2018 Irina CALCIU E243.01 3124 152569 7590 02/11/2022 Patterson + Sheridan, LLP - VMware 24 Greenway Plaza Suite 1600 Houston, TX 77046 EXAMINER MERCADO, RAMON A ART UNIT PAPER NUMBER 2132 NOTIFICATION DATE DELIVERY MODE 02/11/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ipadmin@vmware.com psdocketing@pattersonsheridan.com vmware_admin@pattersonsheridan.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte IRINA CALCIU, JAYNEEL GANDHI, AASHEESH KOLLI, and PRATAP SUBRAHMANYAM ____________ Appeal 2021-000029 Application 16/048,180 Technology Center 2100 ____________ Before CAROLYN D. THOMAS, AMBER L. HAGY, and MICHAEL J. ENGLE, Administrative Patent Judges. THOMAS, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1-20. See Claims App. We have jurisdiction over the appeal under 35 U.S.C. § 6(b). We AFFIRM. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as VMware, Inc. Appeal Br. 3. Appeal 2021-000029 Application 16/048,180 2 The present invention relates generally to tracking dirty cache lines by monitoring cache coherence events. See Spec. ¶ 3. Claim 1, reproduced below with disputed limitations emphasized, is representative: 1. A method for tracking dirtiness of data in memory, the method comprising: monitoring cache coherence events for a cache occurring on a coherence interconnect that is connected to monitoring hardware comprising a memory and processing hardware, the processing hardware including the cache; determining, based on the monitoring, that data in a page of the memory is dirty, wherein the data is of a fixed size corresponding to a size of a cache line of the cache; and adding a representation of the data to a buffer to indicate that the data is dirty. REFERENCES The references relied upon by the Examiner are: Name Reference Date Baumgartner US 6,275,907 B1 Aug. 14, 2001 Subrahmanyam US 2010/0274987 A1 Oct. 28, 2010 Hendry US 2011/0252200 A1 Oct. 13, 2011 Philip US 2015/0052309 A1 Feb. 19, 2015 Kaxiras US 2016/0321181 A1 Nov. 3, 2016 REJECTIONS R1. Claims 1-4, 8-11, and 14-17 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Kaxiras, Philip, and Hendry. Final Act. 3-6. R2. Claims 5, 6, 12, 18, and 19 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Kaxiras, Philip, Hendry, and Baumgartner. Final Act. 6-7. Appeal 2021-000029 Application 16/048,180 3 R3. Claims 7, 13, and 20 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Kaxiras, Philip, Hendry, and Subrahmanyam. Final Act. 7-8. We review the appealed rejections for error based upon the issues identified by Appellant, and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). ANALYSIS Claims 1-6, 8-12, and 14-19 Appellant contends that the “claims involve tracking dirtiness of data in memory - not ownership of data in memory. Hendry does not describe determining dirtiness of data in memory, let alone . . . memory that ‘is of a fixed size corresponding to a size of a cache line of the cache.’” Appeal Br. 8. In response, the Examiner finds that “Kaxiras explicitly teaches monitoring cache coherent events on hierarchical memory systems . . . [and] that [callback] CB directory may be used to track/[monitor] coherent accesses at different granularities.” Ans. 4, citing Kaxiras ¶¶ 32-33. In other words, the Examiner is relying on Kaxiras to teach and/or suggest monitoring coherent events. Furthermore, the Examiner finds that Philip “may be configured to track coherent address lines . . . and can further be configured to store coherence state of the cache line as to whether the line is . . . dirty.” Ans. 5, citing Philip ¶ 78. Therefore, the Examiner is relying on the combined teachings of Kaxiras and Philip to teach monitoring coherent events on a cache and based on the monitoring determining that a cache line is dirty. See Ans. 5. Appeal 2021-000029 Application 16/048,180 4 The Examiner imports Hendry merely to teach “cache coherence . . . at a memory line granularity,” “a ‘memory region’ is a group of memory larger than a single cache line (e.g., two cache lines, a page, etc.),” and “tracking the coherent events at the page level of granularity.” Ans. 5, citing Hendry ¶¶ 21, 34, 39. Thus, it is the combined teachings of Kaxiras, Philip, and Hendry, not just Hendry alone, that the Examiner is relying on to teach the claimed determining that data in a page of the memory is dirty, wherein the data is of a fixed size corresponding to a size of a cache line of the cache. Therefore, Appellant’s argument against Hendry separately from Kaxiras and Philip does not persuasively rebut the combination made by the Examiner. One cannot show non-obviousness by attacking references individually, where the rejections are based on combinations of references. In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986); In re Keller, 642 F.2d 413, 425-26 (CCPA 1981). Appellant’s arguments do not take into account what the collective teachings of the prior art would have suggested to one of ordinary skill in the art and is therefore ineffective to rebut the Examiner’s prima facie case of obviousness. Accordingly, we sustain the Examiner’s rejection of claim 1. Appellant’s arguments regarding the Examiner’s rejection of independent claims 8 and 14 rely on the same arguments as for claim 1, and Appellant does not argue separate patentability for the dependent claims, except as noted below. See Appeal Br. 7-8. We, therefore, also sustain the Examiner’s rejection of claims 2-6, 8-12, and 14-19. Appeal 2021-000029 Application 16/048,180 5 Claims 7, 13, and 20 Appellant contends that “determining a modification to a ‘page table entry’ in Subrahmanyam is different than tracking cache lines of ‘one or more specified pages’ as recited in Appellant’s claims.” Appeal Br. 9 (emphasis omitted). In the Answer, the Examiner clarifies that he/she is not relying on Subrahmanyam to teach “tracks cache lines of one or more specified pages” (see Ans. 6-7), rather the Answer states that the combined “Kaxiras/Philip[]/Hendry clearly teach tracking cache lines of one or more specified pages.” Id. at 7. Consequently, Appellant fails to rebut the combined teachings of Kaxiras/Philip/Hendry, and only targets Subrahmanyam’s teachings. Here, the Examiner appears to be importing Subrahmanyam to merely teach adding an entry to the buffer if the dirty cache line is included. See Ans. 7-8. For example, Subrahmanyam discloses updating or invalidating of the corresponding entry in the corresponding cache by changing the priority bits in the shadow page tables. See Subrahmanyam ¶¶ 21, 49, 56. Additionally, the Examiner also relies on Philip to teach “adding a representation of the data to a buffer to indicate that the data is dirty.” See Final Act. 5 (emphasis omitted) (Philip ¶ 78 (“The directory table may be configured to track coherent address lines in the system. The table can be configured to store coherent cache line addresses and a vector of agents sharing the line . . . [and] as to whether the line is . . . dirty.”)). Here, Appellant’s Specification discloses that “[i]f module is tracking the cache lines of the page, then in step 272 module 252 adds a Appeal 2021-000029 Application 16/048,180 6 representation of the cache line, such as an address or the setting of a bit in a bit map, to DCL-Buf 254.” Spec. ¶ 22. Consistent with Appellant’s Specification, we find that the combination of Subrahmanyam, Philip, Kaxira, and Hendry teaches and/or suggests adding an entry to the buffer if the dirty cache line is included in one of the specified pages. Thus, Appellant’s aforementioned argument, which only disputes Subrahmanyam teachings, is unavailing given the Examiner’s reliance upon the combined teachings. As such, Appellant’s argument against Subrahmanyam separately from the other cited references does not persuasively rebut the combination made by the Examiner. Again, one cannot show non-obviousness by attacking references individually, where the rejections are based on combinations of references. In re Keller, 642 F.2d at 425-26. Accordingly, we sustain the Examiner’s rejection of claim 7, and also of claims 13 and 20 for similar reasons. CONCLUSION The Examiner’s rejections R1-R3 of claims 1-20 as being unpatentable under 35 U.S.C. § 103 are affirmed. Appeal 2021-000029 Application 16/048,180 7 In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-4, 8-11, 14-17 103 Kaxiras, Philip, Hendry 1-4, 8-11, 14-17 5, 6, 12, 18, 19 103 Kaxiras, Philip, Hendry, Baumgartner 5, 6, 12, 18, 19 7, 13, 20 103 Kaxiras, Philip, Hendry, Subrahmanyam 7, 13, 20 Overall Outcome 1-20 No period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Copy with citationCopy as parenthetical citation