Toshiba Corporation et al.v.Intellectual Ventures II LLC

Patent Trial and Appeal Board

May 21, 2014

09671554 (P.T.A.B. May. 21, 2014)

Trials@uspto.gov Paper 11
Tel: 571-272-7822 Entered: May 21, 2014

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________
TOSHIBA CORPORATION; TOSHIBA AMERICA, INC.;
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.; AND
TOSHIBA AMERICA INFORMATION SYSTEMS, INC.
Petitioner
v.
INTELLECTUAL VENTURES II LLC
Patent Owner
_______________

Case IPR2014-00201
Patent 6,618,788
_______________

Before KEVIN F. TURNER, TREVOR M. JEFFERSON,
and DAVID C. MCKONE, Administrative Patent Judges.

MCKONE, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
37 C.F.R. § 42.108

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I. INTRODUCTION
A. Background
Toshiba Corporation, Toshiba America, Inc., Toshiba America
Electronic Components, Inc., and Toshiba America Information Systems,
Inc. (collectively “Petitioner”) filed a Corrected Petition (Paper 8, “Pet.”) to
institute an inter partes review of claims 1-27 of U.S. Patent No. 6,618,788
(Ex. 1001, “the ’788 patent”). See 35 U.S.C. § 311. Intellectual Ventures II
LLC (“Patent Owner”) filed a Preliminary Response (Paper 10, “Prelim.
Resp.”).
The standard for instituting an inter partes review is set forth in
35 U.S.C. § 314(a), which provides as follows:
THRESHOLD.—The Director may not authorize an inter partes
review to be instituted unless the Director determines that the
information presented in the petition filed under section 311
and any response filed under section 313 shows that there is a
reasonable likelihood that the petitioner would prevail with
respect to at least 1 of the claims challenged in the petition.
We determine that the record before us does not demonstrate that
there is a reasonable likelihood that Petitioner would prevail with respect to
at least one challenged claim. We consequently deny the petition and
decline to institute an inter partes review of the ’788 patent.

B. Related Matters
Patent Owner has asserted the ’788 patent against Petitioner in
Intellectual Ventures I LLC and Intellectual Ventures II LLC v. Toshiba
Corporation et al., Case No. 1:13-cv-00453 (D. Del.). Pet. 1; Paper 4 at 2.

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C. References Relied Upon
Petitioner relies upon the following prior art references:
Ex. 1003 Bastiani US 6,609,167 B1 Aug. 19, 2003
(filed Mar. 15, 2000)
Ex. 1005 McDonald US 6,421,760 B1 July 16, 2002
(filed Apr. 26, 2000)
Ex. 1006 Clay US 5,465,338 Nov. 7, 1995

D. The Asserted Grounds
Petitioner contends that the challenged claims are unpatentable based
on the following specific grounds (Pet. 7):
References Basis Claims challenged
Bastiani § 102(e) 1, 9, 10, 17-20, 22, 24
Bastiani § 103(a) 1-27
Bastiani and McDonald § 103(a) 7, 16, and 21
Bastiani and Clay § 103(a) 23

II. ANALYSIS
A. The ’788 Patent
The ’788 patent is directed to techniques for communicating over a
serial communication connection, such as a universal serial bus (“USB”),
between a computer host and a remote device that conforms to one or more
of the Advanced Technology Attachment (“ATA”) standards. Ex. 1001,
Abstract. The ATA standards are promulgated by the American National
Standards Institute (“ANSI”) and define the physical, electrical, transport,
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The host communicates with the ATA device by accessing, reading
from, and writing to registers on the ATA device. Id., col. 1, l. 61-col. 2,
l. 23. For example, the ATA device executes register-driven commands
from the host when those commands are written to the ATA device’s
“COMMAND” register. Id. at col. 2, ll. 1-9. The host includes a register-
based ATA host driver that formats ATA register accesses into ATA
command blocks, which are packets. Id. at col. 4, ll. 11-14; col. 5, ll. 57-63;
Fig. 7. The command blocks are sent from the host to the bridging circuit.
Id. at col. 4, ll. 14-15; col. 5, l. 64-col. 6, l. 6; col. 6, ll. 26-34. At the
bridging circuit, a controller receives an ATA command block, recognizes it
as a command block, and parses it into a sequence of ATA register accesses.
Id. at col. 6, ll. 7-14; Fig. 7. The controller then delivers the ATA register
access sequence to an ATA register protocol adapter for execution. Id. at
col. 6, ll. 14-15; Fig. 7. The ATA register protocol adapter contains the
functionality for communicating asynchronously with the ATA device.
Id. at col. 6, ll. 20-22.
When a given ATA register-delivered transaction requests the values
stored in one or more of the ATA device’s registers, the bridging circuit
sends those values to the host in a packet format. Id. at col. 4, ll. 20-23.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method of controlling an ATA device using
packet-based communication between a host and a packet-to-
ATA bridge, the method comprising
at the host:
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formatting the ATA register accesses necessary to
execute a given ATA register-delivered
transaction into a command block; and
transmitting the command block to the packet-to-
ATA bridge in a packet format, and
at the packet-to-ATA bridge:
parsing the command block into a sequence of
ATA operations necessary to execute the
given ATA register-delivered transaction;
communicating with an ATA device attached to
the bridge via an ATA interface to execute
the sequence of ATA operations on the ATA
device; and
when the given ATA register-delivered transaction
requests the values for one or more registers
on the ATA device, returning the register
values to the host in packet format.

B. Claim Construction
As a step in our analysis for determining whether to institute a trial,
we determine the meaning of the claims. The Board interprets claims using
the broadest reasonable construction. See 37 C.F.R. § 100(b); Office Patent
Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012). Claim
terms generally are given their ordinary and customary meaning, as would
be understood by one of ordinary skill in the art in the context of the entire
disclosure. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed.
Cir. 2007).

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1. “parse” / “parsing”
Neither party proposes an express construction of “parse” or
“parsing.” However, Petitioner contends that a component in Bastiani
“parses or breaks down” an ATA command into a standard sequence of
ATA operations. Pet. 16. Thus, Petitioner implicitly proposes construing
“parse” to mean break down into constituent parts.
An ordinary meaning of “parse” is:
To resolve a request or response into component parts. In the
context of messages, a device can break the message into
pieces, each of which consists of a header and sometimes some
corresponding data. If a device is able to parse a message, it
can recognize each piece of a message. It does not necessarily
make use of the data found in that message. However, it shall
make any confirmation responses or other responses that the
message requires.
IEEE 100, THE AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS
795 (7th ed. 2000) (Ex. 3001). The specification describes parsing
consistently with breaking down a larger block into its component parts. For
example, the ’788 patent explains that “[t]he bridge parses the command
block into a sequence of ATA operations necessary to execute the given
ATA register-delivered transaction.” Ex. 1001, col. 4, ll. 15-17. Similarly,
the patent explains that “[w]hen controller 166 receives an ATA command
block, it recognizes the command block as such, checks it for
inconsistencies, and parses it into a sequence of ATA register accesses.”
Id. at col. 6, ll. 11-14. Accordingly, on this record, “parse” means to break
down a data packet or block into its component parts.

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Id. at col. 3, ll. 63-65. According to Petitioner’s declarant, Thomas Gardner,
the terms IDE and ATA are interchangeable. Ex. 1007 ¶ 11 (citing
MICROSOFT COMPUTER DICTIONARY 33 (4th ed. 1999) (Ex. 1004)). For
purposes of this decision, we accept the argument that IDE and ATA are
interchangeable.
IDE device 122 and ASP Adapter 118 are connected through standard
IDE parallel cable 120 and are enclosed within enclosure 116. Ex. 1003,
col. 6, ll. 44-47. ASP Adapter 118 is connected via serial bus 110 to host
adapter 104, which connects to the motherboard of host 102 through a
Peripheral Component Interconnect (“PCI”) interface. Id. at col. 6, ll. 20-28.
The host creates a Command Descriptor Block (“CDB”) with an ATA
command and stores it in memory. Id. at col. 49, ll. 13-15; col. 50, ll. 16-23.
The host then communicates the ATA Command to the IDE device by
sending the ATA Command packaged in a packet (an “OUTDATA0/1
packet”). Id. at col. 41, ll. 23-27; col. 50, ll. 24-26. The packet is sent over
serial bus 110 to ASP Adapter 118. Id. at col. 42, ll. 6-10. After IDE device
122 executes the ATA command, the device returns its status to the host in a
packet (a “DATA0/1 packet”). Id. at col. 41, ll. 27-31.

2. Claim 1
Regarding claim 1, Petitioner contends that Bastiani’s host computer
is a host, its IDE device is an ATA device, and its ASP Adapter is a packet-
to-ATA bridge. Pet. 13-15. Petitioner further contends that Bastiani’s
creation of CDBs is formatting ATA register accesses necessary to execute a
given ATA register-delivered transaction into a command block (Pet. 15-
16), and that Bastiani’s transmission of an OUTDATA0/1 packet is
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transmitting the command block to the packet-to-ATA bridge in a packet
format (Pet. 16). Petitioner also argues that Bastiani’s returning the
DATA0/1 packets to the host constitutes returning the register values to the
host in packet format.
The parties dispute whether Bastiani discloses claim 1’s “parsing the
command block into a sequence of ATA operations necessary to execute the
given ATA register-delivered transaction.” Petitioner argues that Bastiani’s
ASP Adapter “parses or breaks down” the ATA Command sent in the
OUTDATA0/1 packet into a standard sequence of ATA operations. Pet. 16.
Petitioner (Pet. 17) cites Bastiani (Ex. 1003) at column 42, lines 6-16, which
states:
The ASP protocol implements a serial transport mechanism and
the commands and status that are passed are the normal
ATA/ATAPI1 commands that are currently used with the
parallel version of ATA/ATAPI. ATA/ATAPI commands are
sent across the ASP bus by the transport mechanism and it is up
to the device to execute these commands in a similar manner to
what is done today. The code used to execute these commands
should remain identical for all devices. The user should consult
the current version of the X310 document on AT Attachement-
3 Interface for a complete listing of the commands and
responses that the device uses.
Petitioner argues that the ASP Adapter connects to the IDE device by a
standard IDE cable; therefore it is sending ATA register-delivered
transactions to the IDE device. Pet. 16-17. According to Petitioner, because

1 According to the ’788 patent, AT Attachment with Packet Interface
Extension (“ATAPI”) specifies a method for controlling a storage device
over an ATA bus using packet-delivered commands. Ex. 1001, col. 2,
ll. 31-33.
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the ASP Adapter receives the ATA commands in packets sent by the host
over the ASP cable, “the ASP ADAPTER must parse or break down the
ATA Command contained in the OUTDATA0/1 packets into [a] standard
sequence of ATA operations and the ASP ADAPTER then causes those
operations to occur by accessing ATA registers on the IDE device.”
Id. at 17. Petitioner relies on its declarant, Mr. Gardner, to support this
argument. Id. (citing Ex. 1007 ¶¶ 23-25).
Mr. Gardner seeks to show the technical details of Bastiani’s ASP
Adaptor through comparison of Bastiani’s system with that described in the
’788 patent. According to Mr. Gardner, Bastiani’s IDE device 122 is
“identical” to the ATA device described in the ’788 patent. Ex. 1007 ¶ 24.
Mr. Gardner argues that the connectors and the signals carried over
Bastiani’s standard IDE cable must be identical to those of connector 152 of
the ’788 patent because both the IDE cable and the connector comport to the
same standard. Id. Because their connectors and signals are identical,
Mr. Gardner continues, the ASP Adapter sends standard ATA commands to
the registers of a device so that the device can perform register-delivered
transactions, just as the ’788 patent’s bridging circuit does. Id. Mr. Gardner
then concludes that, because both Bastiani’s ASP Adapter and the
’788 patent’s bridging circuit receive packets containing an ATA Command
Block over a serial cable, Bastiani’s ASP Adapter must parse those packets
into sequences of ATA operations in the same manner as the ’788 patent’s
bridging circuit. Id.
Patent Owner contends that Bastiani does not disclose explicitly the
parsing limitation of claim 1. Prelim. Resp. 5. Rather, Patent Owner argues,
Bastiani merely describes passing commands across the ASP bus to be
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executed by the IDE device without describing any parsing. Id. at 6. We
agree. The portion of Bastiani cited by Petitioner describes transmitting
ATA commands across an ASP bus to a “device.” 2 Petitioner, however, has
not identified persuasively where Bastiani describes the details of how the
device processes the ATA commands once it receives them or whether it
breaks down a packet into component parts. Rather, Bastiani simply states
that “it is up to the device to execute these commands in a similar manner to
what is done today.” Ex. 1003, col. 42, ll. 11-12.
Patent Owner also argues that Petitioner, by failing to show explicit
disclosure of the parsing limitation and arguing instead that it “must” be
disclosed, essentially argues that the parsing limitation is disclosed
inherently in Bastiani. Prelim. Resp. 7. “A reference may anticipate
inherently if a claim limitation that is not expressly disclosed ‘is necessarily
present, or inherent, in the single anticipating reference.’” In re
Montgomery, 677 F.3d 1375, 1379-80 (Fed. Cir. 2012) (quoting Verizon
Servs. Corp. v. Cox Fibernet Va., Inc., 602 F.3d 1325, 1337 (Fed. Cir.
2010)). “‘Inherency . . . may not be established by probabilities or
possibilities. The mere fact that a certain thing may result from a given set
of circumstances is not sufficient.’” Bettcher Indus., Inc. v. Bunzl USA, Inc.,
661 F.3d 629, 639-40 (Fed. Cir. 2011) (quoting In re Oelrich, 666 F.2d 578,
581 (CCPA 1981)).

2 Bastiani uses the term “device” to refer to both the “IDE device” of
Figure 3 and an “ASP device” of Figures 2 and 4A-4C, which includes the
functionality of the IDE device along with an ASP Adapter, either integrated
with the IDE device or connected to the IDE device. Ex. 1003, col. 6, ll. 17-
61; col. 6, ll. 53-60.
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According to Patent Owner, Petitioner’s inherency argument is based
on an unproved allegation that Bastiani’s ASP Adapter and the ’788 patent’s
bridging circuit both comport to the same standard. Prelim. Resp. 8.
According to Patent Owner, Petitioner’s use of the ’788 patent’s disclosure
to prove the contents of Bastiani’s disclosure is an improper circular
argument. Id. Patent Owner further argues that, even if the ASP Adapter in
Bastiani and the bridging circuit in the ’788 patent do comport to the same
standard, the IDE/ATA standard does not relate to the claimed parsing
limitation. Id. at 9-10. Patent Owner contends that neither the ’788 patent
nor the IDE/ATA standards define Bastiani’s ASP packets or specify how to
parse them. Id. at 9.
We agree with Patent Owner that Petitioner has not shown sufficiently
that Bastiani inherently discloses the parsing limitation of claim 1.
Petitioner’s declarant essentially opines that because Bastiani’s ASP Adapter
comports to the same standard as the ’788 patent’s bridging circuit, receives
similar input, and outputs the same commands, it must be implemented in
same way. Ex. 1007 ¶ 24. Mr. Gardner, however, does not introduce
persuasive evidence that the parsing feature of the bridging circuit is a
requirement of the ATA standards. Although the ’788 patent states that its
bridging circuit parses a command block into a sequence of ATA operations,
it does not identify this feature as a requirement of any version of the ATA
standards. Ex. 1001, col. 4, ll. 15-17; col. 6, ll. 11-14.
Moreover, as Patent Owner argues (Prelim. Resp. 9), Bastiani’s ASP
Adapter receives different input than the ’788 patent’s bridging circuit.
Specifically, Bastiani’s ASP Adapter receives a packet conforming to an
ASP protocol (Ex. 1003, col. 3, ll. 21-34), while the ’788 patent’s bridging
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circuit receives a Mass Storage Class (“MSC”) packet (Ex. 1001, col. 6,
ll. 45-50; col. 10, ll. 14-20). Petitioner does not point to persuasive evidence
that any ATA standard requires both types of packets to be processed using
the same parsing technique. Specifically, Petitioner has not demonstrated
that any such standard requires Bastiani’s ASP Adapter to break down an
OUTDATA0/1 packet into a sequence of ATA operations.
We also agree with Patent Owner (Prelim. Resp. 8) that Petitioner has
not shown that Bastiani’s ASP Adapter and the ’788 patent’s bridging circuit
comport to the same standard. According to the ’788 patent, the ATA
standards broadly include ATA/ATAPI-4, its predecessors, and future ATA
standards. Ex. 1001, col. 1, ll. 11-16. Mr. Gardner does not state to which
version of the ATA standards the ’788 patent’s bridging circuit comports.
He does state, however, that ATA-4 was the most recent version available at
the time the ’788 patent was filed, suggesting that the preferred bridging
circuit described in the ’788 patent would comport to ATA-4. Ex. 1007
¶ 11. Petitioner also does not specify to which version of the ATA standards
Bastiani’s ASP Adapter comports. The portion of Bastiani to which
Petitioner cites suggests it is an earlier version, ATA-3, rather than ATA-4.
Ex. 1003, col. 42, ll. 13-16 (“The user should consult the current version of
the X3T10 document on AT Attachement-3 Interface for a complete listing
of the commands and responses that the device uses.”). Mr. Gardner does
not provide a comparison of ATA-4 with ATA-3. Nor does Mr. Gardner
state that the ’788 patent’s preferred bridging circuit would have comported
to ATA-3, or that Bastiani’s ASP Adapter would have comported to ATA-4.
Because Petitioner has not shown that the bridging circuit and the ASP
Adapter comport to the same standard, we are not convinced by Petitioner’s
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argument that the ’788 patent is persuasive evidence of the implementation
details of Bastiani’s ASP Adaptor, including any necessity for parsing.
Regarding the contents of the ATA standards, Mr. Gardner further
opines that the ATA-4 version of the ATA standards has clauses covering
cabling, connector, and signaling requirements of an ATA cable that plugs
into an ATA interface. Ex. 1007 ¶ 19. This opinion, however, is entitled to
little weight as he does not identify any evidence to show the requirements
of the ATA-4 standard.3 See 37 C.F.R. § 42.65(a) (“Expert testimony that
does not disclose the underlying facts or data on which the opinion is based
is entitled to little or no weight.”).
On the current record, we cannot say that the parsing feature of
claim 1 necessarily is present in Bastiani’s ASP Adapter. Thus, we are not
persuaded that Bastiani inherently discloses the parsing limitation of claim 1.
Accordingly, Petitioner has not demonstrated a reasonable likelihood that it
would prevail with respect to claim 1.

3. Claims 9, 10, 17-20, 22, and 24
The remaining independent claims, 10, 18, and 24, each include
substantially the same parsing limitation. Petitioner advances substantially
the same arguments and evidence regarding these limitations. Pet. 22-23,
28-29, 33-34. Patent Owner also argues claims 10, 18, and 24 together with
claim 1. Prelim. Resp. 3. For the reasons given above, Petitioner has not

3 Mr. Gardner cites to page vii of Clay, Ex. 1006, as setting forth certain
clauses of the ATA-4 standard. This appears to by a typographical error,
however, as Clay does not have a page vii and does not discuss specific
clauses of the ATA-4 standard.
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persuaded us that Bastiani explicitly or inherently discloses the parsing
limitations of claims 10, 18, and 24, and, thus, has not demonstrated a
reasonable likelihood that it would prevail with respect to claims 10, 18, and
24 as anticipated by Bastiani.
Claim 9 depends from claim 1; claim 17 depends from claim 10; and
claims 19, 20, and 22 depend from claim 18. In arguing claims 9, 17, 19, 20,
and 22, Petitioner does not advance additional evidence regarding the
parsing limitations of claims 1, 10, and 18. Accordingly, Petitioner has not
demonstrated a reasonable likelihood that it would prevail with respect to
claims 9, 17, 19, 20, and 22 as anticipated by Bastiani.

D. Obviousness over Bastiani, McDonald, and Clay
1. Obviousness of claims 1, 9, 10, 17-20, 22, and 24 over
Bastiani
Petitioner contends that, even if claims 1, 9, 10, 17-20, 22, and 24 are
not anticipated by Bastiani, they nevertheless would have been obvious over
Bastiani. Pet. 36. Specifically, Petitioner argues that “[a]ny elements found
to be missing were well known in the prior art, as Bastiani clearly discloses
all points that the inventors of the ’788 patent considered to be novel. The
claims are rendered obvious by modifying Bastiani to include whatever
elements are found to be missing.” Pet. 36. Petitioner relies on
Mr. Gardner’s declaration, which states
[b]ased on the reasons stated in the petition, as well as my
experience and knowledge, it is my opinion that claims 1, 9-10,
17-20, 22, and 24 of the ’788 patent are rendered obvious by
modifications to Bastiani if not anticipated by Bastiani. The
modifications would involve techniques already known in the
prior art.
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Ex. 1007 ¶ 32. For the reasons given above, we are not persuaded that
Bastiani discloses the parsing limitations of claims 1, 9, 10, 17-20, 22, and
24. Thus, the issue is whether Petitioner has demonstrated that it is
reasonably likely to show that these claims would have been obvious over
Bastiani.
We are not persuaded that claims 1, 9, 10, 17-20, 22, and 24 would
have been obvious over Bastiani.
An analysis of obviousness must be based on several factual
inquiries: (1) the scope and content of the prior art; (2) the
differences between the prior art and the claims at issue; (3) the
level of ordinary skill in the art at the time the invention was
made; and (4) objective evidence of nonobviousness, if any.
In re Kubin, 561 F.3d 1351, 1355 (Fed. Cir. 2009). Here, Petitioner’s
obviousness argument is entirely conclusory. Petitioner does not identify the
claimed parsing as a difference between the claims and Bastiani, nor does
Petitioner explain how Bastiani would have been modified or the reasons a
person of ordinary skill in the art would have done so. Mr. Gardner’s
declaration is equally conclusory. Accordingly, Petitioner has not
demonstrated a reasonable likelihood that it would prevail with respect to
claims 1, 9, 10, 17-20, 22, and 24 as obvious over Bastiani.

2. Remaining Obviousness Contentions
Regarding claims 2-8, 11-16, 21, 23, and 25-27, Petitioner presents
arguments and evidence to show that the additional limitations of these
claims would have been obvious modifications to Bastiani. Pet. 36-51.
Petitioner, however, does not present, in its analysis of these claims, any
additional evidence or argument regarding the parsing limitation of claims 1,
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10, 18, and 24, from which claims 2-8, 11-16, 21, 23, and 25-27 depend.
Accordingly, Petitioner has not demonstrated a reasonable likelihood that it
would prevail with respect to claims 2-8, 11-16, 21, 23, and 25-27 as
obvious over Bastiani.
Petitioner makes additional arguments that claims 7, 16, and 21 would
have been obvious over Bastiani and McDonald (Pet. 51-55) and that claim
23 would have been obvious over Bastiani and Clay (Pet. 55-57). Once
again, Petitioner does not present any additional evidence or argument
regarding the parsing limitation of claims 1, 10, and 18, from which claims
7, 16, 21, and 23 depend. Accordingly, Petitioner has not demonstrated a
reasonable likelihood that it would prevail with respect to claims 7, 16, and
21 as obvious over Bastiani and McDonald or claim 23 as obvious over
Bastiani and Clay.

III. CONCLUSION
Petitioner has not demonstrated persuasively that Bastiani, alone or in
combination, discloses or teaches “parsing the command block into a
sequence of ATA [register] operations necessary to execute the given ATA
register-delivered transaction,” as recited in independent claims 1, 10, and
24, or “an ATA command protocol adapter to parse a command packet into
a sequence of ATA register operations and cause that sequence of operations
to be performed by the ATA register protocol adapter,” as recited in
independent claim 24. Thus, Petitioner has not shown that there is a
reasonable likelihood that it would prevail with respect to at least one of the
claims challenged in the Petition. The Petition is denied.
Case IPR2014-00201
Patent 6,618,788

19

IV. ORDER
For the reasons given, it is
ORDERED that the Petition challenging the patentability of claims 1-
27 is denied.
FURTHER ORDERED that no inter partes review is instituted.

PETITIONER:

Brent Yamashita
Brent.yamashita@dlapiper.com

Gerald Sekimura
Gerald.sekimura@dlapiper.com

PATENT OWNER:

Robert Sterne
Rsterne-ptab@skgf.com

Jon Wright
Jwright-ptab@skgf.com

Christian Camarce
Ccamarce-ptab@skgf.com