Thomas B. Richardson et al.

Patent Trials and Appeals Board

Jul 24, 2019

13981974 - (D) (P.T.A.B. Jul. 24, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/981,974 01/08/2014 Thomas B. Richardson 31183-2403A 3264
159237 7590 07/24/2019
MacDermid Performance Solutions - Patents
c/o Carmody Torrance Sandak & Hennessey LLP
195 Church Street
P.O. Box 1950
New Haven, CT 06509-1950
EXAMINER
SLUTSKER, JULIA
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
07/24/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
mpspatents@carmodylaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte THOMAS B. RICHARDSON, JOSEPH A. ABYS,
WENBO SHAO, CHEN WANG, VINCENT PANECCASIO JR.,
CAI WANG, XUAN LIN, and THEODORE ANTONELLIS1
________________

Appeal 2017-009107
Application 13/981,974
Technology Center 2800
________________

Before BRADLEY W. BAUMEISTER, SHARON FENICK, and
RUSSELL E. CASS, Administrative Patent Judges.

CASS, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 2, 4–11, 14–17, 19–22, 25, 28, and 30–34. Appeal Br.
7.2 We have jurisdiction under 35 U.S.C. § 6(b). An oral hearing was
conducted on June 24, 2019. A transcript of the oral hearing will be made of
record shortly.

1 Appellants list Enthone Inc. as the real party in interest. Appeal Brief filed
March 27, 2017 (“Appeal Br.”) 3.
2 Rather than repeat the Examiner’s positions and Appellants’ arguments in
their entirety, we refer to the above mentioned Appeal Brief, as well as the
following documents for their respective details: the Final Action mailed
November 17, 2016 (“Final Act.”); the Examiner’s Answer mailed May 18,
2017 (“Ans.”); and the Reply Brief (“Reply Br.”) mailed June 12, 2017.
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We reverse.
THE INVENTION
The present invention relates to a process for creating conductive
paths in the manufacture of microelectronic devices, and more specifically
for filling vias that are relatively deep and/or have a relatively small entry
dimension. Spec. ¶ 1. The Specification explains that “[p]lating chemistry
sufficient to copper[-]metallize small size via and trench features has been
developed and finds use in the copper damascene method.” Id. ¶ 4. The
Specification further explains that “[i]n another form, a wafer may be
constructed to comprise one or more very deep via,” known as a “through
silicon via” (TSV), which can “allow electrical interconnection between 2 or
more wafers bonded to each other in a three-dimensional wafer stack.” Id.
¶ 5. The depth of a TSV, the Specification explains, “can vary from on the
order of about 20 microns to about 500 microns.” Id. ¶ 7. The Specification
explains that “[i]n filling deep via[s], and especially deep vias with relatively
small entry dimensions, it has been found difficult to maintain satisfactory
deposition rates throughout the filling process.” Id. ¶ 9.
In the process according to the invention, an “electrodeposition circuit
is established comprising an anode, the electrolytic composition, the
aforesaid cathode, and a power source.” Id. ¶ 12.
A potential is applied between the anode and the cathode during
a via filling cycle to generate a cathodic electrodeposition
current causing reduction of copper ions at the cathode, thereby
plating copper onto the metallizing substrate at the bottom and
sidewall of the via, the via preferentially plating on the bottom
and lower sidewall to cause filling of the via from the bottom
with copper.
Id.
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“During the filling cycle, the polarity of [the] circuit is reversed for an
interval to generate an anodic potential at the metalizing substrate and
desorb [the] leveler from the copper surface within the via.” Id. “Copper
deposition is resumed by re-establishing the surface of the copper within the
via as the cathode in the circuit, thereby yielding a copper filled via feature.”
Id.

THE EXAMINER’S REJECTION
Claims 2, 4–11, 14–17, 19–22, 25, 28, and 30–34 stand rejected as
unpatentable over Mayer (US 6,946,065 B1; issued Sept. 20, 2005) in view
of Ahrens (US 2005/0153546 A1; published July 14, 2005).

ANALYSIS
Appellants separately argue independent claims 25, 28, and 33. Each
of these claims will be discussed in turn below.
I. Claim 25
Claim 25 is reproduced below, with the key element at issue in italics:
25. A process for metalizing a through silicon via feature in a
semiconductor integrated circuit device, said device comprising
a surface having a via feature therein, said via feature
comprising a sidewall extending from said surface and a
bottom, said sidewall, said bottom and said surface having a
metalizing substrate thereon for deposition of copper, said
metalizing substrate comprising a seed layer, the process
comprising:
immersing said metalizing substrate in an electrolytic
copper deposition composition, wherein the through silicon via
feature has an entry dimension between 1 micrometers and 25
micrometers, a depth dimension between 50 micrometers and
300 micrometers, and an aspect ratio greater than 2:1, said
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metalizing substrate providing a cathode for electrolytic
deposition of copper thereon, the electrolytic deposition
composition comprising:
a source of copper ions;
an acid component selected from among an
inorganic acid, an organic sulfonic acid, and mixtures
thereof;
an accelerator;
a suppressor;
a leveler; and
chloride ions;
establishing an electrodeposition circuit comprising an
anode, the electrolytic deposition composition, the cathode, and
a power source;
applying a potential between the anode and the cathode
during a via filling cycle to establish an anodic polarity at the
anode and a cathodic polarity at the cathode to generate an
electrodeposition current and cause reduction of copper ions at
the cathode to plate copper onto the metalizing substrate at the
bottom and sidewall of the via, the via preferentially plating on
the bottom and lower sidewall to cause filling of the via from
the bottom with copper;
reversing a polarity of said electrodeposition circuit
during the via filling cycle for at least one interval to generate
an anodic potential at said metalizing substrate;
resuming copper deposition by re-establishing the surface
of the copper within the via as the cathode in the circuit,
thereby yielding a copper filled via feature;
wherein a ratio of cumulative charge transfer in said
circuit during copper deposition within said filling cycle to
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cumulative charge transfer during a sum of all anodic potential
intervals is at least 80:1.
Appeal Br. 23–24 (Claims Appendix) (emphases added).
The Examiner finds that Mayer teaches the limitations of claim 25
except for two limitations: (1) wherein the through silicon via feature has
an entry dimension between 1 micrometers and 25 micrometers and a depth
dimension between 50 micrometers and 300 micrometers; and (2) wherein a
ratio of cumulative charge transfer in said circuit during copper deposition
within said filling cycle to cumulative charge transfer during the sum of all
anodic potential intervals is at least 80:1. Final Act. 5. As to element (1),
the Examiner combines Mayer with Ahrens, which discloses a “through
silicon via feature [having] an entry dimension between 1 micrometers and
25 micrometers, [and] a depth dimension between 50 micrometers and 300
micrometers for the purpose of fabrication [of] contact structures.” Id.
(citing Ahrens ¶ 36).
As to element (2), the Examiner finds that “Mayer discloses that a
ratio of cumulative charge transfer in said circuit during copper deposition
within said filling cycle to cumulative charge transfer during the sum of all
anodic potential intervals should be greater than 1 to result in net plating.”
Id. at 6 (citing Mayer col. 20, ll. 60–67; Fig. 11). The Examiner further
determines that the “ratio of cumulative charge transfer in said circuit during
copper deposition within said filling cycle to cumulative charge transfer
during the sum of all anodic potential intervals therefore are art-recognized
result-affecting variables/parameters,” and “therefore it would have been
obvious to optimize (for example by routine experimentation) a ratio of
cumulative charge transfer in said circuit during copper deposition within
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said filling cycle to cumulative charge transfer during the sum of all anodic
potential intervals for the purpose of achieving net plating.” Id. (citing
Mayer col. 20, ll. 60–67). The Examiner further states that this ratio is result
affecting because it affects the degree of “net plating” achieved and avoids
“seam and void formation.” Ans. 3 (citing Mayer col. 20, ll. 20–25, 60–67).
Appellants acknowledge that “Mayer describes that ‘relation to
charges carried in the forward and reverse pulses needs to be greater than 1
to result in net plating (not de-plating).’” Appeal Br. 10 (citing Mayer
col. 20, ll. 64–67). Appellants argue, however, that there is no teaching or
suggestion in the art “that would have led one skilled in the art to have
adjusted or optimized this parameter to a ratio of at least 80:1 as described
and claimed by Appellant[s].” Id. at 11. Appellants further argue that “one
skilled in the art cannot ascertain from the teachings of Mayer that such
values would be within the skill of one skilled in the art.” Id. Appellants
assert that the “greater than 1” ratio in Mayer “is very different from” the
80:1 ratio in claim 25, and that that “the value of Mayer would have to be
significantly modified or changed to achieve the desired result.” Id.
We find that the Examiner has not made out a sufficient case of
obviousness. The Examiner acknowledges that Mayer does not reasonably
teach or suggest the claimed ratio of at least 80:1. Final Act. 5. The
Examiner determines that one of skill would have achieved this ratio through
optimization (id.), but we do not find a sufficient basis to conclude that
optimization of the process taught in Mayer would have led to the invention
of claim 25, particularly given the differences between Mayer’s process and
the process of the claimed invention.
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More specifically, Mayer describes a damascene plating process used
to create vias in interlayer dielectric trenches of “approximately 1 µm
depth.” Mayer col. 2, ll. 63–67, col. 7, l. 13; Fig. 20. Claim 25, on the other
hand, discloses a process for metallizing “through silicon vias” having “a
depth dimension between 50 micrometers and 300 micrometers,” which is at
least 50 times as large as the vias described in Mayer. Claim 25. The
Examiner has not sufficiently shown that one of ordinary skill would have
been motivated to use the interlayer-dielectric metallization process of
Mayer for through silicon vias of the dimensions set forth in claim 25, much
less that the routine optimization of such a process would have led to the
claimed 80:1 ratio of cumulative charge transfer of copper deposition to
anodic potential intervals.
Additionally, the Examiner has not established that one of ordinary
skill would have looked to Ahrens’s process, which is performed on a
relatively thick silicon wafer, to optimize the process so as to achieve the
claimed ratio specifically in Mayer’s relatively thin dielectric layer. The
Examiner relies on Ahrens for teaching through silicon vias of the claimed
dimensions. See Final Act. 5 (citing Ahrens ¶ 36). However, the Examiner
does not point to sufficient disclosure in Ahrens that teaches or suggests a
plating process for such through silicon vias using anodic potential intervals
as set forth in the claim, much less the “at least 80:1 ratio” of cumulative
charge transfer of copper deposition to such anodic potential intervals set
forth in claim 25. Consequently, we are persuaded that the Examiner has
failed to establish that it would have been obvious to one of ordinary skill to
have optimized Mayer in the manner claimed.
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Accordingly, we reverse the Examiner’s rejection of claim 25. We
also reverse the Examiner’s rejection of dependent claims 2, 4–11, 14–17,
and 19–22, which are dependent on claim 25.
II. Claim 28
Claim 28 is reproduced below, with the key elements at issue in
italics:
28. A process for metalizing a through silicon via feature in a
semiconductor integrated circuit device, said device comprising
a surface having a via feature therein, said via feature
comprising a sidewall extending from said surface and a
bottom, said sidewall, said bottom and said surface having a
metalizing substrate thereon for deposition of copper, said
metalizing substrate comprising a seed layer, the process
comprising:
immersing said metalizing substrate in an electrolytic
copper deposition composition, wherein the through silicon via
feature has an entry dimension between 1 micrometers and 25
micrometers, a depth dimension between 50 micrometers and
300 micrometers, and an aspect ratio greater than 2:1, said
metalizing substrate providing a cathode for electrolytic
deposition of copper thereon, the deposition composition
comprising:
a source of copper ions;
an acid component selected from among an
inorganic acid, an organic sulfonic acid, and mixtures
thereof;
an accelerator;
a suppressor;
a leveler; and
chloride ions;
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establishing an electrodeposition circuit comprising an
anode, the electrolytic deposition composition, the cathode, and
a power source;
applying a potential between the anode and the cathode
during a via filling cycle to establish a positive polarity at the
anode and a negative polarity at the cathode to generate an
electrodeposition current and cause reduction of copper ions at
the cathode to plate copper onto the metalizing substrate at the
bottom and sidewall of the via, the via preferentially plating on
the bottom and lower sidewall to cause filling of the via from
the bottom with copper;
reversing a polarity of said electrodeposition circuit
during the via filling cycle for at least one interval to generate
an anodic potential at said metalizing substrate;
resuming copper deposition by re-establishing the surface
of the copper within the via as the cathode in the circuit,
thereby yielding a copper filled via feature;
wherein the via filling cycle comprises a plurality of
faradaically material anodic potential intervals in each of
which an average anodic charge transfer is at least 3 x 10·4
coulombs/cm2 integrated over a total electrodic surface area of
said metalizing substrate, and
wherein between successive faradaically material anodic
potential intervals, an integrated average cathodic current
charge transfer over the total electrodic surface area of said
metalizing substrate is at least 1.5 x 10·2 coulombs/cm2.
Appeal Br. 24–25 (Claims Appendix).
The Examiner relies on Mayer for most of the features of claim 28,
but finds that Mayer does not disclose: (1) wherein the through silicon via
feature has an entry dimension between 1 micrometers and 25 micrometers
and a depth dimension between 50 micrometers and 300 micrometers; and
(2) “wherein between successive faradaically material anodic potential
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intervals, an integrated average cathodic current charge transfer over the
total electrodic surface area of said metalizing substrate is at least 1.5 x 10·2
coulombs/cm2”; and (3) “wherein the via filling cycle comprises a plurality
of faradaically material anodic potential intervals in each of which an
average anodic charge transfer is at least 3 x 10·4 coulombs/cm2 integrated
over a total electrodic surface area of said metalizing substrate.” Final
Act. 7–8; Ans. 5–6. The Examiner finds that “Mayer discloses using an
anodic potential for copper deposition (column 20, lines 46-50) and that
some average charge transfer occurs during anodic potential interval
(column 16, lines 10-20; column 20, lines 60-65; Fig. 11).” Ans. 5. The
Examiner further states that “Mayer discloses that parameters of anodic and
cathodic potentials as well as charge current density during these intervals
can be optimized (column 16, lines 10-20) to achieve net plating (column
20, lines 60-67) without seam and void formation (column 20, lines 20-25).”
Id. at 5–6. Consequently, the Examiner determines, these “are result-
effective parameters” that would have been obvious to optimize. Id. at 6.
Appellants respond that Mayer does not teach or suggest “any
particular values of average anodic charge transfer or integrated average
cathodic current charge transfer and thus it cannot be shown that the
teachings of Mayer would have led one skilled in the art to have optimized”
these values. Appeal Br. 12. Appellants also argue that the portion of
Mayer cited by the Examiner does not disclose that the anodic and cathodic
charge transfer values can be optimized, but rather “relates to the Initiation
Phase of Mayer’s process, a phase that the Examiner has not used in the
rejection of the remaining elements of the claims.” Reply Br. 4 (citing
Mayer col. 16, ll. 10–20). “Moreover,” Appellants argue, “the cited passage
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only indicates a proposed range of current density for a superimposed
cathodic-anodic waveform,” and “does not discuss optimization in general
nor does it describe how variation of this variable [a]ffects properties or
results of the method.” Id. Finally, Appellants argue that:
Even taking the highest possible cathodic current density
(255 mA/cm2) disclosed by Mayer in this passage and the
highest possible time period (10ms), the result is still not the
claimed invention. Using the conversion that lamp-second = 1
coulomb, the result of the conversion is 0.00255 coulombs/cm2,
i.e., 0.255x10-2 coulombs/cm2, much less than the claimed
range. Therefore, Mayer does not teach or render obvious the
claimed invention.
Id.
We agree with Appellants that the Examiner has not sufficiently
demonstrated obviousness of claim 28. The Examiner acknowledges that
none of the prior art discloses the claimed ranges of average anodic charge
transfer or integrated average cathodic current charge transfer set forth in
claim 28. As Appellants point out, the range of Mayer relied on by the
Examiner teaches a maximum charge transfer of 0.00255 coulombs/cm2,
well below the claimed ranges. Reply Br. 4 (citing Mayer col. 16, ll. 10–
20). We also agree with Appellants that Mayer does not sufficiently disclose
that average anodic charge transfer or integrated average cathodic current
charge transfer are “result-oriented variables” that can be optimized to
improve plating of for some other purposes.
Moreover, as discussed above with respect to claim 25, Mayer differs
from the process of claim 28 because Mayer describes a damascene plating
process used to create vias in trenches of “approximately 1 µm depth,” while
claim 28 recites a process for metallizing “through silicon vias” having “a
depth dimension between 50 micrometers and 300 micrometers,” which is at
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least 50 times as large as the vias described in Mayer. Mayer col. 2, ll. 63–
67; col. 7, ll. 13; Fig. 20. The Examiner has not sufficiently shown that one
of ordinary skill would have been motivated to use the metallization process
of Mayer for through silicon vias of the dimensions set forth in claim 28,
much less that the routine optimization of Mayer’s process would have led
to the ranges of average anodic charge transfer or integrated average
cathodic current charge transfer set forth in claim 28.
Additionally, the Examiner has not established that one of ordinary
skill would have looked to Ahrens to demonstrate that optimization of
Mayer’s damascene process would have achieved the values set forth in
claim 28. The Examiner does not point to sufficient disclosure in Ahrens
that teaches or suggests a plating process for such through silicon vias using
anodic potential intervals as set forth in the claim, much less the ranges of
average anodic charge transfer or integrated average cathodic current charge
transfer set forth in claim 28. Consequently, we are persuaded that the
Examiner has failed to establish that it would have been obvious to one of
ordinary skill to have optimized Mayer in the manner claimed.
III. Claim 33
Claim 33 is reproduced below, with the key elements at issue in
italics:
33. A process for metalizing a through silicon via feature in a
semiconductor integrated circuit device, said device comprising
a surface having a via feature therein, said via feature
comprising a sidewall extending from said surface, and a
bottom, said sidewall, said bottom and said surface having a
metalizing substrate thereon for deposition of copper, said
metalizing substrate comprising a seed layer, the process
comprising:
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immersing said metalizing substrate with an electrolytic
copper deposition composition, wherein the through silicon via
feature has an entry dimension between 1 micrometers and 25
micrometers, a depth dimension between 50 micrometers and
300 micrometers, and an aspect ratio greater than 2:1, said
metalizing substrate providing a cathode for electrolytic
deposition of copper thereon, the deposition composition
comprising:
a source of copper ions;
an acid component selected from among an
inorganic acid, an organic sulfonic acid, and mixtures
thereof;
an accelerator;
a suppressor;
a leveler; and
chloride ions;
establishing an electrodeposition circuit comprising an
anode, the electrolytic deposition composition the cathode, and
a power source;
applying a potential between the anode and the cathode
during a via filling cycle to establish a positive polarity at the
anode and a negative polarity at the cathode to generate an
electrodeposition current and cause reduction of copper ions at
the cathode to plate copper onto the metalizing substrate at the
bottom and sidewall of the via, the via preferentially plating on
the bottom and lower sidewall to cause filling of the via from
the bottom with copper;
reversing a polarity of said electrodeposition circuit
during the via filling cycle for at least one interval to generate
an anodic potential at said metalizing substrate;
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resuming copper deposition by re-establishing the surface
of the copper within the via as the cathode in the circuit,
thereby yielding a copper filled via feature;
the method further comprising the steps of:
reversing the polarity of the circuit to provide an anodic
potential at said metalizing substrate in a plurality of intervals
during the filling cycle;
wherein a ratio of cumulative charge transfer in said
circuit during copper deposition within said filling cycle to
cumulative charge transfer during the sum of all intervals of
anodic potential at said metalizing substrate is at least 50:1;
wherein said filling cycle comprises a plurality of anodic
potential intervals of material duration, and each of said anodic
intervals of material duration extends for a period of at least
0.6 seconds, a period of cathodic current at said metalizing
substrate between successive anodic potential intervals of
material duration being at least 0.5 minutes;
wherein a cumulative duration of all anodic potential
intervals at said metalizing substrate during said filling cycle is
not more than 50 seconds;
wherein a cumulative extent of anodic charge transfer at
said metalizing substrate in the sum of all said anodic potential
intervals is not greater than an average of 1.8 coulombs/cm2
integrated over the total electrodic surface area of said
metalizing substrate;
wherein during each said anodic potential interval of
material duration, a current density across an electrode surface
of the metalizing substrate is maintained at an average of
between 0.1 and 100 mA/cm2 integrated over a total electrodic
surface area of said metalizing substrate;
wherein each of said anodic potential intervals is
effective to desorb leveler from the electrodic surface, whereby
the average current density integrated over the total electrodic
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surface area of said metalizing substrate is increased upon
resumption of cathodic current relative to a current density prior
to said anodic potential interval;
wherein said anodic potential intervals are effective to
desorb suppressor from the surface of the copper within the via;
wherein a ratio of cumulative duration of cathodic
current during copper deposition within said filling cycle to
cumulative duration of all anodic potential intervals at said
metalizing substrate is at least 80:1; and
wherein the copper filled via is at least one of
substantially free of seams and voids or substantially free of
mounds and protrusions.
Appeal Br. 26–28 (Claims Appendix).
The Examiner finds that Mayer does not disclose multiple limitations
of claim 33, including:
(1) wherein the through silicon via feature has an entry
dimension between 1 micrometers and 25 micrometers, a depth
dimension between 50 micrometers and 300 micrometers;
(2) wherein a ratio of cumulative charge transfer in said circuit
during copper deposition within said filling cycle to cumulative
charge transfer during the sum of all anodic potential intervals
is at least 50:1; (3) said anodic intervals of material duration
extending for a period of at least 0.6 seconds, a period of
cathodic current at said metalizing substrate between successive
anodic potential intervals of material duration being at least
0.5 minutes; (4) wherein a cumulative duration of all anodic
potential intervals at said metalizing substrate during said
filling cycle is not more than 50 seconds; (5) during each said
anodic potential interval of material duration, a current density
across an electrode surface of the metalizing substrate is
maintained at an average of between 0.1 and 100 mA/cm2
integrated over a total electrodic surface area of said metalizing
substrate.
Final Act. 19.
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As with the previous independent claims, the Examiner determines
that it would have been obvious “to modify Mayer with Ahrens to have
through silicon via feature has an entry dimension between 1 micrometers
and 25 micrometers, a depth dimension between 50 micrometers and
300 micrometers for the purpose of fabrication contact structures.” Id.
(citing Ahrens ¶ 36). As to the other limitations, the Examiner finds as
follows:
Regarding elements (2)-(5), Mayer discloses that a ratio of
cumulative charge transfer in said circuit during copper
deposition within said filling cycle to cumulative charge
transfer during the sum of all anodic potential intervals should
be greater than 1 to result in net plating (column 20, lines 60–
67; Fig.11 ). Mayer also discloses that anodic and cathodic
charge transfer as wells as other parameters of deposition such
as duration of anodic and cathode potential intervals, a period
of cathodic and anodic current, a cumulative extend of anodic
charge transfer, current densities affect filling of a via
(column 20, lines 46-67). Parameters of electrodeposition
therefore are art-recognized result-affecting
variables/parameters.
Final Act. 20. Accordingly, the Examiner finds that “it would have been
obvious to optimize (for example by routine experimentation) the parameters
of electrodeposition for the purpose of achieving net plating.” Id. (citing
Mayer col. 20, ll. 60–67).
Appellants argue that “there is no teaching or suggestion in Mayer
that all of elements (2)-(8) are result effective variables that can be
optimized.” Appeal Br. 15 (emphasis omitted). Appellants also argue that
the 50:1 cumulative charge ratio in claim 33 is similar to the ratio in claim
25 and, thus, “is not obvious” “[f]or the same reasons as claim 25.” Reply
Br. 4. As to the claim 33’s limitation that “requires each anodic interval to
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last at least 0.6 seconds and a cathodic interval of 0.5 minutes (30 seconds),”
Appellants argue, “the largest time-period for even the cathodic interval
discussed by Mayer is 200ms. (20:34).” Id. Moreover, Appellants assert,
because “Mayer refers to the anodic period as a ‘pulse’ compared to the
cathodic period, a person of ordinary skill in the art would understand that
the anodic period would be even shorter.” Id. “In any event,” Appellants
state, “the longest period described by Mayer is still much less than
0.6 seconds and 30 seconds.” Id.
We agree with Appellants that the Examiner has not sufficiently
demonstrated obviousness of claim 33. The Examiner acknowledges that
none of the prior art discloses elements (2)–(8) of the claim referred to
above. We also agree with Appellants that Mayer does not disclose that
these are “result-oriented variables” that can be optimized to improve plating
or for some other purposes. This is particularly true because, as discussed
above with respect to claim 25, Mayer differs from the claimed process
because Mayer describes a damascene plating process used to create vias in
dielectric trenches of “approximately 1 µm depth,” whereas claim 33 recites
a process for metallizing “through silicon vias” having “a depth dimension
between 50 micrometers and 300 micrometers,” which depth is at least 50
times as large as the vias described in Mayer and in a different material.
Mayer col. 2, ll. 63–67; col. 7, ll. 13; Fig. 20. As discussed above, the
Examiner has not sufficiently shown that one of ordinary skill would have
used the metallization process of Mayer for through silicon vias of the
dimensions set forth in claim 33, much less that the optimization of Mayer’s
process would have led to the ranges of average anodic charge transfer or
integrated average cathodic current charge transfer set forth in claim 33.
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The Examiner also has not established that one of ordinary skill would have
looked to Ahrens to demonstrate that optimization of Mayer’s damascene
process would have achieved the values set forth in claim 33.
Additionally, we determine that the Examiner has not established the
obviousness of the 50:1 cumulative charge ratio in claim 33, for the same
reasons discussed above with respect to the 80:1 range in claim 25.
Finally, we agree with Appellants that the longest time period Mayer
discloses for a charge transfer interval is 200 ms. Mayer col. 20, ll. 34;
Reply Br. 4. This is significantly less than claim 33’s limitation requiring
“each anodic interval to last at least 0.6 seconds and a cathodic interval of
0.5 minutes (30 seconds).” The Examiner has failed to sufficiently show
that a routine optimization of Mayer would have resulted in the values set
forth in the claim, which are much larger than the maximum length taught
by Mayer, particularly given the differences in Mayer’s damascene process
and the claimed invention’s focus on filling silicon vias, as discussed above.
And, the Examiner fails to point to sufficient disclosure in Mayer that would
support the conclusion that routine optimization of Mayer would have led
one of ordinary skill to the claimed values.
Consequently, we are persuaded that the Examiner has failed to
establish that it would have been obvious to one of ordinary skill to have
optimized Mayer in the manner claimed.
IV. Conclusion
We are persuaded that the Examiner erred in rejecting independent
claims 25, 28, and 33 as obvious based on Mayer and Ahrens. We,
therefore, reverse the Examiner’s rejection of those claims. We also reverse
Appeal 2017-009107
Application 13/981,974

19
the rejections of claims 2, 4–11, 14–17, 19–22, 30–32, and 34, which are
dependent on claims 25, 28, or 33.

DECISION
We reverse the Examiner’s rejection of claims 2, 4–11, 14–17, 19–22,
25, 28, and 30–34.

REVERSED