Steven C. Goss et al.

Patent Trials and Appeals Board

Apr 9, 2020

15097935 - (D) (P.T.A.B. Apr. 9, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/097,935 04/13/2016 Steven C. Goss TI-38213.2A 1668
23494 7590 04/09/2020
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, MS 3999
DALLAS, TX 75265
EXAMINER
TRAN, DENISE
ART UNIT PAPER NUMBER
2138
NOTIFICATION DATE DELIVERY MODE
04/09/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte STEVEN C. GOSS, GREGORY REMY PHILIPPE CONTI,
NARENDAR M. SHANKAR, MEHDI-LAURENT AKKAR, and
AYMERIC VIAL
Appeal 2018-007699
Application 15/097,935
Technology Center 2100
Before JENNIFER S. BISK, LARRY J. HUME, and
JULIET MITCHELL DIRBA, Administrative Patent Judges.
HUME, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant,1 Texas Instruments
Incorporated, appeals from the Examiner’s decision rejecting claims 9, 15–
18, 20, 25, and 26, which are all claims pending in the application.
Appellant has canceled claims 1–8, 10–14, 19, 21–24, and 27–33. Final
Act. 2. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42(a). Appellant identifies the real party in interest as Texas
Instruments Inc. Appeal Br. 1.
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STATEMENT OF THE CASE2
The claims are directed to a methods, apparatus, and systems for
secure demand paging and other paging operations for processor devices.
See Spec. (Title). In particular, Appellant’s disclosed embodiments and
claimed invention relate to “the field of electronic computing hardware and
software and communications, and is more specifically directed to improved
processes, circuits, devices, and systems for page processing and other
information and communication processing purposes, and processes of
making them. Without limitation, the background is further described in
connection with demand paging for communications processing.” Spec. ¶ 5.
Exemplary Claim
Claim 9, reproduced below, is representative of the subject matter on
appeal (emphasis added to contested prior-art limitations):
9. A secure demand paging system comprising:
a secure internal memory;
an external non-volatile memory having encrypted and
integrity-protected code pages;
an external volatile memory for swap pages;
a processor coupled to said secure internal memory and
to said external nonvolatile memory and operable to decrypt
and verify the integrity of the code pages thereby to transfer
code pages to said secure internal memory directly from said

2 Our decision relies upon Appellant’s Appeal Brief (“Appeal Br.,” filed
Feb. 26, 2018); Reply Brief (“Reply Br.,” filed July 20, 2018); Appeal Brief
Replacement paragraphs (“Replacement Arguments,” filed July 25, 2018);
Examiner’s Answer (“Ans.,” mailed June 1, 2018); Final Office Action
(“Final Act.,” mailed Aug. 2, 2017); and the original Specification (“Spec.,”
filed Apr. 13, 2016) (ultimately claiming benefit under 35 U.S.C. § 120 of
US 11/426,597, filed June 27, 2006).
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external non-volatile memory bypassing said external volatile
memory in respect of the code pages, and to swap out and swap
in the swap pages between secure internal memory and said
external volatile memory bypassing said external non-volatile
memory in respect of the swap pages for said external volatile
memory.
Prior Art
The Examiner relies upon the following prior art as evidence in
rejecting the claims on appeal:
Ginter et al. (“Ginter”) US 2002/0112171 A1 Aug. 15, 2002
Foster et al. (“Foster”) US 2003/0200448 A1 Oct. 23, 2003
Rejection on Appeal3
Claims 9, 15–18, 20, and 25–26 stand rejected under pre-AIA 35
U.S.C. § 103(a) as being unpatentable over the combination of Foster and
Ginter. Final Act. 5.
CLAIM GROUPING
Based on Appellant’s arguments (Appeal Br. 5–27) and our discretion
under 37 C.F.R. § 41.37(c)(1)(iv), we decide the appeal of the obviousness
rejection of claims 9, 17, and 20 on the basis of representative claim 9. We
address the obviousness rejection of separately argued claims 15, 16, 18, 25,
and 26, infra.4

3 We note the Examiner withdrew the rejection of claims 9, 15–18, 20, 25,
and 26 on the ground of nonstatutory double-patenting as being unpatentable
over claims 1–6 of U.S. Patent No. 9,432,196. Ans. 12.
4 “Notwithstanding any other provision of this paragraph, the failure of
appellant to separately argue claims which appellant has grouped together
shall constitute a waiver of any argument that the Board must consider the
patentability of any grouped claim separately.” 37 C.F.R. § 41.37(c)(1)(iv).
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ISSUE
Appellant argues (Appeal Br. 7–11; Reply Br. 1–21) the Examiner’s
rejection of claim 9 under 35 U.S.C. § 103(a) as being obvious over the
combination of Foster and Ginter is in error. These contentions present us
with the following issues:
(a) Did the Examiner err in finding the cited prior art combination
teaches or suggests “[a] secure demand paging system” that includes, inter
alia, “a secure internal memory,” and “a processor coupled to said secure
internal memory and to said external nonvolatile memory and operable to
decrypt and verify the integrity of the code pages thereby to transfer code
pages to said secure internal memory,” as recited in claim 1?
(b) Did the Examiner err in rejecting claim 9 as being obvious over
the reference combination because of alleged reliance upon impermissible
hindsight?
ANALYSIS
In reaching this decision, we consider all evidence presented and all
arguments actually made by Appellant. To the extent Appellant has not
advanced separate, substantive arguments for particular claims, or other
issues, such arguments are waived. 37 C.F.R. § 41.37(c)(1)(iv).
We disagree with Appellant’s arguments with respect to claims 9,
15–18, 20, 25, and 26 and, unless otherwise noted, we incorporate by
reference herein and adopt as our own: (1) the findings and reasons set forth

In addition, when Appellant does not separately argue the patentability of
dependent claims, the claims stand or fall with the claims from which they
depend. In re King, 801 F.2d 1324, 1325 (Fed. Cir. 1986).
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by the Examiner in the action from which this appeal is taken, and (2) the
reasons and rebuttals set forth in the Examiner’s Answer in response to
Appellant’s arguments. We highlight and address specific findings and
arguments regarding claim 9 for emphasis as follows.
Independent Claim 9
Issue (a): All limitations are taught or suggested
Secure internal memory
The Examiner finds Foster teaches or suggests a secure internal
memory, i.e., “a secure circuit, access control for maintaining secure [data]
in a cache 700.” Final Act. 8 (citing Foster Fig. 7; ¶ 75).
Appellant “traverse[s the] Examiner’s determination as there is no
teaching or suggestion in Fig. 7 or paragraph [0075] that cache 700 is a
‘secure’ internal memory.” Appeal Br. 7. Appellant further argues:
[W]hile paragraph [0075] teaches “encrypted data” in external
non-volatile memory 260, the “encrypted data” is stored only in
the secure memory region of external non-volatile memory 260.
Paragraph [0075] teaches only “decrypted data” is to be
returned to “instruction or data cache 700 associated with
processor 210 1”, there is no further teaching that data cache
700 is “secure”. . . . Applicants traverse Examiner’s
determination as there is nothing in paragraph [0075] that
teaches or suggests that access control “provides secure data
from cache 700”. Assuming, arguendo, that access control
provides to cache 700 what was secure data in secure memory
region of external non-volatile memory 260, there is no further
teaching or suggestion that the decrypted data sent lo cache 700
somehow transforms cache 700 itself into a “secure” memory.
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Appeal Br. 7–8.5
During prosecution, claims must be given their broadest reasonable
interpretation when reading claim language in light of the specification as it
would be interpreted by one of ordinary skill in the art. In re Am. Acad. of
Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Under this standard,
we interpret claim terms using “the broadest reasonable meaning of the
words in their ordinary usage as they would be understood by one of
ordinary skill in the art, taking into account whatever enlightenment by way
of definitions or otherwise that may be afforded by the written description
contained in the applicant’s specification.” In re Morris, 127 F.3d 1048,
1054 (Fed. Cir. 1997).
We first note Appellant does not provide an explicit definition of what
a “secure internal memory” is, either by argument or evidence. Instead,
Appellant merely points to RAM 1034 in Figure 1 of the Drawings, and
paragraph 23, line 2 of the Specification as providing written description
support for the recited “secure internal memory.” See Appeal Br. 2
(Summary of the Claimed Subject Matter); Spec. ¶ 23 (“Generally, yet
another further additional form of the invention involves a secure demand
paging system including a secure internal memory.”).

5 Appellant further states, “[f]irst, the fact that cache 700 can receive what
was secured data while saved within secure memory region of non-volatile
memory 260 does transform cache 700 into a ‘secure memory.’ Appeal
Br. 9 (emphasis added). Appellant subsequently corrected the emphasized
portion of their statement by adding “not”, i.e., “does not transform cache
700 into a ‘secure memory.’” Reply Br. 2. Even with consideration of this
correction, we are not persuaded by Appellant’s argument, as discussed
further, infra.
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Appellant further cites to Foster, and asserts:
Paragraph [0045] teaches that the combination of the
bus control unit, access control unit and external controllers
form the secure memory subsystem 220. Multiple functional
masters 210 1 . . . 210 n are NOT part of the secure memory
subsystem 220. Data cache 700 is within functional master
210 1 in Fig, 7 and neither the instruction (or data) cache 700 in
function master (or processor) 210 1 is part of the secure
memory subsystem 200. Further, there is no teaching in Foster
that instruction (or data) cache 700 is “secure” or “secure
memory”. As such, Examiner’s conclusion that “cache 720 is a
secure cache because it stores secure data and it is protected by
the secure access control” (OA dated 08/02/2017, p, 15, lines 4–
6) is erroneous for several reasons. First, the fact that cache 700
can receive what was secured data while saved within secure
memory region of non-volatile memory 260 does transform
cache 700 into a “secure memory”. Second, even if there are
some “secure access control” functions handled by access
control in IC 200, there is no further teaching that nonsecure
data is not moved into and out of cache 700. Third, there is no
recitation of the term “secure access control” in Foster and
Examiner fails to set forth the components/elements he
considers comprises “secure access control” in Foster,
Appeal Br. 9.
We are not persuaded by this argument, which relies upon attorney
argument, and not evidence of record, as to how the recited “secure internal
memory” should be construed differently from the broadest reasonable
interpretation set forth by the Examiner. Attorney arguments and conclusory
statements that are unsupported by factual evidence are entitled to little
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probative value. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see
also In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984).6
We are also unpersuaded by this argument because claim 9 generally
recites a “system,” and Appellant appears to argue patentability based upon
the disclosed but unclaimed location of Appellant’s secure memory being
somehow different than the arrangement of components in the Foster
reference.7 Appeal Br. 9. Further, we find Appellant is arguing limitations
not found in the claim, i.e., the phrase “secure access control,” argued by
Appellant (id.), is admittedly not used in Foster, but also is not recited in the
claims.
Therefore, on this record, we are not persuaded the Examiner erred in
finding that Foster teaches or suggests the recited “secure internal memory,”
as found in claim 9, and as similarly recited in method claim 20, i.e., “a
secure memory.”
Processor coupled to the secure internal memory
The Examiner cites either processor 210 or 200 in Foster (see Foster
Figs. 2 and 7; ¶ 74) as teaching or suggesting this contested limitation. Final

6 “Argument in the brief does not take the place of evidence in the record.”
In re Schulze, 346 F.2d 600, 602 (CCPA 1965) (citing In re Cole, 326 F.2d
769, 773 (CCPA 1964)). See also In re Lovin, 652 F.3d 1349, 1357 (Fed.
Cir. 2011)(“[W]e hold that the Board reasonably interpreted Rule 41.37 to
require more substantive arguments in an appeal brief than a mere recitation
of the claim elements and a naked assertion that the corresponding elements
were not found in the prior art.”).
7 While we interpret claims broadly but reasonably in light of the
Specification, we nonetheless must not import limitations from the
Specification into the claims. See Phillips v. AWH Corp., 415 F.3d 1303,
1316, 1323 (Fed. Cir. 2005) (en banc) (citations omitted).
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Act. 8–9. We agree with the Examiner’s finding that Foster teaches or
suggests a processor “coupled to the . . . memory,” that further carries out
the various functions recited in claim 9.8 Final Act. 8–9; Ans. 6–7.
We also agree with the Examiner’s more detailed finding regarding
the functional limitations9 claimed in this disputed limitation:
A processor 210.sub.1 (i.e., the requesting functional master)
issues a request to read data from an external memory location.
This request is forwarded to the data access control function
240 and is processed using the access table[]248 to identify the
associated address range, and also the access parameters,
including an indicator that this request is for data to be
authenticated; [0075] The integrity check function 245
generates a new request for the appropriate integrity value in
external memory 260, and retrieves this encrypted integrity
value from the integrity table 263. In addition, the original read
request is sent to external memory 260, and the encrypted data
261 is retrieved. The integrity check function then calculates
and compares the integrity values as described above, and based
on a match, returns the decrypted data to an instruction or data
cache 700 associated with processor 210.sub.1[], and to connect
between secure internal memory and said external volatile
memory bypassing said external non-volatile memory (e.g.,
figs. 2 and 7, els. 210, 280, 700.
Ans. 6–7.

8 We give the term “coupled” the plain and ordinary meaning, which does
not require direct attachment of the processor to the secure internal memory.
9 These functional limitations include the processor being “operable to
decrypt and verify the integrity of the code pages thereby to transfer code
pages to said secure internal memory directly from said external non-volatile
memory bypassing said external volatile memory in respect of the code
pages.”
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Therefore, based upon the findings above, on this record, we are not
persuaded of error in the Examiner’s reliance on the cited prior art
combination to teach or suggest the disputed limitations of claim 9.
Issue (b): The Examiner did not rely upon impermissible hindsight
With respect to Issue (a), above, Appellant contends the “Examiner’s
determination is supposition not supported by fact which is little more than
improper hindsight reconstruction which must be reversed. There is simply
no teaching in Foster that instruction (or data) cache 700 is ‘a secure
internal memory’ as required by Claim 9. Moreover, Examiner provides
no evidence that Ginter teaches this deficiency in Foster.” Appeal Br. 9.
Further, Appellant contends the Examiner used “hindsight,” but does
not address the reasoning provided except as noted above. Id. By not
showing error in the reasoning provided, Appellant has not shown error in
the conclusion as to obviousness. See In re Cree, Inc., 818 F.3d 694, 702
n.3 (Fed. Cir. 2016) (viewing an “impermissible hindsight” argument as
“essentially a repackaging of the argument that there was insufficient
evidence of a motivation to combine the references”).
First, as explained in In re McLaughlin:
Any judgment on obviousness is in a sense necessarily a
reconstruction based upon hindsight reasoning, but so long as it
takes into account only knowledge which was within the level
of ordinary skill at the time the claimed invention was made
and does not include knowledge gleaned only from applicant’s
disclosure, such a reconstruction is proper.
In re McLaughlin, 443 F.2d 1392, 1395 (CCPA 1971).
Our review of the record establishes that the Examiner’s case for
obviousness is only based on knowledge which was within the level of
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ordinary skill at the time of Appellant’s invention and does not include
knowledge gleaned only from the Appellant’s disclosure.
Second, the Examiner identifies the relevant portions of each of the
references relied on throughout the Examiner’s Answer. See Ans. 5–8. To
the extent that the Examiner relies on the knowledge of one of ordinary skill
in the art to combine the teachings of the references, this practice is
consistent with current case law. For example, the Supreme Court explains:
Often, it will be necessary for a court to look to interrelated
teachings of multiple patents; the effects of demands known to
the design community or present in the marketplace; and the
background knowledge possessed by a person having ordinary
skill in the art, all in order to determine whether there was an
apparent reason to combine the known elements in the fashion
claimed by the patent at issue. To facilitate review, this analysis
should be made explicit. See In re Kahn, 441 F.3d 977, 988
(C.A.Fed.2006) (“[R]ejections on obviousness grounds cannot
be sustained by mere conclusory statements; instead, there must
be some articulated reasoning with some rational underpinning
to support the legal conclusion of obviousness”). As our
precedents make clear, however, the analysis need not seek out
precise teachings directed to the specific subject matter of the
challenged claim, for a court can take account of the inferences
and creative steps that a person of ordinary skill in the art
would employ.
KSR Int’l Co, v. Teleflex, Inc., 550 U.S. 398, 418 (2007).
In this case, the Examiner’s conclusions of obviousness are clearly
articulated and are based on detailed factual findings that are supported by
the references of record. See Ans. 3–27. Thus, we agree with the
Examiner’s findings and conclusions.
Moreover, Appellant has not demonstrated that the Examiner’s
proffered combination of references would have been “uniquely challenging
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or difficult for one of ordinary skill in the art.” See Leapfrog Enters., Inc. v.
Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550
U.S. at 418). Nor has Appellant provided objective evidence of secondary
considerations which our reviewing court guides “operates as a beneficial
check on hindsight.” Cheese Sys., Inc. v. Tetra Pak Cheese and Powder
Sys., 725 F.3d 1341, 1352 (Fed. Cir. 2013).
Accordingly, we do not find error in the Examiner’s obviousness
rejection of independent claim 9, and grouped claims 17 and 20 which fall
therewith. See Claim Grouping, supra.
Dependent Claims 15, 16, 18, 25, and 26
Although Appellant raised additional arguments for patentability of
dependent claims 15, 16, 18, 25, and 26, rejected on the same basis as
claim 9 (Appeal Br. 11–27), we are not persuaded of Examiner error in light
of the Examiner’s findings in the Final Action. We determine those
arguments are rendered moot by a preponderance of the evidence. See Final
Act. 10–14. Therefore, we adopt the Examiner’s findings and underlying
reasoning, which we incorporate herein by reference. Consequently, we
have found no reversible error in the Examiner’s rejections of claims 15, 16,
18, 25, and 26.
REPLY BRIEF
To the extent Appellant may advance new arguments in the Reply
Brief (Reply Br. 1–21) not in response to a shift in the Examiner’s position
in the Answer, arguments raised in a Reply Brief that were not raised in the
Appeal Brief or are not responsive to arguments raised in the Examiner’s
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Answer will not be considered except for good cause (see 37 C.F.R.
§ 41.41(b)(2)), which Appellant has not shown.
CONCLUSION
The Examiner did not err with respect to the obviousness rejection of
claims 9, 15–18, 20, 25, and 26 under 35 U.S.C. § 103(a) over the cited prior
art combination of record, and we sustain the rejection.
DECISION SUMMARY
Claims
Rejected
35 U.S.C.
§
Basis /
References Affirmed Reversed
9, 15–18,
20, 25, 26 103(a)
Obviousness
Foster, Ginter
9, 15–18,
20, 25, 26
FINALITY AND RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37
C.F.R. § 41.50(f).
AFFIRMED