SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Patent Trials and Appeals Board

Feb 25, 2022

2021000882 (P.T.A.B. Feb. 25, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/728,182 10/09/2017 Kyoung Min LEE FSC75555US 1017 134545 7590 02/25/2022 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (DW) 5005 E. McDowell Road, Maildrop A700 Phoenix, AZ 85008 EXAMINER ALMO, KHAREEM E ART UNIT PAPER NUMBER 2849 NOTIFICATION DATE DELIVERY MODE 02/25/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patents@onsemi.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte KYOUNG MIN LEE and KAITLYN SITCH Appeal 2021-000882 Application 15/728,182 Technology Center 2800 Before BEVERLY A. FRANKLIN, DONNA M. PRAISS, and JENNIFER R. GUPTA, Administrative Patent Judges. GUPTA, Administrative Patent Judge. DECISION ON APPEAL1 1 In this Decision, we refer to the Specification filed October 9, 2017 (“Spec.”); the Final Office Action dated November 18, 2019 (“Final Act.”); the Appeal Brief filed March 25, 2020 (“Appeal Br.”); the Examiner’s Answer dated October 1, 2020 (“Ans.”); and the Reply Brief filed November 17, 2020. Appeal 2021-000882 Application 15/728,182 2 Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the Examiner’s decision to reject claims 1-6 and 8.3 We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. CLAIMED SUBJECT MATTER The claims are directed to a set and reset pulse generator circuit. Spec. 1, ll. 11-12. Claim 1, reproduced below with emphasis to highlight key disputed limitations, is illustrative of the claimed subject matter: 1. A set and reset pulse generator circuit, comprising: a set circuit that is configured to receive an input signal, to generate a voltage on a node of the set circuit using the input signal, and to generate a set pulse in accordance with the input signal, the voltage on the node of the set circuit, and a voltage on a node of a reset circuit; the reset circuit that is configured to receive the input signal, to generate the voltage on the node of the reset circuit using the input signal, and to generate a reset pulse in accordance with the input signal, the voltage on the node of the set circuit, and the voltage on the node of the reset circuit; a first cross-coupling circuit that is configured to couple the voltage on the node of the set circuit to the reset circuit; and 2 Appellant refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Semiconductor Components Industries, LLC. Appeal Br. 3. 3 Claims 9-16 and 18-20 are allowed. Final Act. 5. Claim 17 was canceled in the Amendment filed October 1, 2019. Claim 7 is objected to as being dependent on a rejected base claim, but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims. Id. at 4. Appeal 2021-000882 Application 15/728,182 3 a second cross-coupling circuit that is configured to couple the voltage on the node of the reset circuit to the set circuit. Appeal Br. 17 (Claims App.) (emphasis added). REFERENCE The prior art relied upon by the Examiner is: Name Reference Date Confalonieri et al. US 7,283,005 B2 Oct. 16, 2007 REJECTION The Examiner maintains the rejection of claims 1-6 and 8 under 35 U.S.C. § 102(a)(1) over Confalonieri. Final Act. 2-4; Ans. 3. DISCUSSION The dispositive issue on appeal is whether the Examiner reversibly erred in finding that Confalonieri discloses a set circuit configured to receive an input signal and a reset circuit that is configured to receive the same input signal. Final Act. 2. Anticipation is established when a single prior art reference discloses all the elements of the claimed invention. In re Spada, 911 F.2d 705, 708 (Fed. Cir. 1990). The Examiner finds that Confalonieri’s Figure 3, reproduced below with annotations based on the Examiner’s findings, discloses claim 1’s set and reset pulse generator circuit. Final Act. 2. Appeal 2021-000882 Application 15/728,182 4 Confalonieri’s annotated Figure 3 depicts an embodiment of its clock- pulse generator identifying with red boxes what the Examiner finds corresponds to claim 1’s set circuit (126, 120, and 122) and reset circuit (132 and 128), and labeling, in red, gate NAND-B and what the Examiner finds corresponds to claim 1’s “input signal” (164 or 114). The Examiner finds that Figure 3’s pulse generator includes a set circuit (126, 120 and 122) that is configured to receive an input signal (164), to generate a voltage on a node of the set circuit using the input signal, and to generate a set pulse (at 140) in accordance with the input signal (164 or 114), the voltage on the node of the set circuit (170), and a voltage on a node (node 176) of a reset circuit. Final Act. 2 (emphasis added). The Examiner further finds that Figure 3’s pulse generator also includes a reset circuit (132 Appeal 2021-000882 Application 15/728,182 5 and 128) that is configured to receive the input signal (164 or 114), to generate the voltage on the node of the reset circuit (176) using the input signal (164 or 114), and to generate a reset pulse (at 142) in accordance with the input signal (164 or 114), the voltage on the node of the set circuit (170), and the voltage on the node of the reset circuit (176). Id. (emphasis added). Appellant argues that neither stop signal 164 nor feedback signal 114 is an input of NAND-B, associated with Confalonieri’s second ring oscillator 112. Appeal Br. 8-9. Thus, Appellant argues that Confalonieri fails to disclose that “input signal” 164 or 114 generates the set and reset pulses as required by claim 1. Id. at 9-10. We agree. The Examiner interprets each of Confalonieri’s stop signal 164 and feedback signal 114 to be an indirect “input signal” to NAND-B via NAND-A. See Ans. 3-5. We, however, find the Examiner’s interpretation of Confalonieri to be unreasonable and not supported by a preponderance of the evidence. As Appellant argues, the Examiner has not identified sufficient support for interpreting Confalonieri’s stop signal 164 as extending beyond NAND-A. See Reply Br. 3-4. Nor has the Examiner identified sufficient support for interpreting Confalonieri’s feedback signal 114 as an input to NAND-A. Because we find the Examiner’s interpretation of Confalonieri to be unreasonable, the Examiner has not shown that Confalonieri discloses all the elements of the claimed invention. Accordingly, we do not sustain the Examiner's § 102(a)(1) rejection based on Confalonieri. CONCLUSION The Examiner’s decision to reject claims 1-6 and 8 is reversed. Appeal 2021-000882 Application 15/728,182 6 DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-6, 8 102(a)(1) Confalonieri 1-6, 8 REVERSED