SAP SE

Patent Trials and Appeals Board

Jun 29, 2021

2020002051 (P.T.A.B. Jun. 29, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/213,754 07/19/2016 Ahmad Hassan 22135-0939001/151375US01 6747
32864 7590 06/29/2021
FISH & RICHARDSON, P.C. (SAP)
PO BOX 1022
MINNEAPOLIS, MN 55440-1022
EXAMINER
TSAI, SHENG JEN
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
06/29/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PATDOCTC@fr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte AHMAD HASSAN
____________________

Appeal 2020-002051
Application 15/213,7541
Technology Center 2100
____________________

Before JOHN A. JEFFERY, MARC S. HOFF, and CATHERINE SHIANG,
Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE

Appellants appeal under 35 U.S.C. § 134 from a Non-Final Rejection
of claims 1–20. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
Appellant’s invention is a system and method for determining a first
and second cost associated with a virtual memory page accessed during
execution of an application. The first cost is associated with a first memory
type, and the second cost is associated with a second memory type. The two

1 Appellants state that SAP SE is the real party in interest. Appeal Br. 4.
Appeal 2020-002051
Application 15/213,754

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costs are compared, and the virtual memory page is selectively migrated
from its current location based on the comparison result. Abstract.
Claim 1 is reproduced below:

1. A computer-implemented method executed by one or more
processors, the method comprising:

storing, by the one or more processors, an object in an
initial location based on a memory allocation function of a
plurality of memory allocation functions of an application,
a first memory allocation function being directed to a first
memory type and a second memory allocation function
being directed to a second memory type for storing the
object in a hybrid memory system;

determining, by the one or more processors, a first
cost and a second cost associated with a virtual memory
page accessed during execution of an application, the first
cost being calculated for the first memory type based on
costs for reading and writing the virtual memory page to and
from the first memory type, if the virtual page were stored
in the first memory type, and the second cost being
calculated for the second memory type based on costs for
reading and writing the virtual memory page to and from the
second memory type, if the virtual page were stored in the
second memory type;

comparing, by the one or more processors, the first cost and
the second cost to provide a comparison result;

determining, by the one or more processors, a current
location of the virtual memory page, the current location
comprising one of the first memory type and the second
memory type; and

selectively migrating, by the one or more processors,
the virtual memory page from the current location based on
the comparison result and the current location.
Appeal 2020-002051
Application 15/213,754

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The prior art relied upon by the Examiner as evidence is:

Name Reference Date
Magenheimer et al.
(“Magenheimer)
US 2014/0280685 A1 Sept. 18, 2014
Lim et al. (“Lim”) US 2017/0010817 A1 Jan. 12, 2017
Doerner US 2017/0060740 A1 Mar. 2, 2017
Gokita US 2017/0115892 A1 Apr. 27, 2017
Jayasena et al.
(“Jayasena”)
US 2017/0160955 A1 June 8, 2017

Claims 1, 3, 4, 6–8, 10, 11, 13–15, 17, 18, and 20 stand rejected under
35 U.S.C. § 103 as being unpatentable over Jayasena, Lim, and Gokita. Non-
Final Act. 6–21.
Claims 2, 9, and 16 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Jayasena, Lim, Gokita, and Doerner. Non-Final Act. 21–
23.
Claims 5, 12, and 19 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Jayasena, Lim, Gokita, and Magenheimer. Non-Final Act.
23–24.
Throughout this decision, we make reference to the Appeal Brief filed
Oct. 4, 2019 (“App. Br.”); the Reply Brief filed Jan. 17, 2020 (“Reply Br.”);
the Examiner’s Answer mailed Dec. 5, 2019 (“Ans.”); and the Non-Final
Action mailed May 23, 2019 (“Non-Final Act.”) for their respective details.
ISSUE
Does the combination of Jayasena, Lim, and Gokita teach or suggest a
plurality of memory allocation functions of an application, a first memory
allocation function being directed to a first memory type and a second
memory allocation function being directed to a second memory type?
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Application 15/213,754

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ANALYSIS
Each of independent claims 1, 8, and 15 recites, in pertinent part,
“storing . . . an object in an initial location based on a memory allocation
function of a plurality of memory allocation functions of an allocation, a first
memory allocation function being directed to a first memory type and a
second memory allocation function being directed to a second memory type
for storing the object in a hybrid memory system.” Appeal Br. 19, 21, and
23–24 (Claims App.) (emphasis added).
The Examiner finds that Jayasena does not teach multiple memory
allocation functions, and refers to Lim for a teaching of this claim limitation.
Non-Final Act. 7. The Examiner finds that Lim Figure 8 “shows memory
allocation scheme where a first memory allocation function is directed to
allocating memory space to a first memory type DRAM . . . and a second
Appeal 2020-002051
Application 15/213,754

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memory allocation function is directed to allocating memory space to a
second memory type NVM.” Non-Final Act. 7–8.
Figure 8 of Lim is reproduced below:

Lim describes Figure 8 as “describing memory allocation according to
some embodiments of the inventive concept.” Lim ¶ 38. Figure 8 illustrates
memory allocation dividing “a main memory into an operating system (OS)
area and an application area.” Lim ¶ 148. The application area “may store
first application data APPD_DRAM and second application data
ADDP_NVM (sic, APPD_NVM).” Lim ¶ 149.
Appellant argues, and we agree, that while Lim discloses performing a
VMEM allocation request using a function of “malloc(),” Lim makes no
mention of multiple memory allocation functions. Appeal Br. 11–12; Lim
¶ 161. We do not agree with the Examiner’s finding that Lim teaches two
discrete memory allocation functions, one for DRAM and one for NVM.
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Ans. 5–6. We find that Lim discloses only generic “memory allocation” and
mentions only one function, “malloc(),” and that in only one instance. Lim
¶ 161. By contrast, Appellant discloses allocating data from an application
by using “memory allocators.” In some implementations, “an NVM allocator
is provided as a default allocator for a hybrid memory system, and
allocations identified as critical allocations are conducted using a DRAM
allocator.” Spec. ¶ 21. “In order to differentiate between DRAM and NVM
allocations, implementations of the present disclosure provide distinct
memory allocators in the application, one managing pages mapped to
DRAM, and the other managing pages mapped to NVM.” Spec. ¶ 29.
“[T]here are four memory allocators at the application level. More
particularly, the DRAM allocators 308 include dram_malloc and
dram_mmap . . . and the NVM allocators 310 include nvm_malloc and
nvm_mmap.” Spec. ¶ 32.
We find that the cited portions of Jayasena, Lim, and Gokita do not
teach all the limitations of independent claims 1, 8, and 15. We do not
sustain the Examiner’s 35 U.S.C. § 103 rejection of claims 1, 3, 4, 6–8, 10,
11, 13–15, 17, 18, and 20.
Claims 2, 9, and 16
These claims depend respectively from independent claims 1, 8, and
15. As noted supra, we find that the combination of Jayasena, Lim, and
Gokita does not teach or suggest all the limitations of the independent
claims. The Examiner does not find that Doerner supplies any teachings to
cure the deficiencies of Jayasena, Lim, and Gokita. See Non-Final Act. 21-
23. Therefore, we do not sustain the Examiner’s 35 U.S.C. § 103 rejection of
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Application 15/213,754

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claims 2, 9, and 16, for the same reasons given supra with respect to
independent claims 1, 8, and 15.
Claims 5, 12, and 19
These claims depend respectively from independent claims 1, 8, and
15. As noted supra, we find that the combination of Jayasena, Lim, and
Gokita does not teach or suggest all the limitations of the independent
claims. The Examiner does not find that Magenheimer supplies any
teachings to cure the deficiencies of Jayasena, Lim, and Gokita. See Non-
Final Act. 23, 24. Therefore, we do not sustain the Examiner’s 35 U.S.C.
§ 103 rejection of claims 5, 12, and 19, for the same reasons given supra
with respect to independent claims 1, 8, and 15.

CONCLUSION
The cited portions of Jayasena, Lim, and Gokita do not teach or
suggest a plurality of memory allocation functions of an application, a first
memory allocation function being directed to a first memory type and a
second memory allocation function being directed to a second memory type.
The Examiner’s decision to reject claims 1–20 is reversed.

Appeal 2020-002051
Application 15/213,754

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DECISION SUMMARY
In summary:

Claims
Rejected
35 U.S.C. § Reference(s)/Basis  Affirmed Reversed
1, 3, 4, 6–8,
10, 11, 13–
15, 17, 18, 20
103 Jayasena, Lim,
Gokita
1, 3, 4, 6–8,
10, 11, 13–
15, 17, 18, 20
2, 9, 16 103 Jayasena, Lim,
Gokita, Doerner
2, 9, 16
5, 12, 19 103 Jayasena, Lim,
Gokita,
Magenheimer
5, 12, 19
Overall
Outcome
1–20

REVERSED