Rambus Inc.Download PDFPatent Trials and Appeals BoardAug 25, 20212020003210 (P.T.A.B. Aug. 25, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/525,379 05/09/2017 Frederick A. Ware 10304US03 8776 38489 7590 08/25/2021 Silicon Edge Law Group LLP 7077 Koll Center Pkwy Unit 183 Pleasanton, CA 94566 EXAMINER RIGOL, YAIMA ART UNIT PAPER NUMBER 2135 NOTIFICATION DATE DELIVERY MODE 08/25/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): Art@SiliconEdgeLaw.com USPTO@dockettrak.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte FREDERICK A. WARE, ELY TSERN, JOHN ERIC LINSTADT, THOMAS J. GIOVANNINI, CRAIG E. HAMPEL, SCOTT C. BEST, and JOHN YAN Appeal 2020-003210 Application 15/525,379 Technology Center 2100 Before JEREMY J. CURCURI, NATHAN A. ENGELS, and JAMES W. DEJMEK, Administrative Patent Judges. ENGELS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 13–23. No other claims are pending. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a) (2019). Appellant identifies the real party in interest as Rambus, Inc. Appeal Br. 1. Appeal 2020-003210 Application 15/525,379 2 CLAIMED SUBJECT MATTER Claim 13, reproduced below, is illustrative of the claimed subject matter: 13. A memory module comprising: a module interface; memory components, including a first memory component and a second memory component; and an address-buffer component having: a primary address interface coupled to the module interface to receive primary memory addresses expressed as primary-address bits; a primary chip-select interface coupled to the module interface to receive primary chip-select information as primary chip-select bits; a first secondary chip-select interface coupled to the first memory component; and a second secondary chip-select interface coupled to the second memory component; and logic to direct the primary chip-select information to the first secondary chip-select interface and disable the second secondary chip-select interface responsive to a subset of the primary-address bits and a subset of the primary chip-select bits. REJECTIONS Claims 13–15 and 19–21 stand rejected under 35 U.S.C. § 103 as being unpatentable in view of Muralimanohar (US 2014/0208156 A1; July 24, 2014) and Norman (US 2010/0157644 A1; June 24, 2010). Claims 16–18, 22, and 23 stand rejected under 35 U.S.C. § 103 as being unpatentable in view of Muralimanohar, Norman, and Matsumoto (US 2002/0191480 A1; Dec. 19, 2002). Appeal 2020-003210 Application 15/525,379 3 OPINION The Examiner determines that Muralimanohar teaches most of claim 13 except that the Examiner states that Muralimanohar does not expressly refer to disabling the inactive chip and cites Norman for its teachings regarding disabling data operations in deselected chips. Final Act. 4–5 (citing Norman ¶ 27). We begin our analysis with a brief review of Muralimanohar. Muralimanohar generally relates to memory access methods that “can be used to implement electronic memory devices that consume less power than traditional memory devices.” Muralimanohar ¶ 34. Muralimanohar describes two approaches that purport to facilitate memory access “while consuming relatively lower power by activating relatively less DRAM [(other memory types are also contemplated)] circuitry per memory access.” Muralimanohar ¶ 37. One approach is a Selective Bitline Activation (SBA) approach that selectively accesses single cache lines and the other approach is a Single Subarray Access (SSA) that “organizes the layout of DRAM chips and the mapping of data to DRAM chips so that an entire cache line can be fetched from a single DRAM memory chip of a [(multi-chip)] memory module.” Muralimanohar ¶¶ 37–38. Muralimanohar describes the SSA technique enables reading out an entire cache line “by activating only a single memory chip of a memory module.” Muralimanohar ¶ 38. As such Muralimanohar describes that “the SSA technique eliminates the need to activate every DRAM chip in a memory module when accessing a requested cache line.” Muralimanohar ¶ 66. In a disclosed embodiment, Muralimanohar describes a memory controller interfacing with a multi-chip DRAM memory module. Appeal 2020-003210 Application 15/525,379 4 Muralimanohar ¶ 67, Fig. 8. Muralimanohar describes that the addressing organization used by the memory controller allows for selectively enabling specific DRAM chips. Muralimanohar ¶ 68. “[A] portion of an address communicated by the memory controller 802 function as chip selects to enable selecting a specific one of the DRAM chips.” Muralimanohar ¶ 68. Figure 9 of Muralimanohar is illustrative and is reproduced below. Figure 9 of Muralimanohar is a diagram of a DRAM module (804) comprising a memory module buffer (908) and a plurality of DRAM chips (806a–806h). Muralimanohar ¶¶ 11–12, 72–73. Muralimanohar describes the “three MSBs [(i.e., most significant bits)] 916 of the address bus 914 are used by the demultiplexer 912 as chip selects to enable a specified one of the eight DRAM chips” Muralimanohar ¶ 73. Thus, as shown in Figure 9 of Muralimanohar, memory module buffer (908) includes an interface for receiving address bits (received by address Appeal 2020-003210 Application 15/525,379 5 buffer (910) and an interface for receiving chip select bits (received by demultiplexer (912)). Appellant argues that Muralimanohar uses only address bits for chip selection and that Muralimanohar does not respond to primary chip-select bits from a requesting controller by disabling a secondary chip-select interface. Appeal Br. 6–8. Appellant also argues Norman lacks any teaching of logic to disable a secondary chip-select interface responsive to a subset of primary chip-select bits, as claimed. Appeal Br. 8. Appellant also argues the term “chip select,” as applied to signals and corresponding nodes, “refers to control signals ‘to select individual integrated-circuit DRAM dies, or “chips,” for both access and power-state management.’” Appeal Br. 8 (quoting Spec. ¶ 35). Further, Appellant argues a person of ordinary skill would understand the difference between chip-select bits and “address bits” and the fact that claim 13 recites both terms further demonstrates the difference between the terms. Reply Br. 2. Appellant also argues “primary chip-select” refers to chip-select nodes and signals on the host side of a memory module, while “secondary chip-select” refers to nodes and signals on the memory-chip side. Appeal Br. 8. As discussed above, contrary to Appellant’s arguments, we agree with the Examiner (see, e.g., Final Act. 3–4; Ans. 4–5) that Muralimanohar teaches a memory module comprising memory module buffer component (908) comprising a primary address interface (i.e., the input to address buffer (910)) and a primary chip select interface (i.e., the interface to demultiplexer (912)). Muralimanohar’s three MSBs of the address bus are used exclusively as chip selects and constitute the primary chip-select bits as claimed. Ans. 4–5 (citing Muralimanohar ¶¶ 35, 68, 69, 70, 73). In further Appeal 2020-003210 Application 15/525,379 6 contrast to Appellant’s argument that Muralimanohar uses only address bits, Muralimanohar also contemplates using bits other than the MSB bits: “In some example implementations, three bits other than the MSB bits may be used instead.” Muralimanohar ¶ 73. Similarly, we disagree with Appellant’s arguments that the claim’s different use of chip-select and address distinguishes Muralimanohar, which also separately discloses address bits and address bus 914 interfaced with address buffer 910 separately from chip select bits 916. Muralimanohar ¶ 73, Fig. 9. Accordingly, having considered the Examiner’s rejection of claim 13 in light of each of Appellant’s arguments and the evidence of record, we disagree with Appellant and agree with the Examiner that claim 13 would have been obvious in view of Muralimanohar and Norman. Accordingly, we sustain the Examiner’s rejection of claim 13, as well as the Examiner’s rejections of claims 14–23, which Appellant does not substantively argue independently of claim 13. CONCLUSION The Examiner’s rejections of claims 13–23 are sustained. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 13–15, 19– 21 103 Muralimanohar, Norman 13–15, 19– 21 16–18, 22, 23 103 Muralimanohar, Norman, Matsumoto 16–18, 22, 23 Overall Outcome 13–23 Appeal 2020-003210 Application 15/525,379 7 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Copy with citationCopy as parenthetical citation