2019003443 (P.T.A.B. Dec. 24, 2020)

QUALCOMM Incorporated

Patent Trials and Appeals BoardDec 24, 2020

2019003443 (P.T.A.B. Dec. 24, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/271,812 05/07/2014 Suresh Kumar Venkumahanti 140211/1173-131 6649 115309 7590 12/24/2020 W&T/Qualcomm 106 Pinedale Springs Way Cary, NC 27511 EXAMINER WHEATON, BRADFORD F ART UNIT PAPER NUMBER 2193 NOTIFICATION DATE DELIVERY MODE 12/24/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ocpat_uspto@qualcomm.com patents@wt-ip.com us-docketing@qualcomm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte SURESH KUMAR VENKUMAHANTI, STEPHEN ROBERT SHANNON, and LIN WAN ____________ Appeal 2019-003443 Application 14/271,812 Technology Center 2100 ____________ Before ELENI MANTIS MERCADER, JOHNNY A. KUMAR, and NORMAN H. BEAMER, Administrative Patent Judges. BEAMER, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) the Examiner’s final rejection of claims 1–24. We have jurisdiction over the pending rejected claims under 35 U.S.C. § 6(b). We reverse. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies Qualcomm Incorporated as the real party in interest. (Appeal Br. 2.) Appeal 2019-003443 Application 14/271,812 2 THE INVENTION Appellant’s invention is directed to dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources. (Abstr.) Claim 1, reproduced below, is illustrative of the subject matter on appeal: 1. A dynamic load balancing circuit, comprising: a control unit communicatively coupled to a first cluster of one or more hardware threads and a second cluster of one or more hardware threads of a clustered processor core; the control unit configured to: determine whether a suboptimal load condition exists between the first cluster and the second cluster; and responsive to determining that a suboptimal load condition exists: transfer a content of one or more private registers of a first hardware thread of the one or more hardware threads of the first cluster to one or more private registers of a second hardware thread of the one or more hardware threads of the second cluster via shared hardware resources communicatively coupled to the first hardware thread and the second hardware thread; and swap a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources. REJECTIONS The Examiner rejected claims 1–3, 5, 8–13, 15, 18–20, and 22 under 35 U.S.C. 103(a) as being unpatentable over Song (US 2010/0146513 A1, Appeal 2019-003443 Application 14/271,812 3 pub. June 10, 2010) and Sato et al. (US 2014/0109098 A1, pub. Apr. 17, 2014). (Final Act. 4–7.) The Examiner rejected claims 4, 14, and 21 under 35 U.S.C. § 103(a) as being unpatentable over Song, Sato, and Zaarur et al. (US 2013/0061237 A1, pub. Mar. 7, 2013). (Final Act. 7–8.) The Examiner rejected claims 6, 7, 16, 17, 23, and 24 under 35 U.S.C. § 103(a) as being unpatentable over Song, Sato, and Krieger et al. (US 2011/0126200 A1, pub. May 26, 2011). (Final Act. 8–9.) ISSUE ON APPEAL Appellant’s arguments in the Appeal Brief present the following dispositive issue:2 Whether the Examiner erred in finding the combination of Song and Sato taught or suggested the independent claim 1 limitation, “a first cluster of one or more hardware threads and a second cluster of one or more hardware threads of a clustered processor core,” and the commensurate limitations of independent claims 10, 11, and 18. (Appeal Br. 7–8.) ANALYSIS For the claim limitation at issue, the Examiner relies on the disclosure in Song of remapping threads that are ready to transition into a deep low power state from one processor core to a different processor core if it is determined that the destination core would then consist of threads that would 2 Rather than reiterate the arguments of Appellant and the findings of the Examiner, we refer to the Appeal Brief (filed Aug. 29, 2018); the Reply Brief (filed Mar. 29, 2019); the Final Office Action (mailed May 2, 2018); and the Examiner’s Answer (mailed Feb. 5, 2019) for the respective details. Appeal 2019-003443 Application 14/271,812 4 all be in a lower power state, and then placing the destination core in a low power state to save power. (Final Act. 4; Ans. 3; Song Abstr., Figs. 3, 4, ¶¶ 12, 34, 38–41.) The Examiner also relies on the disclosure in Sato of thread scheduling measures applied to groups of threads. (Final Act. 5; Sato Abstr., ¶¶ 8, 38, 94.) Appellant argues that, for the combination relied on by the Examiner: In one aspect according to Song, “an operating system may perform a logical remapping and task pulling to pull tasks from one hardware thread context on one core to another hardware thread context on a different core.” [Song ¶ 14] emphasis added. Thus, aspects disclosed by Song do not disclose or suggest “a first cluster . . . and a second cluster . . . of a clustered processor core” as claim 1 recites, but rather describe “hardware thread contexts” being reassigned from one processor core to a different processor core. Appellant's review of Sato did not locate any disclosure or suggestion of multiple “clusters” within a single “clustered processor core,” as recited by claim 1. (Appeal Br. 8 (emphasis omitted).) We agree with Appellant. Neither Song nor Sato teach or suggest the concept of groups of threads in a single processor core that are reassigned in accord with the requirements of the claims. The Examiner does not address this issue, and in particular provides no explanation or articulation that would provide support for finding that the combination of Song and Sato teaches or suggests this aspect of the claims. Accordingly, we are persuaded that the Examiner has not made out a prima facie case that the limitation at issue is taught or suggested by the cited references, and therefore we do not sustain the Examiner’s rejections of independent claims 1, 10, 11, and 18 as obvious over Song and Sato. For the same reason, we also do not sustain the Examiner’s obviousness Appeal 2019-003443 Application 14/271,812 5 rejections of claims 2, 3, 5, 8, 9, 12, 13, 15, 19, 20, and 22 over Song and Sato, which claims depend from claims 1, 11, or 18. In addition, in rejecting the remaining dependent claims, over Song, Sato, and Zaarur, or Song, Sato, and Krieger, the Examiner does not rely on Sato of Krieger with respect to the claim limitation discussed above. (See Final Act. 11–12; Appeal Br. 9.) Therefore we also do not sustain the Examiner’s rejection of claims 4, 6–7, 14, 16–17, 21, and 23–24. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference/Basis Affirmed Reversed 1–3, 5, 8–13, 15, 18–20, 22 103 Song, Sato 1–3, 5, 8–13, 15, 18–20, 22 4, 14, 21 103 Song, Sato, Zaarur 4, 14, 21 6–7, 16–17, 23–24 103 Song, Sato, Krieger 6–7, 16–17, 23–24 Overall Outcome 1–24 REVERSED