Micron Technology, Inc.

Patent Trials and Appeals Board

Mar 4, 2022

2021003055 (P.T.A.B. Mar. 4, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/850,132 12/21/2017 Denzil S. Frost MI22-6416 6590 128753 7590 03/04/2022 Wells St. John, P.S. 601 W. Main Avenue Suite 600 Spokane, WA 99201 EXAMINER WALL, VINCENT ART UNIT PAPER NUMBER 2822 NOTIFICATION DATE DELIVERY MODE 03/04/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@wellsip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte DENZIL S. FROST and TUMAN EARL ALLEN III Appeal 2021-003055 Application 15/850,132 Technology Center 2800 Before KAREN M. HASTINGS, JEFFREY B. ROBERTSON, and JAMES C. HOUSEL, Administrative Patent Judges. HOUSEL, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the Examiner’s decision to reject claims 22, 23, 25, 27-29, 32, 34, and 35.1,2 See Final Office Action (“Final Act.”) dated July 8, 2020, 1. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies Micron Technology, Inc. as the real party in interest. Appeal Brief (“Appeal Br.”) filed November 24, 2020, 3. 2 Although the Examiner includes claim 26 in the statement of rejection in both the Final Office Action and Examiner’s Answer, claim 26 was canceled in an amendment filed May 19, 2020. Appeal 2021-003055 Application 15/850,132 2 CLAIMED SUBJECT MATTER The invention recited in the claims on appeal relates to an array of memory cells comprising at least two tiers or levels of memory cells. Specification (“Spec.”) filed December 21, 2017, ¶ 29. Claim 22, reproduced below from the Claims Appendix to the Appeal Brief, is illustrative of the claimed subject matter. The limitations at issue are italicized. 22. An array of memory cells, comprising: an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines crossing the inner tier lower first conductive lines, and programmable material elevationally between the inner tier lower first conductive lines and the inner tier upper second conductive lines at respective locations where such cross; first insulative material laterally between the inner tier upper second conductive lines having respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier upper second conductive lines, the respective elevationally outermost surfaces of the first insulative material being elevationally outward of elevationally innermost surfaces of the inner tier upper second conductive lines; second insulative material elevationally over the first insulative material and laterally between the inner tier upper second conductive lines, the second insulative material being of different composition from that of the first insulative material, the second insulative material and the inner tier upper second conductive lines having respective elevationally outermost surfaces that are elevationally coincident; an elevationally outer tier of memory cells comprising spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines crossing the outer tier lower first Appeal 2021-003055 Application 15/850,132 3 conductive lines, and programmable material of elevationally between the outer tier lower first conductive lines and the outer tier upper second conductive lines at respective locations where such cross; third insulative material above and directly against the second insulative material laterally between the spaced outer tier lower first conductive lines, the third insulative material being of different composition from that of the second insulative material, the third insulative material having respective elevationally innermost surfaces that are lower than elevationally outermost surfaces of immediately laterally- adjacent of the outer tier lower first conductive lines; and the spaced outer tier lower first conductive lines and the spaced inner tier upper second conductive lines comprising differing materials relative to each other and together forming respective shared conductive lines having vertically-continuous conductive material from tops to bottoms of the respective shared conductive lines, each of the shared conductive lines comprising a lower portion consisting of the respective inner tier upper second conductive line and an upper portion consisting of respective outer tier lower first conductive line, the second insulative material being in direct physical contact with the vertically-continuous conductive material only along the lower portion. Appeal Br. 20, Claims App. Remaining independent claim 34 recites a memory cell array similar to claim 22, and further requiring that the programmable material of the elevationally inner tier of memory cells is in direct physical contact with the inner tier upper second conductive lines. Appeal 2021-003055 Application 15/850,132 4 REFERENCES The Examiner relies on the following prior art to reject the claims: Name Reference Date Cooney, III et al. US 6,674,168 B1 Jan. 6, 2004 Takase US 8,040,715 B2 Oct. 18, 2011 Laxman et al. US 2002/0172766 A1 Nov. 21, 2002 Clark et al. US 2004/0033631 A1 Feb. 19, 2004 Toda US 2006/0268594 A1 Nov. 30, 2006 Sokolik et al. US 2007/0058426 A1 Mar. 15, 2007 Toyoda et al. US 2007/0202699 A1 Aug. 30, 2007 Tagami US 2012/0276735 A1 Nov. 1, 2012 REJECTIONS The Examiner maintains, and Appellant requests our review of, the following rejections under 35 U.S.C. § 103: 1. Claims 22, 23, 27, 28, and 32 as unpatentable over Toda in view of Cooney and Sokolik; 2. Claim 25 as unpatentable over Toda in view of Cooney and Sokolik, and further in view of Clark and Laxman; 3. Claim 29 as unpatentable over Toda in view of Cooney and Sokolik, and further in view of Toyoda and Tagami; and 4. Claims 34 and 35 as unpatentable over Toda in view of Cooney and Sokolik, and further in view of Takase. OPINION We review the appealed rejections for error based upon the issues Appellant identifies, and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential) Appeal 2021-003055 Application 15/850,132 5 (cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) (“[I]t has long been the Board’s practice to require an applicant to identify the alleged error in the examiner’s rejections.”)). After considering the Examiner’s and Appellant’s respective positions and the evidence of record, we are persuaded of reversible error in the stated rejections for reasons set forth in the Appeal and Reply Briefs. Rejection 1: Obviousness over Toda, Cooney, and Sokolik The Examiner rejects claims 22, 23, 27, 28, and 32 under 35 U.S.C. § 103 as unpatentable over Toda in view of Cooney and Sokolik. Final Act. 2-10. The Examiner finds that Toda discloses a stacked memory cell array substantially as recited in claim 22, except for: 1) a second insulative material elevationally between, and made from a different material from, first insulative material 17 and third insulative material 19; 2) conductive word lines 18ab comprising spaced outer tier lower first conductive lines and spaced inner tier second conductive lines made of differing materials relative to each other; and 3) the second insulative material and the inner tier upper second conductive lines having respective elevationally outermost surfaces that are elevationally coincident. Id. at 2-4, 8. For feature 1), the Examiner finds that Cooney teaches first insulative material 345a, 346a (which can be SiN), second insulative material 355a (which can be SiOx), and third insulative material 360a (which can be SiN). Final Act. 5. The Examiner also finds that Toda forms conductive word line WL0 simultaneously with plugs in insulating layer 17 using a dual damascene process and Cooney similarly teaches forming a metallization by a dual damascene process using laminates of the first, second, and third insulative materials. Id. The Examiner concludes that it would have been Appeal 2021-003055 Application 15/850,132 6 obvious to have modified Toda’s array by replacing Toda’s first and second insulative materials 17, 19 with first SiN, second SiOx, and third SiN insulative materials, as taught in Cooney, to facilitate reworking single layer defective back end of line (“BEOL”) levels, without having to remove multiple layers. Id. With regard to feature 2), the Examiner finds that Sokolik teaches that word lines may comprise bilayers of different conductive materials for improving switching time and lower voltage, thereby creating more efficient memory cells. Final Act. 8-9. Therefore, the Examiner concludes that it would have been obvious to have modified Toda’s word lines 18ab to comprise two layers of different conductive material in order to improve switching time and lower voltage for more efficient memory cells in the array. Id. at 9. With regard to feature 3), the Examiner determines that the combination of Toda and Cooney would provide a first insulative material with elevationally outermost surfaces that are outward of the elevationally innermost surfaces of the inner tier upper second conductive lines, as well as a second insulative material with elevationally outermost surfaces that are elevationally coincident with the elevationally outermost surfaces of the inner tier upper second conductive lines. Final Act. 6-7. Appellant argues that Toda, Cooney, and Sokolik fail to teach or support the Examiner’s placement of a second insulative material between Toda’s first and second insulative materials 17, 19 as set forth in the Examiner’s annotated Figure 8 from Toda. Appeal Br. 12. Appellant also argues that the applied prior art similarly fails to teach or support the Examiner’s placement of the division of Toda’s word line 18ab into two Appeal 2021-003055 Application 15/850,132 7 different layers as shown in the Examiner’s annotated figure. Id. at 12-13. As such, Appellant contends that the Examiner’s placement of the respective second insulative layer and the division between the word line bilayer in the annotated figure is arbitrary and based on improper hindsight reconstruction. Id. at 13. In response, the Examiner finds that Cooney’s purpose of providing a plurality of insulating layers is to allow reworking or removing of a layer if that layer was incorrectly formed. Ans. 12. The Examiner finds that Cooney’s insulating layers act as a stop for ensuring that only the defective layer is removed. Id. at 12-13. Based on these findings, the Examiner determines that “it is logical that a POSITA would place a[n] insulating layer coplanar with the inner tier upper conductive line (N) of Sokolik in order to allow for rework of the outer tier lower conductive [line] (M) of Sokolik.” Id. at 13. The Examiner further finds that Cooney teaches the use of multiple insulating layers because the error may be formed not just in a layer above, but also a current layer. Id. The Examiner reasons, therefore, that it would have been obvious to form the top of the inner tier upper conductive line and the top of the second insulative layer to be coplanar to allow for any rework in the formation of the outer tier lower conductive line. Id. In rebuttal, Appellant asserts that Cooney’s teaching is directed to back end of line processing where levels have lines and vias embedded in dielectric layers, wherein such BEOL levels are interconnect layers formed over logic/functional layers of an integrated circuit (“IC”) chip. Reply Brief filed April 6, 2021, 3. Appellant contends that Cooney’s “reworking” process is specific to such BEOL features and elements. Id. Appellant Appeal 2021-003055 Application 15/850,132 8 further contends that the Examiner fails to explain how such “reworking” could be accomplished in Toda’s non-BEOL logic/functional areas, which could affect the ability to perform a reworking process. Id. at 3-4. Appellant’s arguments are persuasive of reversible error because the prior art, at best, merely suggests that a plurality of insulative layers may be provided, but fails to teach or suggest the placement of such layers, in particular, the placement of the second insulative layer, in Toda’s array as recited in claims 22 and 34. The Examiner explains that the only logical placement of the outermost surfaces of a second insulative material in Toda, as modified in view of Cooney and Sokolik, is coincident with the outermost surfaces of upper conductive lines of inner tier MA0, which is distinct in material from lower conductive lines of outer tier MA1. However, the Examiner’s logic would appear to run contrary to placement of the outermost surfaces of the first insulative material outward of the innermost surfaces of the inner tier upper conductive lines, such that the innermost surfaces of the second insulative material are outward of the innermost surfaces of the upper conductive lines of inner tier MA0. In other words, following the Examiner’s logic for placement of the outermost surfaces of the second insulative material coincident with the outermost surfaces of the upper conductive lines of the inner tier, an ordinary artisan also would have placed the outermost surfaces of the first insulative material coincident with the innermost surfaces of the upper conductive lines of the inner tier. Such placement is contrary to claims 22 and 34. Notwithstanding the above, as Appellant contends, Cooney distinguishes BEOL processing for the final dielectric and conductive interconnects and vias from front end processing for electronically active Appeal 2021-003055 Application 15/850,132 9 devices such as transistors. Cooney 1:32-35 (“[S]top on top of the dielectric and tungsten interconnect region residing the electronically active devices such as transistors (typically called the front end.”), 1:41-43 (“[T]hese conventional processes do not address rework of the final metal in addition to the dielectric BEOL.”). Moreover, Cooney teaches that these BEOL sections are above the IC chip’s sections comprising logical and functional devices. Id. at 2:47-53 (“[A] first section comprising logical and functional devices and interconnection layers above the first section. Each of the interconnection layers comprises a first insulator layer, a second insulator layer above the first insulator layer and electrical wiring within the first insulator layer and the second insulator layer.”). Therefore, Cooney’s teaching regarding the provision of multiple insulative layers within an interconnect layer containing metal conductive wiring to allow for reworking of the wiring would not have suggested the use of multiple insulative layers in Toda’s structure, as modified in view of Sokolik, for the purpose of reworking the upper conductive lines of inner tier MA0. This is because Toda’s stacked memory cells are akin to front end logical and functional structures, rather than Cooney’s BEOL interconnects and vias. Accordingly, we do not sustain the Examiner’s obviousness rejection of claim 22, or dependent claims 23, 27, 28, and 32, over the combination of Toda, Cooney, and Sokolik. Rejections 2-4: Obviousness of Claims 25, 29, 34, and 35 The Examiner rejects, as unpatentable under 35 U.S.C. § 103, claim 25 over Toda in view of Cooney and Sokolik, and further in view of Clark and Laxman; claim 29 over Toda in view of Cooney and Sokolik, and further in view of Toyoda and Tagami; and claims 34 and 35 over Toda in Appeal 2021-003055 Application 15/850,132 10 view of Cooney and Sokolik, and further in view of Takase. Final Act. 11- 18. However, the Examiner does not rely on the above tertiary references to remedy the deficiencies in the combination of Toda, Cooney, and Sokolik discussed above. Accordingly, for the same reasons given above, we likewise do not sustain the Examiner’s obviousness rejections of claims 25, 29, 34, and 35. CONCLUSION Upon consideration of the record and for the reasons set forth above and in the Appeal and Reply Briefs, the Examiner’s decision to reject claims 22, 23, 25, 27-29, 32, 34, and 35 under 35 U.S.C. § 103 is reversed. DECISION SUMMARY The following table summarizes the outcome of each rejection: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 22, 23, 27, 28, 32 103 Toda, Cooney, Sokolik 22, 23, 27, 28, 32 25 103 Toda, Cooney, Sokolik, Clark, Laxman 25 29 103 Toda, Cooney, Sokolik, Toyoda, Tagami 29 34, 35 103 Toda, Cooney, Sokolik, Takase 34, 35 Overall Outcome 22, 23, 25, 27-29, 32, 34, 35 REVERSED