KIPB LLC et al.

Patent Trials and Appeals Board

Oct 27, 2020

90014227 - (D) (P.T.A.B. Oct. 27, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/014,227 10/31/2018 6885055 K107992.1010US.REX 8099
26158 7590 10/27/2020
WOMBLE BOND DICKINSON (US) LLP
ATTN: IP DOCKETING
P.O. BOX 7037
ATLANTA, GA 30357-0037
EXAMINER
WHITTINGTON, KENNETH
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/27/2020 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte KIPB LLC
Patent Owner and Appellant
____________

Appeal 2020-004990
Reexamination Control 90/014,227
Patent 6,885,055 B2
Technology Center 3900
____________

Before JOHN A. JEFFERY, ERIC B. CHEN, and MINN CHUNG,
Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON APPEAL
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Patent 6,885,055 B2

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Pursuant to 35 U.S.C. §§ 134(b) and 306, Patent Owner1 appeals from
the final rejection of claims 1–6, 11–13, and 15–17. Claims 7–10, 14, 18,
and 19 were not subject to reexamination. We have jurisdiction under
35 U.S.C. § 6(b).
An oral hearing was held on August 31, 2020. The record includes a
written transcript of the oral hearing.
We AFFIRM IN PART.

STATEMENT OF THE CASE
Reexamination Proceedings
A request for ex parte reexamination of U.S. Patent No. 6,885,055 B2
(“the ’055 patent”) was filed on October 31, 2018, and assigned
Reexamination Control No. 90/014,227. The ’055 patent, titled “Double-
Gate FinFET Device and Fabricating Method Thereof,” issued April 26,
2005 to Jong-Ho Lee, based on Application No. 10/358,981, filed
February 4, 2003.

Claimed Subject Matter
The claims are directed to an electrically stable double-gate FinFET
device, in which the Fin active region is formed on a bulk silicon substrate
and where the device channel and the body are to be formed has a nano-size

1 Patent Owner identifies the real party in interest as KIPB LLC (formerly
KAIST IP US LLC). (Appeal Br. 4.)
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width connected to the substrate and is formed with the shape of a wall
along the channel length direction. (Abstract.)

Related Litigation
The ’055 patent has been asserted in KAIST IP US LLC v. Samsung
Electronics Co., Ltd., No. 2:16-cv-01314 (E.D. Tex. Nov. 29, 2016). The
jury found that defendants willfully infringed claims 1–6, 11–13, and 15–17
of the ’055 patent. (Appeal Br. 6.) The final judgement is currently
appealed to the U.S. Court of Appeals for the Federal Circuit. (Reply Br. 5.)
The ’055 patent has also been asserted in KAIST IP US LLC v.
Samsung Electronics Co., Ltd., No. 2:19-cv-00056 (E.D. Tex. Feb. 14,
2019). The case is pending. (Appeal Br. 7.)
The ’055 patent was also the subject of the petitions for inter partes
review in the following proceedings: (i) Samsung Electronics Co. v. KAIST
IP US LLC, Nos. IPR2017-01046 and IPR2017-01047 (PTAB Oct. 2, 2017);
and (ii) Samsung Electronics Co. v. KAIST IP US LLC, Nos. IPR2018-00266
and IPR2018-00267 (PTAB May 29, 2018). Institution of inter partes
review was denied in all of the aforementioned AIA proceedings.

The Claims
Claims 1 and 13 are illustrative of the claimed subject matter, and are
reproduced below with disputed limitations in italics:
1. A double-gate FinFET device, comprising:
a bulk silicon substrate;
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a Fin active region which is a wall-shape single
crystalline silicon on a surface of the bulk silicon substrate and
connected to said bulk silicon substrate;
a second oxide layer which is formed up to a certain
height of the Fin active region from the surface of bulk silicon
substrate;
a gate oxide layer which is formed on both side-walls of
the Fin active region protruded from said second oxide layer;
a first oxide layer which is formed on the upper surface
of said Fin active region with a thickness greater or equal to
that of the gate oxide;
a gate which is formed on said first and second oxide
layer;
a source/drain region which is formed on both sides of
the Fin active region except where said gate overlaps with the
Fin active region; and
a contact region and a metal layer which are formed at
said source/drain and gate contact region,
wherein the thickness of said gate oxide layer is between
0.5 nm and 10 nm, and the thickness of said first oxidation
layer is between 0.5 nm and 200 nm.

13. A double-gate FinFET device, comprising:
a bulk silicon substrate;
a Fin active region which is a wall-shape single
crystalline silicon on a surface of the bulk silicon substrate and
connected to said bulk silicon substrate;
a second oxide layer which is formed up to a certain
height of the Fin active region from the surface of bulk silicon
substrate;
a gate oxide layer which is formed on both side-walls of
the Fin active region protruded from said second oxide layer;
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a first oxide layer which is formed on the upper surface
of said Fin active region with a thickness greater or equal to
that of the gate oxide;
a gate which is formed on said first and second oxide
layer;
a source/drain region which is formed on both sides of
the Fin active region except where said gate overlaps with the
Fin active region; and
a contact region and a metal layer which are formed at
said source/drain and
gate contact region, wherein the resistance of said Fin
active region is reduced by enlarging the width of said Fin
active region within the oxidation layer as it approaches the
bulk silicon substrate.

REFERENCES
Name Reference Date
Hisamoto et al. US 5,115,289 May 19, 1992
Chen et al. US 6,720,619 B1 Apr. 13, 2004
Mizuno et al. JP 1996-139325 A May 31, 1996
Inokawa et al. JP 2,633,001 B2 Apr. 25, 1997
Yagishita et al. JP H10-93093 A Apr. 10, 1998

Patent Owner also relied upon the following in rebuttal to the
Examiner’s rejections:
Declaration under 37 C.F.R. § 1.132 of Kelin J. Kuhn, Ph.D.,
dated April 13, 2019.
Supplemental Declaration under 37 C.F.R. § 1.132 of Kelin J.
Kuhn, Ph.D., dated September 18, 2019.
Rebuttal Declaration under 37 C.F.R. § 1.132 of Kelin J. Kuhn,
Ph.D., dated May 25, 2020.

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The Rejections
A. Claims 1, 5, 6, and 13 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Inokawa.
B. Claims 2–4, 16, and 17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Inokawa and Yagishita.
C. Claim 15 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Inokawa and Chen.
D. Claims 1–6, 13, 16, and 17 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by Hisamoto.
E. Claims 4, 5, 11, 12, and 17 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Hisamoto.
F. Claim 15 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hisamoto and Chen.2
G. Claims 1–6, 13, 16, and 17 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Mizuno.
H. Claim 15 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Mizuno and Chen.

2 Patent Owner has not presented any arguments with respect to the
rejection of: (i) dependent claims 2–4, 16, and 17 under 35 U.S.C. § 103(a)
as unpatentable over Inokawa and Yagishita; (ii) dependent claim 15 under
35 U.S.C. § 103(a) as unpatentable over Inokawa and Chen; (iii) dependent
claims 4, 5, 11, 12, and 17 under 35 U.S.C. § 103(a) as unpatentable over
Hisamoto; and (iv) dependent claim 15 under 35 U.S.C. § 103(a) as
unpatentable over Hisamoto and Chen. Thus, any such arguments are
deemed to be waived. Accordingly, we sustain these rejections under
35 U.S.C. § 103(a).
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OPINION
§ 102 Rejection—Inokawa
Claims 1, 5, and 6
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 41–
45) that Inokawa does not disclose the limitation “a Fin active region which
is a wall-shape single crystalline silicon on a surface of the bulk silicon
substrate and connected to said bulk silicon substrate,” as recited in
independent claim 1.
The Examiner found that channel region 3 of Inokawa formed over
substrate 1, as illustrated in Figure 1(d) of Inokawa, corresponds to the
limitation “a Fin active region which is a wall-shape single crystalline
silicon on a surface of the bulk silicon substrate and connected to said bulk
silicon substrate.” (Final Act. 16; see also Ans. 14.) In particular, the
Examiner found that “the Fin active region 3 is shown connected to the
substrate 1, albeit through a narrowed region.” (Ans. 14.) We agree with
the Examiner’s findings.
Inokawa relates to an insulated gate field effect transistor (IG-FET)
(p. 4, col. 2, para. 2) having a “protruding or plate-like semiconductor region
. . . vertically disposed on the substrate, such that the active region is
structured to contact the semiconductor substrate at a narrow surface
including the direction connecting the source region and the drain region”
(p. 7, col. 2, para. 1). Figure 1(d) of Inokawa, a cross-sectional view of an
IG-FET, which includes thin plate-like Si 9 (or channel region 3),
monocrystalline Si substrate 1, and field oxide film 2, is reproduced below:
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Figure 1(d) of Inokawa illustrates a cross-sectional view of an IG-FET.
Inokawa explains that “the IG-FET of the present embodiment has thin
plate-like Si 9 having a height H and a thickness D arranged vertically with
respect to the monocrystalline Si substrate 1” and “field oxide film [2] for
element isolation, such as an oxidized Si film, and the thin plate-like
Si 9 . . . is in contact with the substrate 1 through an opening formed in the
film 2.” (P. 4, col. 2, para. 2.) As illustrated in Figure 1(d), the “contact”
interface between channel region 3 and substrate 1 is indicated by a dashed
line. Moreover, Inokawa explains the following:
With the above structure, the box-type channel region 3
bounded by the gate oxide film 4 is surrounded on six surfaces,
a first surface being in contact with the source region 6 and a
second surface opposite to the first surface being in contact with
the drain region 7. A third surface including the direction
connecting the source region 6 and the drain region 7 is in
contact with the substrate 1.
(Id. para. 3.)
Figure 4(a) of Inokawa, which illustrates a cross-sectional view of Si
substrate 1 and plate-like Si 9 during one step in the manufacturing process,
is reproduced below:
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Figure 4(a) of Inokawa illustrates a cross-sectional view of Si substrate 1
and plate-like Si 9.
In reference to Figure 4(a), Inokawa explains that “directional etching was
performed on the nitride film 62, the oxide film 14, and the Si substrate 1
using a simple resist pattern as a mask to obtain the structure of the
protruding or plate-like Si 9 shown.” (P. 5, col. 2, para. 5.)
Figure 4(c) of Inokawa, which illustrates a cross-sectional view of Si
substrate 1, plate-like Si 9, and field oxide film 2 during another step in the
manufacturing process, is reproduced below:

Figure 4(c) of Inokawa illustrates a cross-sectional view of Si substrate 1,
plate-like Si 9, and field oxide film 2
In reference to Figure 4(c), Inokawa explains the following:
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The field oxide film 2 was formed by selectively
thermally oxidizing the planar portion of the substrate l to a
thickness or 200 to 600 nm using the nitride films 62 and 64
attached to the periphery of the plate-shaped Si 9 as a mask.
Subsequently, after removing the nitride films 62 and 64 with
hot phosphoric acid, the thin oxide films 61 and 63 covering the
plate-like Si 9 were removed . . . .
(P. 5, col. 2, last para.)
Because Inokawa explains that: (i) plate-like Si 9, which is later
formed into channel region 3, is in contact with substrate 1 through an
opening formed in field oxide film 2; and (ii) one surface of tile box-type
channel region 3 contacts substrate 1, Inokawa discloses the limitation “a
Fin active region which is a wall-shape single crystalline silicon on a surface
of the bulk silicon substrate and connected to said bulk silicon substrate.”
First, Patent Owner argues that Inokawa does not disclose “analogous
‘Fin active Regions’ (viz., Inokawa’s ‘box type channel region 3’. . . ) . . . on
the surface of the substrate” because “an intermediate silicon material . . . is
disposed between the analogous ‘Fin active region’. . . and the surface of the
substrate.” (Appeal Br. 41.) Patent Owner also points to paragraph 23 of
the Supplemental Kuhn Declaration, which states the following:
Neither Inokawa . . . disclose that their analogous “Fin active
Regions” (i.e., Inokawa’s “box type channel region 3”. . .) are
on the surface of the substrate. As the above annotated
illustrations show [Figure 1(d) of Inokawa], each of those
references teaches that an intermediate silicon material . . . is
disposed between the analogous “Fin active region” and the
surface of the substrate . . . .
(Supp. Kuhn Decl. ¶ 23 (emphasis omitted).) Contrary to Patent Owner’s
arguments, the Examiner found that the region between the two field oxide
films 2 of Inokawa, directly beneath box type channel region 3 (i.e., Patent
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Owner’s “intermediate silicon material”) is a part of substrate 1. Again,
Inokawa explains that “thin plate-like Si 9 . . . is in contact with the
substrate 1 through an opening formed in the film 2.” (P. 4, col. 2, para. 2.)
Moreover, Figures 4(a) and 4(c) of Inokawa illustrate that thin plate-like
Si 9, which is formed by directionally etching substrate 1, includes both: (i)
box type channel region 3; and (ii) the silicon region immediately beneath
box type channel region 3, between the two field oxide films 2 (i.e., Patent
Owner’s “intermediate silicon material”).
Second, Patent Owner argues that “the separation between their
analogous Fin active regions and their substrates is a direct consequence of
the specific fabrication process for those devices, namely, LOCal Oxidation
of Silicon (‘LOCOS’)” and “[i]n the LOCOS fabrication process, silicon
dioxide is used to oxidize the surface of the silicon, thereby creating an
insulating oxide layer between the Fin active region and the silicon
substrate.” (Appeal Br. 42.) Patent Owner also points to paragraph 110 of
the Kuhn Declaration, which states the following:
The bird’s beak ensures that the field oxide film 2 is
significantly intruded under the projection and (more
importantly) ensures that the channel region is electrically
isolated from the substrate. . . . In every single Inokawa
embodiment the field oxide 2 is significantly intruded under the
projection. As a consequence of this, the monocrystalline
substrate 1 in Inokawa is not “a bulk silicon substrate,” because
field oxide film 2 serves as an insulating layer that isolates the
channel regions from the substrate. The active region is not
connected to, but instead physically isolated from, the substrate.
This creates an SOI-like device, not a genuine bulk device.
(Kuhn Decl. ¶ 110.) However, Patent Owner’s arguments are inconstant
with Inokawa because Figure 1(d) of Inokawa indicates that the two field
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oxide films 2 remain separated by an “opening formed in the [oxide] film 2.”
Moreover, Figure 1(d) of Inokawa does not illustrate that the two field oxide
films 2 encroach upon one another.
Third, Patent Owner argues the following:
Inokawa does state that its “box type channel region 3” is
“connected to” and “in contact with” the semiconductor
substrate, but that disclosure relates to the claims’ latter
limitation “connected to said bulk silicon substrate”, not its
former separate limitation “on a surface of the bulk silicon
substrate”. Indeed, Inokawa makes clear that its “box type
channel region 3” connects to (or is in contact with) the
semiconductor substrate “through an opening formed in the
[oxide layer] film 2” – that is, through the intermediate silicon
material.
(Appeal Br. 45 (emphases and footnote omitted).) Patent Owner also points
to paragraph 24 of the Supplemental Kuhn Declaration, which states the
following:
Inokawa does state that its “box type channel region 3” is
“connected to” and “in contact with” the semiconductor
substrate, but that disclosure relates to the claims’ latter
limitation “connected to said bulk silicon substrate”, not its
former limitation “on a surface of the bulk silicon substrate”. I
understand that the Examiners have interpreted “connected to”
to include a connection through the intermediate silicon
material, which I will use solely for purposes of this
proceeding.
(Supp. Kuhn Decl. ¶ 24 (emphases and citation omitted).) Again, the
Examiner found that the region between the two field oxide films 2 of
Inokawa, directly beneath box type channel region 3 (i.e., Patent Owner’s
“intermediate silicon material”) is a part of substrate 1, and as discussed
previously, such findings are supported by Inokawa.
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Therefore, we agree with the Examiner that Inokawa discloses the
limitation “a Fin active region which is a wall-shape single crystalline
silicon on a surface of the bulk silicon substrate and connected to said bulk
silicon substrate,” as recited in claim 1.
Accordingly, we sustain the rejection of independent claim 1 under
35 U.S.C. § 102(b). Claims 5 and 6 depend from claim 1, and Patent Owner
has not presented any additional substantive arguments with respect to these
claims. Therefore, we sustain the rejection of claims 5 and 6 under
35 U.S.C. § 102(b) for the same reasons discussed with respect to
independent claim 1.

Claim 13
We are persuaded by Patent Owner’s argument (Appeal Br. 48) that
Inokawa does not disclose the limitation “wherein the resistance of said Fin
active region is reduced by enlarging the width of said Fin active region
within the oxidation layer as it approaches the bulk silicon substrate,” as
recited in independent claim 13.
The Examiner found that the “enlarged/widened portion” of silicon
between the two channel regions 2, as illustrated in Figure 1(d) of Inokawa,
corresponds to the limitation “wherein the resistance of said Fin active
region is reduced by enlarging the width of said Fin active region within the
oxidation layer as it approaches the bulk silicon substrate.” (Final Act. 20.)
In particular, the Examiner found that “the Fin active region 3 expands in
width with a rounded corner as it approaches the bulk silicon substrate 1.”
(Id.) We do not agree with the Examiner’s findings.
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As discussed previously, Figure 1(d) of Inokawa illustrates that the
“contact” interface between channel region 3 and substrate 1 is indicated by
a dashed line. Moreover, Inokawa explains that channel region 3 has a
“box-type” shape. (P. 4, col. 2, para. 3.)
Although the Examiner cited to the “enlarged/widened portion” of
silicon between the two channel regions 2, as illustrated in Figure 1(d) of
Inokawa, the Examiner has provided insufficient evidence to support a
finding that Inokawa discloses the limitation “wherein the resistance of said
Fin active region is reduced by enlarging the width of said Fin active region
within the oxidation layer as it approaches the bulk silicon substrate.” In
particular, such “enlarged/widened portion” of silicon resides in substrate 1
of Inokawa, rather than channel region 3. Thus, on this record, the Examiner
has not demonstrated that Inokawa discloses the limitation “wherein the
resistance of said Fin active region is reduced by enlarging the width of said
Fin active region within the oxidation layer as it approaches the bulk silicon
substrate.”
Accordingly, we are persuaded by Patent Owner’s argument, as
follows:
In Inokawa . . . there can be no legitimate dispute that the
silicon material through the oxide layer is significantly
narrowed, directly contrary to the ’055 patent’s express claim
language and teachings. By pointing to a tiny drawn chamfer at
the bottom of that narrowed region – the so-called “bird’s beak”
– as somehow satisfying the claim language is entirely
unreasonable.
(Appeal Br. 48 (citations omitted).)
Therefore, we do not agree with the Examiner that Inokawa discloses
the limitation “wherein the resistance of said Fin active region is reduced by
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enlarging the width of said Fin active region within the oxidation layer as it
approaches the bulk silicon substrate.”
Accordingly, we do not sustain the rejection of independent claim 13
under 35 U.S.C. § 102(b).

§ 102 Rejection—Hisamoto
Claims 1–6, 16, and 17
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 41–
45) that Hisamoto does not disclose the limitation “a Fin active region which
is a wall-shape single crystalline silicon on a surface of the bulk silicon
substrate and connected to said bulk silicon substrate,” as recited in
independent claim 1.
The Examiner found that Fin active region 100 connected to substrate
10, as illustrated in Figures 3a–3c of Hisamoto, corresponds to the limitation
“a Fin active region which is a wall-shape single crystalline silicon on a
surface of the bulk silicon substrate and connected to said bulk silicon
substrate.” (Final Act. 28; see also Ans. 14.) In particular, the Examiner
found that “[a]s shown in Hisamoto FIG. 3b . . . the Fin active region 100 is
connected to the substrate 10, albeit through a narrowed region.” (Ans. 14.)
We agree with the Examiner’s findings.
Hisamoto relates to an FET “having a channel or a charge coupled
portion formed in a thin semiconductor layer which is substantially
perpendicular to the substrate.” (Abstract.) Figure 3c of Hisamoto, a cross-
sectional view of an FET, including substrate 10, insulating layer 20, and
semiconductor layer 100, is reproduced below:
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Figure 3c of Hisamoto illustrates a cross-sectional view of an FET.
Figure 3c of Hisamoto illustrates “Embodiment 2” of the FET, in which “the
substrate crystal and the thin film (the semiconductor layer) are connected to
each other, it is possible to form the insulating layer 20, having an opening,
on the substrate, and to have epitaxial growth of the substrate crystal from
such opening, thereby obtaining the semiconductor layer 100.”3 (Col. 10,
ll. 60–63.) Moreover, Figure 3c of Hisamoto illustrates a dashed line that
separates semiconductor layer 100 and substrate 10. With respect to
“Embodiment 2,” Hisamoto further explains the following:
In the device structure of the Embodiment 1, in the
condition when the insulating layers extending from both sides
are not connected to the lower part of the semiconductor layer,
the effect of the separation between the element and the
substrate by electric insulation will be lost. However, it is
possible to have good control of electric characteristics of the
channel due to field effect made by the gate on both sides, with

3 Paragraph 68 of the Rebuttal Kuhn Declaration states the following:
Epitaxy (or epitaxial growth) is the process of growing single
crystal material on a single crystal starting substrate.
Meticulous attention to processing conditions allows new
individual atoms to precisely bond to the crystal lattice of the
underlying substrate, replicating that crystal lattice exactly.
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respect to the channel produced in thin film semiconductor, or
to maintain characteristics of the element suitable to integration.
(Col. 10, ll. 35–45.)
Because Hisamoto explains that semiconductor layer 100 is formed on
substrate 10 via epitaxial growth through the opening in insulating layer 20,
Hisamoto teaches the limitation “a Fin active region which is a wall-shape
single crystalline silicon on a surface of the bulk silicon substrate and
connected to said bulk silicon substrate.”
First, Patent Owner argues that Hisamoto does not disclose
“analogous ‘Fin active regions’ (viz., . . . Hisamoto’s ‘semiconductor layer
100’) are on the surface of the substrate” because “an intermediate silicon
material . . . is disposed between the analogous ‘Fin active region’ . . . and
the surface of the substrate.” (Appeal Br. 41.) Patent Owner also points to
paragraph 23 of the Supplemental Kuhn Declaration, which states the
following:
Neither . . . Hisamoto disclose[s] that their analogous “Fin
active regions” (i.e., . . . Hisamoto’s “semiconductor layer
100”) are on the surface of the substrate. As the above
annotated illustrations show [Figure 3(c) of Hisamoto], each of
those references teaches that an intermediate silicon material
. . . is disposed between the analogous “Fin active region” and
the surface of the substrate.
(Supp. Kuhn Decl. ¶ 23 (emphasis omitted).) Contrary to Patent Owner’s
arguments, the Examiner found that the “narrow region” immediately
beneath semiconductor layer 100 of Hisamoto, surrounded by two insulating
layers 20 (i.e., Patent Owner’s “intermediate silicon material”) is a part of
substrate 10. Again, Figure 3c of Hisamoto illustrates a dashed line that
separates semiconductor layer 100 and substrate 10, and Hisamoto explains
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that “the substrate crystal and the thin film (the semiconductor layer) are
connected to each other, it is possible to form the insulating layer 20, having
an opening, on the substrate, and to have epitaxial growth of the substrate
crystal from such opening, thereby obtaining the semiconductor layer 100.”
(Col. 10, ll. 58–63.)
Second, Patent Owner argues that “the separation between their
analogous Fin active regions and their substrates is a direct consequence of
the specific fabrication process for those devices, namely, LOCal Oxidation
of Silicon (‘LOCOS’)” and “[i]n the LOCOS fabrication process, silicon
dioxide is used to oxidize the surface of the silicon, thereby creating an
insulating oxide layer between the Fin active region and the silicon
substrate.” (Appeal Br. 42.) Patent Owner also points to paragraph 343 of
the Kuhn Declaration, which states the following:
Hisamoto creates field oxide layer (20) by oxidizing underneath
a nitride mask. The process is described several places in
Hisamoto, with a representative description at 8:9–21, “It is
possible to form thick field oxidation film selectively on the
surface of the substrate 10, other than the semiconductor layer
100, by removing the silicon oxide film 152 in the portion not
covered with silicon nitride films 701 and 700, in applying
etching with mixture of various hydrofluoric acids on the above
substrate and, further, in applying light etching on the silicon at
the lower level of the semiconductor layer 100 by use of wet
etching with HF/HNO solution, and then by field oxidation in
wet environment of 1100° C. This oxide film becomes the
insulating layer 20. At this time, due to growth of the oxide
film from both sides, the extending oxidized films will be
connected together, thereby separating the semiconductor layer
100 from the substrate 10.”
(Kuhn Decl. ¶ 343.) However, the Kuhn Declaration discusses
“Embodiment 1” of Hisamoto, rather than “Embodiment 2” of Hisamoto,
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which was cited by the Examiner. Patent Owner’s arguments are inconstant
with Hisamoto because Figure 3c of Hisamoto indicates that “it is possible
to form the insulating layer 20, having an opening, on the substrate, and to
have epitaxial growth of the substrate crystal from such opening, thereby
obtaining the semiconductor layer 100.” (Col. 10, ll. 60–63.) Furthermore,
Figure 3c of Hisamoto does not illustrate that the two insulating layers 20
encroach upon one another.
Last, Patent Owner argues that that following:
Similarly, Hisamoto states that the “substrate crystal and the
thin film (the semiconductor layer [100]) are connected to each
other”, but that disclosure again relates to the claims’ latter
limitation “connected to said bulk silicon substrate”, not its
former separate limitation “on a surface of the bulk silicon
substrate”. Indeed . . . Hisamoto makes clear that its
“semiconductor layer 100” connects to the semiconductor
substrate through “the insulating layer 20, having an opening” –
that is, through the intermediate silicon material.
(Appeal Br. 46.) Again, the Examiner found that the “narrow region”
immediately beneath semiconductor layer 100 of Hisamoto, surrounded by
two insulating layers 20 (i.e., Patent Owner’s “intermediate silicon
material”) is a part of substrate 10, and as discussed previously, such
findings are supported by Hisamoto.
Therefore, we agree with the Examiner that Hisamoto discloses the
limitation “a Fin active region which is a wall-shape single crystalline
silicon on a surface of the bulk silicon substrate and connected to said bulk
silicon substrate,” as recited in claim 1.
Accordingly, we sustain the rejection of independent claim 1 under
35 U.S.C. § 102(b). Claims 2–6, 16, and 17 depend from claim 1, and
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Patent Owner has not presented any additional substantive arguments with
respect to these claims. Therefore, we sustain the rejection of claims 2–6,
16, and 17 under 35 U.S.C. § 102(b) for the same reasons discussed with
respect to independent claim 1.

Claim 13
We are persuaded by Patent Owner’s argument (Appeal Br. 48) that
Hisamoto does not describe the limitation “wherein the resistance of said Fin
active region is reduced by enlarging the width of said Fin active region
within the oxidation layer as it approaches the bulk silicon substrate,” as
recited in independent claim 13.
The Examiner found that the “enlarged/widened portion” of silicon
between the two insulating layers 20, as illustrated in Figure 3c of Hisamoto,
corresponds to the limitation “wherein the resistance of said Fin active
region is reduced by enlarging the width of said Fin active region within the
oxidation layer as it approaches the bulk silicon substrate.” (Final Act. 35.)
In particular, the Examiner found that “Fin active region 100 shrinks and
expands within the second oxide layer 20.” (Id.) We do not agree with the
Examiner’s findings.
As discussed previously, Hisamoto explains that “it is possible to
form the insulating layer 20, having an opening, on the substrate [10], and to
have epitaxial growth of the substrate [10] crystal from such opening,
thereby obtaining the semiconductor layer 100.” (Col. 10, ll. 60–63.)
Moreover, Figure 3c of Hisamoto illustrates a dashed line that separates
semiconductor layer 100 and substrate 10.
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Although the Examiner cited to the “enlarged/widened portion” of
silicon between the two insulating layers 20, as illustrated in Figure 3c of
Hisamoto, the Examiner has provided insufficient evidence to support a
finding that Inokawa discloses the limitation “wherein the resistance of said
Fin active region is reduced by enlarging the width of said Fin active region
within the oxidation layer as it approaches the bulk silicon substrate.” In
particular, such “enlarged/widened portion” between the two insulating
layers 20 resides in substrate 1 of Hisamoto (i.e., below the dashed line
separating semiconductor layer 100 and substrate 10 in Figure 3c of
Hisamoto). On this record, the Examiner has not demonstrated that
Hisamoto discloses the limitation “wherein the resistance of said Fin active
region is reduced by enlarging the width of said Fin active region within the
oxidation layer as it approaches the bulk silicon substrate.”
Accordingly, we are persuaded by Patent Owner’s argument, as
follows:
In . . . Hisamoto, there can be no legitimate dispute that the
silicon material through the oxide layer is significantly
narrowed, directly contrary to the ’055 patent’s express claim
language and teachings. By pointing to a tiny drawn chamfer at
the bottom of that narrowed region [Figure 3c of Hisamoto] –
the so-called “bird’s beak” – as somehow satisfying the claim
language is entirely unreasonable.
(Appeal Br. 48 (citations omitted).)
Therefore, we do not agree with the Examiner that Hisamoto
describes the limitation “wherein the resistance of said Fin active region is
reduced by enlarging the width of said Fin active region within the oxidation
layer as it approaches the bulk silicon substrate.”
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Thus, we do not sustain the rejection of independent claim 13 under
35 U.S.C. § 102(b).

§ 103 Rejection—Mizuno
Claims 1–6
We are persuaded by Patent Owner’s arguments (Appeal Br. 52) that
Mizuno would not have rendered obvious independent claim 1, which
includes the limitation “a Fin active region which is a wall-shape single
crystalline silicon on a surface of the bulk silicon substrate and connected to
said bulk silicon substrate.”
The Examiner found that Fin active region 52 of Mizuno, as
illustrated in Figure 17, corresponds to the limitation “a Fin active region
which is a wall-shape single crystalline silicon on a surface of the bulk
silicon substrate and connected to said bulk silicon substrate.” (Final
Act. 40; see also Ans. 18.) In particular, the Examiner found that “the Fin
active region is the entire projection part 52 that includes an impurity
layer 54 in the middle thereof” and “as shown in FIG. 17, this entire Fin
active region/projection part 52 is connected to and on the surface of the
substrate.” (Ans. 18.) We do not agree with the Examiner’s findings.
Mizuno relates to a semiconductor device, in particular, “a substrate 1
having a projecting semiconductor element region.” (Abstract.) Figure 17
of Mizuno, which illustrates a perspective view of a metal oxide
semiconductor (MOS) transistor, is reproduced below:
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Figure 17 of Mizuno illustrates a perspective view of an MOS transistor.
Mizuno explains that “by etching a p-type silicon substrate 51. . . a
projection 52 having a width of 0.1 μm is formed, an insulating film 53 is
embedded in the element isolation region.” (¶ 65.) Moreover, Mizuno
explains that “boron ions are implanted into the projection 52, and
consequently, a p-type impurity layer 54 . . . is formed at a position that is
deeper than 0.3 μm from the upper surface of the projection 52.” (Id.)
Moreover, Figure 17 of Mizuno illustrates that projection 52 directly
contacts a p-type impurity layer 54, such that p-type impurity layer 54 is an
intervening layer between projection 52 and substrate 51.
Although the Examiner cited generally to Figure 17 of Mizuno, the
Examiner has provided insufficient evidence to support a finding that
Mizuno teaches the limitation “a Fin active region which is a wall-shape
single crystalline silicon on a surface of the bulk silicon substrate and
connected to said bulk silicon substrate.” Because Figure 17 of Mizuno
illustrates that p-type impurity layer 54 is an intervening layer between
projection 52 and substrate 51, Mizuno does not teach the limitation “a Fin
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active region . . . on a surface of the bulk silicon substrate,” as recited in
claim 1.
Accordingly, we are persuaded by Patent Owner’s argument that
“Mizuno’s projection part 52 is a distinct layer between the distinct impurity
layer 54 . . . and the distinct source/drain regions 57/58.” (Appeal Br. 52.)
Therefore, we do not agree with the Examiner that Mizuno teaches the
limitation “a Fin active region which is a wall-shape single crystalline
silicon on a surface of the bulk silicon substrate and connected to said bulk
silicon substrate.”
Thus, we do not sustain the rejection of independent claim 1 under
35 U.S.C. § 103(a). Claims 2–6, 16, and 17 depend from claim 1. We do
not sustain the rejection of claims 2–6, 16, and 17 under 35 U.S.C. § 103(a)
for the same reasons discussed with respect to claim 1.
Independent claim 13 recites limitations similar to those discussed
with respect to claim 1. We do not sustain the rejection of claim 13 under
35 U.S.C. § 103(a) for the same reasons discussed with respect to claim 1.

§ 103 Rejection—Mizuno and Chen
We do not sustain the rejection of dependent claim 15 under
35 U.S.C. § 103(a) as unpatentable over Mizuno and Chen for the same
reasons as discussed previously with respect to the rejection of claims 1–6,
13, 16, and 17 as being unpatentable under 35 U.S.C. § 103(a) over Mizuno.

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DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 5, 6 102(b) Inokawa 1, 5, 6
13 102(b) Inokawa 13
2–4, 16, 17 103(a) Inokawa, Yagishita 2–4, 16, 17
15 103(a) Inokawa, Chen 15
1–6, 16, 17 102(b) Hisamoto 1–6, 16, 17
13 102(b) Hisamoto 13
4, 5, 11, 12,
17
103(a) Hisamoto 4, 5, 11, 12,
17

15 103(a) Hisamoto, Chen 15
1–6, 13, 16,
17
103(a) Mizuno 1–6, 13, 16,
17
15 103(a) Mizuno, Chen 15
Overall
Outcome
1–6, 11, 12,
15–17
13

REQUESTS FOR EXTENSIONS OF TIME
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).

AFFIRMED IN PART

msc

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PATENT OWNER:
WOMBLE BOND DICKINSON (US) LLP
ATTN: IP DOCKETING
P.O. Box 7037
Atlanta, GA 30357-0037

THIRD PARTY REQUESTER:

PAUL HASTINGS LLP
875 15TH Street, NW
Washington, DC 20005