Kinetic Technologies, Inc.v.Skyworks Solutions, Inc.

Patent Trial and Appeal Board

Sep 29, 2014

11582927 (P.T.A.B. Sep. 29, 2014)

Trials@uspto.gov Paper 8
Tel: 571-272-7822 Entered: September 29, 2014

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________
KINETIC TECHNOLOGIES, INC.,
Petitioner,

v.
SKYWORKS SOLUTIONS, INC.,
Patent Owner.
_______________

Case IPR2014-00530
Patent 7,921,320 B2
_______________

Before GLENN J. PERRY, SCOTT A. DANIELS, and
BARRY L. GROSSMAN, Administrative Patent Judges.

GROSSMAN, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
37 C.F.R. § 42.108

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I. INTRODUCTION
Kinetic Technologies, Inc. (“Petitioner”) filed a Petition requesting inter
partes review of claims 13–22 and 37–45 of U.S. Patent No. 7,921,320 B2
(Ex. 1001, “the ’320 patent”). Paper No. 1 (“Pet.”). Skyworks Solutions, Inc.,
(“Patent Owner”), filed a Preliminary Response. Paper No. 6 (Prelim. Resp.”).
We have jurisdiction under 35 U.S.C. § 314.
We determine that the information presented does not show that there is a
reasonable likelihood that Petitioner would prevail in establishing the
unpatentability of any of claims 13–22 and 37–45. Accordingly, we deny the
Petition and do not institute an inter partes review of the ’320 patent.
A. Related Proceedings
Petitioner informs us of the following related matters.
The ’320 patent is at issue in Skyworks Solutions, Inc. v. Kinetic
Technologies, Inc., Case No. 1:13-cv-10655 (D. Mass.), filed March 20, 2013; and
also in Skyworks Solutions, Inc. v. Kinetic Technologies, Inc., Case No. 3:14-cv-
00010 (N.D. Cal.), filed January 2, 2014.
The ’320 patent is a continuation of U.S. Application 10/144,333, now U.S.
Patent No. 7,127,631, which is the subject of Reexamination Control No.
95/000,501. U.S. Patent No. 7,127,631 is at issue in Advanced Analogic
Technologies, Inc. v. Kinetic Technologies, Inc., Case No. 3:09-cv-01360 (N.D.
Cal.), filed March 2, 2009.
U.S. Application 14/028,365, filed September 16, 2013, currently claims
priority to the ’320 patent.
Petitioner filed another Petition (IPR-2014-00529) requesting inter partes
review of the ’320 patent on grounds different from the grounds asserted against
the challenged claims in the Petition in this case.
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We also are aware that U.S. Patent No. 8,539,275 B2, a continuation of
application no. 11/582,927, now the ’320 patent, is the subject of a Petition, also
filed by Petitioner, to institute an inter partes review (IPR2014-00690).
B. The ’320 Patent
The ’320 patent, entitled “Single Wire Serial Interface,” relates generally to
control interfaces for integrated circuits (ICs) and other devices. Ex. 1001, col. 1,
ll. 14–15. The device disclosed in the ’320 patent provides a single wire serial
interface that may be used to control stand-alone power ICs and other devices. Id.
at col. 1, ll. 62–64. When so used, an IC is configured to include a sensing circuit,
a counter, and a ROM or similar decoder. Id., at col. 1, ll. 64–66.
The ’320 patent describes that stand-alone power systems for power
integrated circuits are often constrained by package size and cost, and where most
of the available pins in such stand-alone power applications are used for power
load, there are few pins in the interface left to accommodate power control
functions. Id. at col. 1, ll. 34–43. The ’320 patent states that ideally in such
applications, minimal pins, or a single pin “interface would be able to
accommodate a wide variety of control needs and be scaleable to many levels of
complexity.” Id. at col. 1, ll. 52–58.
Figure 2 of the ’320 patent, reproduced below, illustrates integrated
circuit (IC) 200, which has a single wire serial interface. Id. at col. 2, ll. 59–60.
According to the ’320 patent, to use a single wire serial protocol, compatible
devices must provide a single wire serial interface. Id. at col. 3, ll. 57–60. Figure
2 shows a block diagram of an IC configured to provide a single wire serial
interface. Id.
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As depicted by Figure 2 of the ’320 patent, integrated circuit 200 has one or
more inputs 202, and one or more outputs 204, as well as EN/SET signal input
206. EN/SET input 206 is connected to sensing circuit 210, which, as discussed
further below, determines the voltage state, i.e. high, low or toggling, of the
EN/SET signal. Id. at col. 3, l. 60–col. 4, l. 1.
Figure 1 of the ’320 patent, reproduced below, illustrates three waveform
types defining EN/SET signal. The first of these is a toggling waveform, where
the EN/SET signal is composed of a series of clock pulses. The second waveform
is where the EN/SET signal has a constant high value. The third waveform is
where the EN/SET signal has a constant low value. Ex. 1001, col. 3, ll. 27–34.

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The toggling waveform causes compatible devices to select particular
operational states. The total number of clock pulses (or rising edges) determines
the particular operational state that will be selected (i.e., four clock pulses selects
the fourth operational state). Id. at col. 3, ll. 35–39. The constant high waveform
causes compatible devices to maintain their previously selected operational states.
Id. at col. 3, ll. 43–44. The constant low waveform causes compatible devices to
power off (or otherwise adopt a predefined configuration) after a pre-defined
timeout period has elapsed. Id. at col. 3, ll. 47–49.
Sensing circuit 210 determines the waveform type of the EN/SET signal and
produces two output signals, Clock signal and Enable signal to send to the counter
212. Id. at col. 4, ll. 1–3. The ’320 patent states that:
a rising transition of the EN/SET signal causes sensing circuit 210 to
assert the Enable signal. Sensing circuit 210 holds the Enable signal
high until the EN/SET signal transitions to a logical low state and
remains in the low state until the predetermined timeout period has
elapsed.
Id. at col. 4, ll. 10–15. The Enable signal is a gate signal for the Clock signal, as
long as the Enable signal is high. The Clock signal is forwarded by sensing circuit
210 to counter 212. Id. at col. 4, ll. 15–18. In this case, counter 212 counts the
transitions, i.e. waveform pulses, forwarded by sensing circuit 210, e.g. 1, 2, 3,
4 . . . n, to determine a counter n-bit output. Id. at col. 4, ll. 22-23. Counter 212
resets to zero “when sensing circuit 210 transitions the Enable signal to a low
value.” Id. at col. 4, ll. 21–25.
Devices that implement a single wire serial interface as disclosed in the
’320 patent select a new control state each time a rising edge of a clock pulse is
received. Id. at col. 4, ll. 65–67. One result is that compatible devices
progressively select each control state in sequence until the desired control state is
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reached. Id. at col. 4, l. 67–col. 5, l. 2. Accordingly, selecting the eighth control
state means that compatible devices will progressively select control states one
through seven before finally selecting the eighth (desired) control state. Id. at
col. 5, ll. 2–5.
C. Illustrative Claim
Of the challenged claims, claims 13 and 37 are independent claims.
Claim 13 is illustrative of the claimed subject matter and is reproduced below.
13. A power integrated circuit device having at least one
input and at least one output, comprising:
a core circuit producing at least one output from the power
integrated circuit; and an interface for controlling the core
circuit, the interface including,
a first circuit for receiving a signal via a single input of the
integrated circuit, the first circuit for accumulating a count of
clock pulses encoded in the received signal;
a second circuit for mapping the count of encoded clock
pulses into a corresponding one of a plurality of control states for
the core circuit;
a third circuit for resetting the count of encoded clock pulses
to zero in response to the received signal being low for a period
that exceeds a predetermined timeout value, the predetermined
timeout value being longer than a width of one of the encoded
clock pulses;
the first circuit outputs progressively increasing count values
during the accumulating of the count of clock pulses encoded in
the received signal; and
the second circuit is responsive to the count values, and
operative to progressively map each of the count values output
during the accumulating to a corresponding one of a plurality of
intermediate control states.

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D. References Relied Upon
Petitioner relies upon the following prior art references:
Reference Pat. Number or
Reference ID
Date Exhibit Number
McIntyre “Automotive
Electronics: The
Future?,”
Automotive
Engineering,
vol. 97, no. 8
Aug. 1989 Ex. 1002
Renner US 4,114,366 Sept. 19, 1978 Ex. 1003
Park KR1994-0003509 Jan. 11, 1994 Ex. 1004
Ex. 1005 (Engl.
Trans.)
Yoshikawa JP Pub. H05-
35208 (A)
Feb. 12, 1993 Ex. 1007
Ex. 1008 (Engl.
Trans.)
E. The Asserted Grounds
Petitioner asserts the following grounds of unpatentability.
Claims Challenged Statutory Basis
(35 U.S.C.)
References
13–17, 19–21, and 37–
44
§§ 102 and/or 103 McIntyre
13, 18-19, 22, 37 and 45 § 102 Park
13, 15, 22, 37, 41, and
45
§§ 102 and/or 103 Yoshikawa
22 and 45 § 103 McIntyre and
Renner

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II. ANALYSIS
A. Claim Construction
In an inter partes review, “[a] claim in an unexpired patent shall be given its
broadest reasonable construction in light of the specification of the patent in which
it appears.” 37 C.F.R. § 42.100(b); see also Office Patent Trial Practice Guide,
77 Fed. Reg. 48756, 48764, 48766 (Aug. 14, 2012) (Claim Construction). The
broadest reasonable construction is “in light of the specification as it would be
interpreted by one of ordinary skill in the art.” In re Am. Acad. of Sci. Tech. Ctr.,
367 F.3d 1359, 1364 (Fed. Cir. 2004).
Petitioner proposes a specific construction for the phrase “receiving a signal
via a single input” in independent claims 13 and 37. Pet. 7–8. Petitioner asserts
that this phrase should be construed as “receiving a signal encoded with clock
pulses, which signal is the same signal encoding a low period that exceeds a
predetermined timeout value.” Id. at 8. Petitioner argues that the proposed claim
interpretation is required based on arguments in the prosecution history to
overcome a claim rejection. Id. at 7–8 (citing Ex. 1011, 288–289).
Patent Owner asserts that Petitioner’s proposed construction of the claim
phrase “receiving a signal via a single input” “is incorrect because it goes beyond
the broadest reasonable interpretation of the phrase.” Prelim. Resp. 24. According
to Patent Owner, the broadest reasonable interpretation of the phrase “is, simply,
that the signal is received ‘via a single input.’ Thus, no construction of ‘receiving
a signal via a single input’ is required.” Id. at 22.
For purposes of this decision, we agree with Patent Owner. Petitioner’s
proposed claim construction unduly limits the broadest reasonable interpretation of
the phrase “receiving a signal via a single input.” Accordingly, we determine that
no express construction of the phrase “receiving a signal via a single input” is
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necessary at this time.
B. Asserted Grounds of Unpatentability
1. Anticipation by and/or Obviousness in View of McIntyre
Petitioner asserts that claims 13–17, 19–21, and 37–44 are anticipated and/or
would have been obvious in view McIntyre. Patent Owner correctly argues,
however, that “the Petition does not set forth an obviousness analysis with respect
to McIntyre.” Prelim. Resp. 7. Petitioner provides no argument or evidence that
the challenged claims would have been obvious in view of McIntyre. Accordingly,
based on the information presented in the Petition, we determine that Petitioner has
not demonstrated a reasonable likelihood that it would prevail in establishing that
any of claims 13–17, 19–21, and 37–44 of the ’320 patent would have been
obvious based on McIntyre. We proceed to an analysis of the assertion that
McIntyre anticipates the challenged claims.
McIntyre relates to vehicle power train electronics, and acknowledges that in
1989 electronics were “playing a rapidly expanding role in automotive design,
manufacture, and function,” including areas such as “engine management.
electronic transmission and anti-skid braking systems, shock damping, four-wheel
steering, climate and cruise control, infrared door locking, air bags, and service
diagnostic computers.” Ex. 1002, 1, 3. As an example of the use of electronics in
cars, McIntyre referred to electronics used in a camshaft or crankshaft pick-up for
determining engine speed and position. Ex. 1002, 4 (Fig. 2), 5. Figure 2, shown
below, discloses spark and fuel injection control signals based on a cam-input
signal reflecting crankshaft rotation. Id.
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Figure 2 of McIntyre
McIntyre explains that microcontrollers used in powertrain control
applications use “input capture” to detect when rising or falling edges occur on an
input line. Id. at 5. Input capture records the time when an edge of a wave signal
is detected (see Fig. 2). Id. Based on this information, an output signal is
generated to drive the fuel injectors or spark plug coil(s). Id. Figure 2 shows how
an output signal is generated from a cam sensor signal. Id.
McIntyre further discusses auto electronics in the context of a distributorless
ignition system having a toothed wheel attached to a crankshaft or camshaft, which
generates a square wave output. Id. at 5–6. A microcontroller measures the square
wave period and counts the number of pulses. Id. at 6. McIntyre discloses that one
way of measuring the square wave period is with a 16-bit hardware timer in
capture mode. By using a timer in capture mode to measure engine speed, the
dedicated high-speed input/output channels of the microcontroller are free for other
tasks. Id.
Petitioner cites much of this same disclosure (Pet. 9–14) and concludes that
“each and every element of claim 13 is described in McIntyre; hence McIntyre
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anticipates claim 13.” Id. at 14.
1

“A claim is anticipated only if each and every element as set forth in the
claim is found, either expressly or inherently described, in a single prior art
reference.” Verdegaal Bros. v. Union Oil Co., 814 F.2d 628, 631 (Fed. Cir. 1987).
“The identical invention must be shown in as complete detail as is contained in the
claim.” Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236 (Fed. Cir. 1989).
The elements must be arranged as required by the claim, but this is not an
ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910
F.2d 831, 832 (Fed. Cir. 1990).
a. A Third Circuit
Independent claim 13 requires a third circuit for resetting the count of
encoded clock pulses to zero in response to the received signal being low for a
period that exceeds a predetermined timeout value. The predetermined timeout
value is longer than a width of one of the encoded clock pulses. Ex. 1001, col. 8,
ll. 65–67. Independent claim 37 is similar, but requires a third circuit for resetting
the count of encoded clock pulses to zero in response to the received signal being
at the first level (rather than “low,” as in claim 13). Claim 37 also requires a
transition from the second level to the first level after the period that exceeds a
predetermined timeout value. Id. at col. 11, ll. 37–42.
The ’320 patent discloses that “[h]olding the voltage at the EN/SET pin high
causes the counter to stop counting and maintain its value. Holding the voltage at
the EN/SET pin low for more than a preset timeout period causes the counter to

1
Petitioner repeats the same analysis and arguments for claim 37 as are made for
claim 13. See, e.g., Pet. 22 (“McIntyre teaches every element of claim 37 and so
claim 37 is anticipated by Mcintyre.”) We analyze claims 13 and 37 together
because of their substantial similarity. We will cite to the Petition and Petitioner’s
arguments only for claim 13 unless separate reference to claim 37 is required.
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reset to zero.” Ex. 1001, col. 2, ll. 6–10. As also explained in the ’320 patent,
counter 212 resets to zero when sensing circuit 210 transitions the Enable signal to
a low value. Id. at col. 4, ll. 23–25.
Petitioner asserts that McIntyre “teaches the third circuit for resetting the
count of encoded clock pulses to zero in response to the received signal being low
for a period that exceeds a predetermined timeout value, the predetermined timeout
value being longer than a width of one of the encoded clock pulses.” Pet. 12–13.
Petitioner points to Figures 2 and 3 in McIntyre for support. Id. at 13. Petitioner
also cites for support the Declaration of Prasant Mohapatra, Ph.D. Id. (citing Ex.
1012 ¶ 21).
Figure 2 in McIntyre shows “how an output signal is generated from a cam
sensor signal.” Ex. 1002, p. 5. The cam pick-up, or cam sensor signal, in Figure 2
illustrates the signal generated upon rotation of the camshaft. Id. at 4–5. This
signal does not reset the count of encoded clock pulses in response to another
received signal.
As shown in Figure 3 of McIntyre, “[a]utomatic input and output engine
control signals use OFFSET and DURATION registers to allow maximum pulse-
placement flexibility and reduce processor overhead.” Ex. 1002, 5. Each edge of
the signal “increments a counter” used for an index into a RAM array. Id. at
Fig. 3. McIntyre explains that “[i]f every rising edge of the cam signal is ‘time
stamped’ into a RAM location and indexed via the edge number for easy access, an
array of 100 numbers can be generated (one for each cam rising edge).” Id. at 5.
As McIntyre further explains, the “‘real time’ Capture” (id. at Fig. 3) in the RAM
array results in a “table of ‘real-time’ values” that will be “useful for generating
output signals.” Id. at 5. OFFSET and DURATION values will be added to these
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real-time values and placed in their respective control registers. Id. “Figure 3
illustrates such a task.” Id.
McIntyre also states that “[t]he array pointer will be reset when the ‘missing
tooth’ is found.” Ex. 1002, 5. Petitioner quotes this sentence (Pet. 13) without any
further discussion or explanation. The “array” to which McIntyre refers appears to
be the RAM array in Figure 3. McIntyre provides no antecedent for the “pointer”
referred to in this sentence. It is this undefined “pointer” that McIntyre states will
be reset. While McIntyre uses the word “reset” to describe what happens when the
“‘missing tooth’ is found,” the RAM array is merely storing the signal received.
Petitioner has not directed us to any disclosure in McIntyre that states that, in the
RAM array or any other element in McIntyre, the count of encoded clock pulses
resets to zero in response to the received signal being low for a period that exceeds
a predetermined timeout value, as required by claims 13 and 37.
Petitioner also relies on paragraph 21 of Dr. Mohapatra’s Declaration for
support of the assertion that McIntyre discloses a third circuit as required by the
challenged claims. Pet. 13. Paragraph 21 in Dr. Mohapatra’s Declaration is
substantively identical to the corresponding text of the Petition. Compare Ex.
1012 ¶ 21, with Pet. 12–13.
Expert testimony that does not disclose the underlying facts or data on which
the opinion is based is entitled to little or no weight. 37 C.F.R. § 42.65(a).
Dr. Mohapatra’s Declaration does not provide any facts, data, or analysis to
support the opinion stated. Merely repeating an argument from the Petition in the
declaration of a proposed expert does not give that argument enhanced probative
value. Accordingly, we give the cited evidence of Dr. Mohapatra’s Declaration no
probative weight.
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Petitioner has not directed us to persuasive evidence that Figures 2 and 3 in
McIntyre, or any other disclosure in McIntyre, disclose the identical elements and
limitations of the claimed “third circuit” in as complete detail as is contained in the
challenged claims. We are not persuaded that the Figure 2 signal or the Figure 3
elements and described functionality disclose a circuit for resetting the count of
encoded clock pulses to zero in response to a received signal, as required by claims
13 and 37.
b. Conclusion Regarding Anticipation Based on McIntyre
Based on the analysis above, the information presented in the Petition does
not establish a reasonable likelihood that McIntyre anticipates the challenged
claims.
2. Obviousness in View of McIntyre and Renner
Petitioner asserts that claims 22 and 45 would have been obvious in view of
McIntyre and Renner. Claim 22, which depends from claim 13, and claim 45,
which depends from claim 37, each require that the claimed power integrated
circuit device is an LED current source integrated circuit. Petitioner assets that
Renner discloses the claimed LED circuit. Renner does not compensate, however,
for the deficiencies in McIntyre discussed above. Thus, we are not persuaded that
claims 22 and 45 would have been obvious in view of McIntyre and Renner.
3. Anticipation by Park
Petitioner asserts that claims 13, 18, 19, 22, 37 and 45 are anticipated by
Park. Pet. 32. It is Petitioner’s view that “Park teaches every element of claim 13
and so Park anticipates claim 13.” Pet. 37–38. Petitioner makes the identical
assertion for independent claim 37. Pet. 45–46.
2

2
Petitioner repeats the same analysis and arguments for claim 37 as are made for
claim 13. We analyze claims 13 and 37 together because of their substantial
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We base our analysis of Park on an English translation (Ex. 1005) provided
by Petitioner.
3
Park discloses “an apparatus of controlling a volume of a receiving
bell of a phone.” Ex. 1005, ¶ 0001. More specifically, Park discloses an apparatus
for gradually increasing the volume of the receiving bell in proportion to a change
in ambient illumination or the number of received calls. Id.
a. A First Circuit
Independent claims 13 and 37 each require a first circuit having two
components, as discussed above. Petitioner asserts that “[i]n Park, counter 2 is a
first circuit for receiving a signal via a single input of the integrated circuit.”
Pet. 33. Petitioner asserts that counter 2 “accumulates a count of clock pulses
encoded in the received signal.” Id. In support of this assertion, Petitioner cites to
Figure 3 in Park and paragraph 0013 in Exhibit 1005, the English translation of
Park. Petitioner also cites for support Dr. Mohapatra’s Declaration. Id. at 34
(citing Ex. 1012 ¶ 55). Paragraph 55 of Dr. Mohapatra’s Declaration essentially
repeats the arguments and citations from the Petition, with no further data, facts, or
analysis. Compare Ex. 1012 ¶ 55, with Pet. 33–34. Accordingly, we give this
evidence no probative weight. 37 C.F.R. § 42.65(a).
Park describes the function of counter 2 in Figure 2 as follows: “the
counter 2 counting outputs of the AND gate AND to output a counting value and at
the same time, output the ripple carry signal per a predetermined counting value.”
Ex. 1005, ¶ 0010. Park states that Figures 3A to 3H “are waveform diagrams of
each component for describing an operation of the apparatus.” Id. at ¶ 0008.
4
Park

similarity. We will cite to the Petition and Petitioner’s arguments only for claim
13, unless separate reference to claim 37 is required.
3
We rely on the original, untranslated exhibit for the figures in Park because the
figures were not included with the translated Exhibit 1005.
4
Exhibit 1005, the English translation of Park, refers to the sub-figures in Figure 3
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also discloses that signals “in a pulse form shaped and inverted as shown in Figure
3B are output through the shaping elements R2 and C2 and the inverter I1 connected
to an emitter side of the photo-coupler PC1.” Id. at ¶ 0013. Additionally,
regarding the counter 2, Park discloses that “when the output signals in the pulse
form as shown in FIG. 3B are applied to the counter 2 through the AND gate
AND, the counter 2 counts an initial pulse P1 to output a value of 1.ø.ø.ø.” Id. As
the number of call signals is increased, the count value of the counter 2 is increased
as shown in FIGS. 3C–3F and an output analog voltage of the digital-to-analog
converter 3 also is increased, as shown in FIG. 3G. Id. at ¶ 0014. The end result is
that the volume of buzzer BZ is gradually increased. Id. Thus, it appears that
counter 2 in Park receives a signal and accumulates a count of clock pulses
encoded in the received signal.
Claims 13 and 37 also require that the output of the first circuit is
progressively increasing count values when accumulating the count of clock pulses
encoded in the received signal. Ex. 1001, col. 9, ll. 3–5; col. 11, ll. 43–45.
Petitioner asserts that “counter 2 outputs progressively increasing count
values during the accumulating of the count of clock pulses encoded in the
received signal.” Pet. 37. For support, Petitioner cites Figures 3C–3F of Park. Id.
Petitioner also cites paragraph 58 of Dr. Mohapatra’s Declaration. Id.
Dr. Mohapatra repeats, verbatim, Petitioner’s argument. Dr. Mohapatra’s
Declaration does not provide any facts, data, or analysis to support the views
stated. We give this evidence no probative weight.

as Figures 3A–3H, using uppercase letters. Exhibit 1004, the original language
version of Park, labels the sub-figures as Figures 3(a)–(h), using lowercase letters.
Because we are citing to Exhibit 1005 for the substantive analysis of Park, we will
use the format of Exhibit 1005 and refer to the sub-figures in Figure 3 as
Figures 3A–3H.
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In Park, “counter 2 counts an initial pulse P1 to output a preset value, of
1.ø.ø.ø.” Ex. 1005 ¶ 0013. “The counting value 1øøø of the initial pulse P1 is
converted into an analog value . . . by digital-to-analog converter 3.” Id.
5
In some
instances, however, “the output value of the counter 2 is changed from a state of
1111 to a state of øøøø, such that the volume is decreased from a maximum
magnitude to a minimum magnitude,” and a pulse input is not applied to counter 2.
Id. at ¶ 0015. Thus, counter 2 does not progressively increase count values when
accumulating the count of clock pulses encoded in the received signal.
Accordingly, we are not persuaded that Park discloses a first circuit as
required in independent claims 13 and 37.
b. A Second Circuit
Independent claims 13 and 37 each require a second circuit for mapping the
count of encoded clock pulses into a corresponding one of a plurality of control
states for the core circuit. Ex. 1001, col. 8, ll. 62–64; col. 11, ll. 34–36. Claims 13
and 37 also each require that the second circuit is responsive to the count values,
and operative to progressively map each of the count values output when
accumulating one of a plurality of intermediate control states. Id. at col. 4, ll. 6–9;
col. 11, ll. 46–49.
Petitioner asserts that digital-analog converter (“DAC”) 3 corresponds to the
claimed second circuit. Pet. 34. Petitioner also asserts that “as the number of call
signals is increased, the counting value of the counter 2 is increased as shown in
FIGS. 3C to 3F and an output analog voltage of the digital-to-analog converter 3 is
also increased as shown in FIG. 3G.” Id. at 35. Petitioner’s assertion is based on a

5
In some instances, Exhibit 1005 uses the designation “1.ø.ø.ø.” (with a period
between the zeros). In other instances, Exhibit 1005 uses the designation “1øøø,”
(without a period between the zeros).
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quotation from paragraph 0014 in Park. See Ex. 1005 ¶ 0014. Petitioner cites
paragraph 56 Dr. Muhapatra’s Declaration for support. Pet. 35. Dr. Mohapatra
quotes from claim 13, from Park, and also repeats Petitioner’s argument. Ex. 1012
¶ 56.
Park Discloses that DAC 3 performs the function of “converting a digital
value into an analog voltage whenever the counting value is output from the
counter 2.” Ex. 1005 ¶ 0010. We are not persuaded that “converting” a digital
value is “mapping.” Based on the description of the function of DCA 3 in Park,
we are not persuaded that DAC 3 discloses a second circuit for mapping the count
of encoded clock pulses into a corresponding one of a plurality of control states for
the core circuit, as required by claims 13 and 37.
c. A Third Circuit
Independent claim 13 requires a third circuit for resetting the count of
encoded clock pulses to zero in response to the received signal being low for a
period that exceeds a predetermined timeout value. Independent claim 37 is
similar, but requires a third circuit for resetting the count of encoded clock pulses
to zero in response to the received signal being at the first level (rather than “low,”
as in claim 13). Claim 37 also requires a transition from the second level to the
first level after the period that exceeds a predetermined timeout value.
Petitioner asserts that “[m]onostable oscillator 4 is a third circuit for
resetting the count of encoded clock pulses to zero.” Pet. 35. In support of its
position, Petitioner cites portions of Park that refer to oscillator 4 resetting
counter 2. Id. at 35–36.
Based on the limited record before us, and for purposes of this Decision, it
appears that oscillator 4 is part of a circuit for resetting counter 2. Park discloses
that “monostable oscillator 4 outputs the ‘low’ level when a predetermined time
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elapses by the resistor R3 and the condenser C3 for setting a time constant after a
final call signal to automatically reset the output value of the counter 2 counted to
be increased up to now in an initialized state for the next call.” Ex. 1005 ¶ 0018.
In addition, the switch SW1 connected to a reset terminal RESET of the
monostable oscillator 4 interworks with the hook switch SW1. Therefore, when a
person picks up the handset to start a call, the monostable oscillator 4 is reset to
reset the counter 2. Id. at 0019.
Accordingly, we are not persuaded that Park discloses a third circuit as
required in independent claims 13 and 37.
d. Conclusion Regarding Anticipation Based on Park
Based on the analysis above, the information presented in the Petition does
not establish a reasonable likelihood that Park anticipates the challenged claims.
4. Anticipation by and/or Obviousness in View of Yoshikawa
Petitioner asserts that claims 13, 15, 22, 37, 41 and 45 of the ’320 are
anticipated and/or obvious in view of Yoshikawa. Pet. 47. According to
Petitioner, “Yoshikawa teaches every element of claim 13 and so Yoshikawa
anticipates claim 13. Pet. 53.
6

Petitioner provides no argument or evidence that the challenged claims
would have been obvious in view of Yoshikawa. Accordingly, based on the
information presented in the Petition, we determine that Petitioner has not
demonstrated a reasonable likelihood that it would prevail in establishing that any
of the challenged claims would have been obvious based on Yoshikawa. We

6
Petitioner repeats the same analysis and arguments for claim 37 as are made for
claim 13. We analyze claims 13 and 37 together because of their substantial
similarity. We will cite to the Petition and Petitioner’s arguments only for
claim 13 unless separate reference to claim 37 is required.
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proceed to an analysis of the assertion that Yoshikawa anticipates the challenged
claims.
Yoshikawa discloses a timing circuit for controlling brightness or
“luminosity” of LEDs. Ex. 1008, Configuration. Yoshikawa addresses the
problem of “irregular pulses,” that is pulses “having a long pulse width after LED
light emission and a short pulse width” in a possible range of the time setting. Id.
at ¶¶ 0005, 0007.
Yoshikawa discloses counter circuit 2, “which loads the luminous intensity
preset in setting switch 1 in response to a data latch signal.” Id. at¶ 0010. Gate
circuit 3, including an AND circuit, outputs a high level signal due to a change of a
signal level from a “low” level to a “high” level when the count number
corresponding to the brightness preset in the setting switch is counted. Id. Delay
circuit 4 receives a signal input from the gate circuit, “supplied as reset signals,”
and outputs a “blank signal.” Id. LED drive circuit 5, which receives the “blank,
data latch, data clock and data signals,” allows LEDs “to emit light for a
predetermined time.” Id. Counter clock gate 6 provides a brightness control pulse
to counter circuit 2 based on output of gate circuit 3. Id. Pulse generator 15
generates the brightness control pulse. Id.
In operation, when a data latch signal is received, counter circuit 2 resets a
count value preset in the counter circuit and loads a count value corresponding to
the preset brightness level. Ex. 1008 ¶ 0011. Counter circuit 2 transmits “a reset
signal such that output from the gate circuit (3) becomes a “low” level,” which is
“input as a feedback signal” to counter clock gate 6. Id. Counter circuit 2 also
receives a brightness control pulse and counts pulses. Id. at ¶ 0013. When the
pulse count value becomes a count value corresponding to the preset
predetermined brightness, output of gate circuit 3 is changed from the “low” level
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to the “high” level, and a “high” level signal is output to delay circuit 4. Id. In
response to the “high” signal, LED drive circuit 5 “suppresses light emission from
the LED.” Id. As a result, “light emission from the LED is stopped until a
subsequent data latch signal is input.” Id. at ¶ 0015. In other words, the LED is
“turned off.” Id. at ¶ 0020.
a. A Third Circuit
As discussed above, independent claims 13 and 37 require a third circuit for
resetting the count of encoded clock pulses to zero in response to the received
signal being low for a period that exceeds a predetermined timeout value.
Concerning the “third circuit,” Petitioner asserts that Yoshikawa discloses
that “a circuit (not depicted) generates a data latch signal that resets the count of
encoded clock pulses to zero.” Pet. 51 (emphasis added) (citing Ex. 1012 ¶ 82,
Ex. 1008 ¶ 0013). We find no such disclosure in Paragraph 0013 of Yoshikawa.
This paragraph does not use the words “reset,” “zero,” or similar words or phrases
that support Petitioner’s assertion. Paragraph 0013 describes that when the pulse
count value becomes a count value corresponding to a “preset predetermined
luminous intensity,” output of gate circuit 3 is changed from the “low” level to the
“high” level, and a “high” level signal is output to delay circuit 4. Ex. 1008
¶ 0013.
Paragraph 82 of Exhibit 1012, Dr. Mohapatra’s Declaration, also cited in
support of Petitioner’s assertion concerning the claimed “third circuit,” quotes
language from claim 13, repeats Petitioner’s assertion, and then cites to paragraph
0013 of Yoshikawa but quotes from language that appears to be from paragraph
0011 of Yoshikawa. Dr. Mohapatra’s opinion in paragraph 82 of his Declaration,
however, does not support Petitioner’s assertion that clock pulses are reset to zero.
Dr. Mohapatra’s opinion, and paragraph 0011 of Yoshikawa, state that when a data
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latch signal is received, counter circuit 2 transmits a reset signal such that output
from gate circuit 3 “becomes a ‘low’ level” signal. Petitioner does not direct us to
any disclosure in Yoshikawa that states that the count of encoded clock pulses in
counter 2 is reset to zero, as required by the challenged claims.
Petitioner also asserts that the count in Yoshikawa “is reset in response to
the received signal being low for a period that exceeds a predetermined timeout
value as shown in Figure 6.” Pet. 51. Yoshikawa states that Figure 6 is a “[t]ime
chart of a luminous intensity control pulse and a blank signal according to the first
embodiment of the present invention.” Ex. 1008, 12. Yoshikawa also explains
that Figure 6 “is a time chart of each control signal, illustrating how an LED light
emission period is controlled by a value preset in the setting switch (1) after a data
latch signal is input to an LED display controller.” Id. at ¶ 0018. We are not
persuaded that Figure 6 establishes that the count of encoded clock pulses in
counter 2 is reset to zero in response to the received signal being low for a period
that exceeds a predetermined timeout value.
In support, Petitioner again cites paragraph 82 of Dr. Mohapatra’s
Declaration, which repeats Petitioner’s assertion without further facts, data, or
analysis. As discussed above, we give this evidence no probative weight.
b. Conclusion Regarding Anticipation Based on Yoshikawa
Based on Petitioner’s arguments and evidence, we are not persuaded that the
information presented in the Petition establishes a reasonable likelihood that
Yoshikawa discloses a third circuit for resetting the count of encoded clock pulses
to zero in response to the received signal being low for a period that exceeds a
predetermined timeout value, as required by the challenged claims. Accordingly,
we are not persuaded that Yoshikawa anticipates the challenged claims.
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5. Dependent Claims
Our analysis above addresses independent claims 13 and 37 and determines,
for purposes of this proceeding, that the information in the Petition does not show
sufficiently that independent claims 13 and 37 are unpatentable based on the cited
references. The remaining challenged claims depend from either claim 13 or claim
37. Petitioner does not provide persuasive arguments or evidence directed to the
dependent claims that cures the deficiencies discussed above concerning the
independent claims.
III. CONCLUSION
For the foregoing reasons, based on the information presented in the
Petition, we determine that Petitioner has not demonstrated a reasonable likelihood
that it would prevail in establishing that any of the challenged claims are
unpatentable based on any of the asserted grounds. Accordingly, we deny the
Petition and do not institute an inter partes review of claims 13–22 and 37–45 of
the ’320 patent.
IV. ORDER
For the reasons given, it is
ORDERED that the Petition is denied.

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For Petitioner:
Tarek Fahmi
Tarek.fahmi@ascendalaw.com

Amy Embert
Amy.embert@ascendalaw.com

For Patent Owner:

Brenton R. Babcock
2brb@knobbe.com

Ted M. Cannon
2tmc@knobbe.com

Michelle E. Armond
2mea@knobbe.com