Intel CorporationDownload PDFPatent Trials and Appeals BoardMar 18, 20212019005792 (P.T.A.B. Mar. 18, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/642,113 07/05/2017 Mohammad ABDALLAH 42P111993US-C1 1070 131413 7590 03/18/2021 NDWE LLP/Intel 99 Almaden Boulevard, Suite 710 San Jose, CA 95113 EXAMINER SNYDER, STEVEN G ART UNIT PAPER NUMBER 2184 NOTIFICATION DATE DELIVERY MODE 03/18/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ndwe_docketing@cardinal-ip.com patent@ndwe.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MOHAMMAD ABDALLAH Appeal 2019-005792 Application 15/642,113 Technology Center 2100 Before JEAN R. HOMERE, MICHAEL J. STRAUSS, and ADAM J. PYONIN, Administrative Patent Judges. HOMERE, Administrative Patent Judge. DECISION ON APPEAL I. STATEMENT OF THE CASE1 Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the Examiner’s rejection of claims 20–40, all of the claims pending.2 Claims App. Claims 1–19 are canceled. Id. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 We refer to the Specification filed July 5, 2017 (“Spec.”); the Final Office Action, mailed July 23, 2018 (“Final Act.”); the Appeal Brief, filed Dec. 21, 2018 (“Appeal Br.”); and the Examiner’s Answer, mailed Mar. 29, 2019 (“Ans.”). 2 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies Intel Corporation as the real party-in-interest. Appeal Br. 2. Appeal 2019-005792 Application 15/642,113 2 II. CLAIMED SUBJECT MATTER According to Appellant, the claimed subject matter relates to a method and system for outputting reliably predictable instruction sequences (100) and associated branch instructions stored in a cache/buffer. Spec. ¶¶ 6, 23, Fig. 1. Figure 1, reproduced and discussed below, is useful for understanding the claimed subject matter: Figure 2 above illustrates reliably predictable instruction sequence (100) including 4 branch instructions. Spec. ¶ 25, 27. As depicted in Figure 2 above, upon determining that a reliably predictable instruction sequence from memory exceeds a threshold frequency of fetches, a microprocessor associates therewith an identified Appeal 2019-005792 Application 15/642,113 3 branch instruction that precedes the reliably predictable instruction sequence and stores them in buffer (500), which subsequently outputs the instruction into the pipeline of the microprocessor in response to a subsequent access of the branch instruction. Id. ¶¶ 7, 36, 37, 43. Upon determining that the reliably predictable instruction sequence is associated with a branch instruction having a wrong predicted outcome, the microprocessor evicts the predictable instruction from the buffer and directs a subsequent access thereto to a second buffer storing an alternative instruction sequence for retrieval. Id. ¶¶ 38–44. Claims 20, 27, and 34 are independent. Claim 20, reproduced below with disputed limitations emphasized, is illustrative: 20. A method for outputting reliably predictable instruction sequences, comprising: tracking fetches of instruction sequences from memory; determining a reliably predictable instruction sequence from the instruction sequences that exceeds a threshold frequency of fetches; identifying a branch instruction preceding the reliably predictable instruction sequence; storing the reliably predictable instruction sequence into a buffer with an association to the branch instruction; and outputting the reliably predictable instruction sequence from the buffer into a pipeline of a processor, in response to a subsequent access of the branch instruction. Claims App. (Emphasis added). III. REFERENCES The Examiner relies upon the following references.3 3 All reference citations are to the first named inventor only. Appeal 2019-005792 Application 15/642,113 4 Name Reference Date Bondi et al. US 5,881,277 Mar. 9, 1999 Jouppi, Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Digital Equipment Corporation Western Research Lab, 364−73 (1990) Rotenberg et al., Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching, 29th Annual International Symposium on Microarchitecture (1996) Ramirez et al., Fetching Instructions Streams, Computer Architecture Department, Universitat Politecnica de Catalunya, 371−82, (2002) IV. REJECTIONS The Examiner rejects claims 20–40 as follows: Claims 20, 21, 23–25, 27, 28, 30–35, and 37–40 stand rejected as anticipated under 35 U.S.C. §102 by Rotenberg. Final Act. 3–8. Claim 26 stand rejected as unpatentable under 35 U.S.C. §103 over the combination of Rotenberg and Ramirez. Id. at 10–11. Claims 22, 29, and 36 stand rejected as unpatentable under 35 U.S.C. §103 over the combination of Rotenberg and Jouppi. Ans. 9–11.4 4 In the Final Action, the Examiner rejected these claims over the combination of Rotenberg and Bondi. Final Act. 8–9. However, in the Answer, the Examiner issues a new ground of rejection of the claims over the combination of Rotenberg and Jouppi. Ans. 9–11. Appeal 2019-005792 Application 15/642,113 5 V. ANALYSIS We consider Appellant’s arguments seriatim, as they are presented in pages 4–13.5 We are unpersuaded by Appellant’s contentions. Except as otherwise indicated herein below, we adopt as our own the findings and reasons set forth in the Final Action, and the Examiner’s Answer in response to Appellant’s Appeal Brief. Final Act. 3–14; Ans. 3–17. However, we highlight and address specific arguments and findings for emphasis as follows. 1. Anticipation Rejection First, Appellant argues that the Examiner errs in finding that Rotenberg’s disclosure of storing recently used traces in a buffer describes “determining a reliably predictable instruction sequence” as recited in claim 20. Appeal Br. at 5–6 (citing Rotenberg ¶ 2.3.6). Likewise, Appellant argues that Rotenberg’s disclosure of temporal locality does not describe the cited limitation. Id. at 6. Second, Appellant argues that the Examiner errs in finding that Rotenberg’s disclosure of buffering traces describes storing a trace in association with a branch instruction, as recited in the claim. Id. at 6–7. Further, Appellant argues that because Rotenberg’s disclosure of basic blocks of instructions that have been taken together does not feature branch instruction, it does not describe the branch instructions stored along with the reliably predictable instruction sequence. Id. (citing Rotenberg Fig. 2). 5 We have considered in this Decision only those arguments Appellant actually raised in the Briefs. Any other arguments Appellant could have made but chose not to make in the Briefs are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(iv) (2017). Appeal 2019-005792 Application 15/642,113 6 Appellant’s arguments are not persuasive of reversible Examiner error. Rotenberg discloses a trace cache for storing dynamic instruction sequences wherein each line stores a snapshot or trace of the dynamic instruction stream. Rotenberg ¶ 1.1. According to Rotenberg, the stored sequence includes m basic blocs with n instructions. Id. Further, Rotenberg discloses that the trace cache relies on dynamic sequences of code being reused because of their (1) temporal locality (i.e., “the trace cache can count on instructions which been recently used being used again in the near future”); and (2) branch behavior (i.e., “most branches tend to be biased towards one direction, which is why branch prediction accuracy is usually high”). Id. As a preliminary matter, we note Appellant’s Specification does not expressly define “reliably predictable instruction sequence” or “branch instruction”. Accordingly, we broadly but reasonably construe the cited phrases according to their ordinary meaning in light of the Specification. Thus, we construe “reliably predictable instruction sequence” to mean an instruction sequence that is predicted with a high degree of certainty and can be counted on/relied upon for reuse. Further, we construe “branch instruction” as an instruction indicating a particular path having a block of code to be executed.6 6 “A branch is an instruction in a computer program that may, when executed by a computer, cause the computer to begin execution of a different instruction sequence. Branch (or branching, branched) may also refer to the act of beginning execution of a different instruction sequence due to executing a branch instruction. A branch instruction can be either an unconditional branch, which always results in branching, or a conditional branch, which may or may not cause branching depending on some condition. / an instruction is used to modify the instruction execution Appeal 2019-005792 Application 15/642,113 7 The Examiner finds, and Appellant does not dispute, that Rotenberg’s disclosure of the temporal locality coupled with the branch behavior characteristics of the dynamic sequence of code stored in the cache describes the “reliably predictable instruction sequence”. Ans. 13. Appellant unpersuasively argues that Rotenberg does not discuss the “temporal locality” characteristic of the dynamic sequence. Appeal Br. 6. However, as noted above, Rotenberg indicates that the “temporal locality” characteristic of the instruction sequence indicates that the cache can count on or rely upon such instruction to reuse them in the near future. Further, Appellant does not address the branch behavior characteristic of the instructions, which (as discussed above) Rotenberg indicates confers a high degree of predictability and accuracy to the instruction. Because these findings are unchallenged, we are not persuaded of error in the Examiner’s finding that Rotenberg’s disclosure describes the “reliably predictable instruction sequence”. Further, the Examiner finds that Rotenberg’s disclosure of m blocks of n instructions, each block separated by a branch, describes the “reliably predictable instruction sequence” stored in association with a branch instruction. Ans. 14 (citing Rotenberg, Fig. 2). Appellant unpersuasively argues that Figure 2 of Rotenberg merely discloses blocks of instructions, and fails to account for the branches that link the instruction blocks to the buffer. Because these Examiner’s findings are unchallenged, we are not persuaded of error in the Examiner’s finding that Rotenberg’s disclosure describes the “reliably predictable instruction sequence” stored in sequence of the CPU.” http://www.engineeringslab.com/all_engineerings_dictionary_terms/branch- instruction.htm Appeal 2019-005792 Application 15/642,113 8 association with a branch instruction. Accordingly, we sustain the Examiner’s anticipation of rejection of claim 20. Regarding the rejection of claims 21, 23–25, 27, 28, 30–35, and 37–40, Appellant does not present separate patentability arguments or reiterates substantially the same arguments as those previously discussed for the patentability of claim 20 above. Appeal Br. 8–9. As such, claims 21, 23–25, 27, 28, 30–35, and 37–40 fall therewith. See 37 C.F.R. § 41.37(c)(1)(iv). 2. Obviousness Rejections Regarding the rejection of claims 22, 29, and 36, Appellant argues that the combination of Rotenberg and Bondi does not teach or suggest storing in a second buffer an alternative instruction sequence for retrieval therefrom upon a subsequent access to the branch instruction where a predicted outcome of the branch instruction is wrong. Appeal Br. 9–10. In particular, Appellant argues that Bondi’s disclosure of a machine word cache for storing and outputting machine words upon being notified of a preceding misprediction does not cure the noted deficiencies of Rotenberg. Id. at 10– 11(citing Bondi 6:31–53). Appellant’s arguments are moot in light of the Examiner’s new ground of rejection.7 Because Appellant does not avail itself of the opportunity to respond to the new ground of rejection, we summarily sustain the Examiner’s rejection of claims 22, 29 and 36 as being unpatentable over the combination of Rotenberg and Joppi. Regarding the rejection of claim 26, Appellant does not present separate patentability arguments as those previously discussed for the patentability of 7 See supra note 4. Appeal 2019-005792 Application 15/642,113 9 claim 20 above. Appeal Br. 12. As such, claim 26 falls therewith. See 37 C.F.R. § 41.37(c)(1)(iv). VI. CONCLUSION For the above reasons, we affirm the Examiner’s rejections of claims 20–40. VII. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 20, 21, 23–25, 27, 28, 30–35, 37–40 102 Rotenberg 20, 21, 23– 25, 27, 28, 30–35, 37–40 22, 29, 36 103 Rotenberg, Jouppi 22, 29, 36 26 Rotenberg, Ramirez 26 Overall Outcome 20–40 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Copy with citationCopy as parenthetical citation