Intel Corporation

Patent Trials and Appeals Board

Jun 9, 2021

2020000708 (P.T.A.B. Jun. 9, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/666,211 03/23/2015 EHUD SHOOR P80134/1020P80134 1091
57035 7590 06/09/2021
KACVINSKY DAISAK BLUNI PLLC
2601 Weston Parkway
Suite 103
Cary, NC 27513
EXAMINER
RIZK, SAMIR WADIE
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
06/09/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
INTEL@kdbfirm.com
docketing@kdbfirm.com
kpotts@kdbfirm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte EHUD SHOOR, ERAN GALIL, and EFRAIM KUGMAN
Appeal 2020-000708
Application 14/666,211
Technology Center 2100
Before ERIC S. FRAHM, BETH Z. SHAW, and JOYCE CRAIG,
Administrative Patent Judges.
SHAW, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–25. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Intel Corporation.
Appeal Br. 2.
Appeal 2020-000708
Application 14/666,211

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CLAIMED SUBJECT MATTER
The claims are directed to framing with error-correction parity bit
support for high-speed serial interconnects. Spec. ¶ 2.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. An apparatus, comprising:
a processor circuit; and
an interconnect manager component for execution by the
processor circuit, the interconnect manager component comprising:
a frame packing component to generate a block, the block
comprising a plurality of frames, each of the plurality of frames
comprising a header information element, an error-correction
information element, and a data information element; and
an interconnect component to communicate the block via a
serial interconnect.
REFERENCE
The prior art relied upon by the Examiner is:
Name Reference Date
Shulman US 2013/0272357 A1 Oct. 17, 2013
REJECTION
Claims 1–25 stand rejected under 35 U.S.C. § 102 as anticipated by
Shulman.
OPINION
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments that the Examiner has erred. We disagree with Appellant’s
contentions that the Examiner erred in finding that Shulman discloses the
disputed limitations recited in claim 1. We agree with and adopt the
Appeal 2020-000708
Application 14/666,211

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Examiner’s findings and conclusions in the Final Rejection and Answer. See
Final Act. 2–9; Ans. 2–7.
Appellant argues interface 114 of Shulman is not an interface manager
component. Appeal Br. 11. Appellant also argues Shulman does not describe
the processor 116 executing interface 114. Id. Additionally, Appellant
argues, Shulman does not disclose generating a block comprising a number
of frames with each frame comprising header, error-correction, and data
information elements. Id. at 12.
The Examiner finds, and we agree, that Shulman teaches a processor
116 with an interconnect manager (i.e., elements 148 and 152) component
for execution by the processor 116 to generate a block comprising a plurality
of frames. See Ans. 3, 4 (citing Shulman, Fig. 3). The Examiner finds, and
we agree, that Shulman discloses each of the plurality of frames comprising
a header information element, an error-correction information element, and a
data information and an interconnect component to communicate the block
via a serial interconnect. Id. (citing Shulman, Fig. 3, Fig. 1 HS IF (154)).
Appellant does not respond to these findings in the Answer, and
consequently, we are not persuaded of error in them.
Accordingly, we sustain the rejection of claim 1. We also sustain the
Examiner’s obviousness rejections of dependent claims 2–25. Despite
nominally arguing these claims separately, Appellant reiterates similar
arguments made in connection with claim 1. Appeal Br. 13. We are not
persuaded by these arguments for the reasons previously discussed.

CONCLUSION
We affirm the rejection of claims 1–25.
Appeal 2020-000708
Application 14/666,211

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DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–25 102 Shulman 1–25
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED