Intel Corporation

Patent Trials and Appeals Board

May 26, 2021

2020003676 (P.T.A.B. May. 26, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/791,292 10/23/2017 Pramod MALATKAR P34724C2-
C1/111079-225925
9129
31817 7590 05/26/2021
SCHWABE, WILLIAMSON & WYATT, P.C.
1211 SW 5th Avenue, Suite 1600
Portland, OR 97204
EXAMINER
YEUNG LOPEZ, FEIFEI
ART UNIT PAPER NUMBER
2899
NOTIFICATION DATE DELIVERY MODE
05/26/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
IPDocketing@SCHWABE.com
intelparalegal@schwabe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PRAMOD MALATKAR
Appeal 2020-003676
Application 15/791,292
Technology Center 2800
Before CATHERINE Q. TIMM, KAREN M. HASTINGS, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–4 and 10. See Final Act. 1. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party in interest as Intel Corporation. Appeal Br. 3.
Appeal 2020-003676
Application 15/791,292

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CLAIMED SUBJECT MATTER
The claims are directed to a microelectronic package including a
plurality of stacked microelectronic dies on a substrate. See, e.g., claims 1
and 10. The die stack includes a bottommost microelectronic die and a next
bottommost microelectronic die. Id. The package includes an encapsulation
material over the substrate and laterally adjacent the two dies, but the
encapsulation material is not present on the backside of the next bottommost
die. Id. Claim 1, reproduced below with the limitation most at issue
italicized, is illustrative of the claimed subject matter:
1. A microelectronic package, comprising:
a substrate;
a plurality of stacked microelectronic dies above the
substrate, the plurality of stacked microelectronic dies having a
bottommost microelectronic die proximate the substrate, and a
next bottommost microelectronic die above the bottommost
microelectronic die, wherein the bottommost microelectronic
die has a plurality of front side lands on an active portion facing
the substrate and a plurality of backside lands facing the next
bottommost microelectronic die with a plurality of through
silicon vias (TSVs) electrically coupling the backside lands and
the front side lands of the bottommost microelectronic die,
wherein the next bottommost microelectronic die has a plurality
of front side lands facing the bottommost microelectronic die,
the front side lands of the next bottommost microelectronic die
opposite a back side of the next bottommost microelectronic
die, wherein the plurality of backside lands of the bottommost
microelectronic die is directly coupled to the plurality of front
side lands of the next bottommost microelectronic die by a
solder layer, and wherein the plurality of front side lands of the
bottommost microelectronic die electrically couples the
bottommost microelectronic die to the substrate, wherein the
TSV s of the bottommost microelectronic die are in direct
contact with the backside lands of the bottommost
Appeal 2020-003676
Application 15/791,292

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microelectronic die but are not in direct contact with the front
side lands of the bottommost microelectronic die;
an underfill material layer between the bottommost
microelectronic die and the next bottommost microelectronic
die; and
an encapsulation material, the encapsulation material a
single continuous layer over the substrate and laterally adjacent
to the bottommost microelectronic die, the next bottommost
microelectronic die and the underfill material layer, wherein a
bottommost surface of the encapsulation material is below a
bottommost surface of the bottommost microelectronic die,
wherein the encapsulation material is not on the back side of
the next bottommost microelectronic die, and wherein the
encapsulation material is separate and distinct from the underfill
material layer.
Appeal Br. 14–15 (Claims Appendix) (emphasis added).
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Yoo US 7,843,052 B1 Nov. 30, 2010
Maeda US 2003/0178716 A1 Sept. 25, 2003
Tsukagoshi US 2005/0236638 A1 Oct. 27, 2005
Subraya US 2007/0210433 A1 Sept. 13, 2007
Hatano US 2007/0287265 A1 Dec. 13, 2007
Tsao US 2008/0169557 A1 July 17, 2008
Shen US 2010/0327465 A1 Dec. 30, 2010
REJECTIONS
Claims 1 and 10 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hatano, Subraya, Maeda, Tsao, and Yoo. Final Act. 2.
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Application 15/791,292

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Claims 2 and 3 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hatano, Subraya, Maeda, Tsao, Yoo, and Shen. Final Act.
6.
Claim 4 is rejected under 35 U.S.C. § 103(a) as being unpatentable
over Hatano, Subraya, Maeda, Tsao, Yoo, and Tsukagoshi. Final Act. 7.
OPINION
Appellant’s arguments focus on the Examiner’s rejection of claim 1.
Appeal Br. 7–12. Thus, we confine our review to that rejection. The issue is:
Has Appellant identified a reversible error in the Examiner’s finding of a
suggestion within the teachings of Tsao and Yoo for encapsulating Hatano’s
device to protect the stacked dies as taught by Tsao, but without including
the encapsulant on the backside of the next bottommost microelectronic die
to improve heat removal as taught by Yoo?
Appellant has not identified such an error.
Appellant, in fact, does not address the Examiner’s rejection.
Appellant states that “[i]t is the Examiner’s position that it would have been
obvious to not include the encapsulant 100 of Tsao on second semiconductor
chip 85 of Tsao, based on the teachings of Yoo, for the benefit of heat
removal.” Appeal Br. 10, citing Final Act. 5. But the Examiner’s conclusion
of obviousness is based on findings of suggestions within Tsao and Yoo for
encapsulating Hatano’s device, not Tsao’s device. Final Act. 4–5; see also
Ans. 3 (“Yoo was used to modify Hatano’s device, not Tsao’s.”).
Because Appellant’s arguments do not address the Examiner’s
rejection of claim 1, Appellant has not identified a reversible error in it. We
further fully adopt the Examiner’s response to Appellant’s arguments as set
forth in the Answer. Ans. 2–3.
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Application 15/791,292

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CONCLUSION
The Examiner’s decision to reject claims 1–4 and 10 is affirmed.
DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 10 103(a) Hatano, Subraya,
Maeda, Tsao, Yoo
1, 10
2, 3 103(a) Hatano, Subraya,
Maeda, Tsao, Yoo,
Shen
2, 3
4 103(a) Hatano, Subraya,
Maeda, Tsao, Yoo,
Tsukagoshi
4
Overall
Outcome
1–4, 10
RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED