Intel CorporationDownload PDFPatent Trials and Appeals BoardMay 13, 202014341481 - (D) (P.T.A.B. May. 13, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/341,481 07/25/2014 Douglas L. Li P64262/1020P64262 8850 57035 7590 05/13/2020 KACVINSKY DAISAK BLUNI PLLC 2601 Weston Parkway Suite 103 Cary, NC 27513 EXAMINER NASRI, MARYAM A ART UNIT PAPER NUMBER 2483 NOTIFICATION DATE DELIVERY MODE 05/13/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@kdbfirm.com intel@kdbfirm.com kpotts@kdbfirm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte DOUGLAS L. LI ____________ Appeal 2019-002724 Application 14/341,481 Technology Center 2400 ____________ Before ERIC S. FRAHM, JOYCE CRAIG, and MATTHEW J. McNEILL, Administrative Patent Judges. FRAHM, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1–25, which are all the claims pending and rejected in the application. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. “The word ‘applicant’ when used in this title refers to the inventor or all of the joint inventors, or to the person applying for a patent as provided in §§ 1.43, 1.45, or 1.46.” 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Intel Corporation (Appeal Br. 2). Appeal 2019-002724 Application 14/341,481 2 STATEMENT OF THE CASE Introduction Because “full-motion video displays based upon digital video signals are becoming more widely available” (Spec. ¶ 2), and “the amount of raw digital information in video is massive, takes up a large amount of storage, and uses a significant amount of bandwidth when being transmitted” (Spec. ¶ 3), “video encoders are used to take the video data and to encode it in a format which takes up less space. As a result, the bandwidth consumed between devices that transmit and receive the video information may be used more efficiently or more data can be transmitted between those devices in the same time” (Spec. ¶ 4). Appellant’s invention, entitled “Techniques for Performing a Forward Transformation by a Video Encoder Using a Forward Transform Matrix” (Title), “generally relate[s] to techniques for processing a raw video stream. More specifically, techniques may include applying a forward transformation for encoding one or more video frames of the raw video stream” (Spec. ¶ 1). Appellant discloses: The forward transform matrices for particular transform unit sizes and types may be generated by converting each stage of a linear transformation algorithm into intermediate matrices and summing the intermediate matrices to create a final forward transform matrix. As will be discussed in more detail below, various improvements may be realized by deferring rounding that normally occurs after each intermediate stage until the final stage or when the final forward transform matrix is generated. These forward transform matrices with deferred rounding may produce better results than when the actual linear transformation algorithms or processes are used. (Spec. ¶ 22 (emphases added); see also claims 1, 12, 19 (last clause of each claim)). Independent claim 1 is exemplary, and is reproduced below with Appeal 2019-002724 Application 14/341,481 3 emphases, formatting, and bracketed lettering added to disputed portions of the claim: 1. An apparatus, comprising: processing circuitry; a memory coupled with the processing circuitry, the memory to store at least one master forward transform matrix comprising signed constants having a defined number of precision bits and a sign bit, and the processing circuitry to perform the transformation on residuals of pixel values of a frame using one of the at least one master forward transform matrix or a forward transform matrix derived from one of the at least master forward transform matrix, and determine which forward transform matrix to use to perform the transformation based on at least a transform unit size, [A] the processing circuitry to defer a rounding operation until a final forward transform matrix is generated. Appeal Br. 10, Claims Appendix (emphases, formatting, bracketed lettering added). Remaining independent claims 12 and 19 recite limitations commensurate in scope with limitation A, regarding deferring a rounding operation until a final forward transform matrix is generated. The Specification (see Spec. ¶ 36) also supports performing the rounding operation after each intermediate matrix operation (vertical or horizontal matrix). Examiner’s Rejections (1) Claims 1, 3–7, 10, 12, 14–16, 19, and 21–23 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Sadafale et al. (US 2012/0082212 A1; published April 5, 2012) (hereinafter, “Sadafale”) and Yoneoka et al. (US 2009/0172506 A1; published July 2, 2009). Final Act. 4–11; Ans. 3–10. Appeal 2019-002724 Application 14/341,481 4 (2) Claims 2, 8, 9, 11, 13, 17, 18, 20, 24, and 25 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Sadafale, Yoneoka, and Han et al. (US 9,544,596 B1; issued Jan. 10, 2017) (hereinafter, “Han”). Final Act. 11–15; Ans. 11–14. Appellant’s Contentions With regard to the obviousness rejections of claims 1–25, Appellant primarily argues the merits of independent claim 1 (see Appeal Br. 5–7), and makes similar arguments as to the patentability of remaining independent claims 12 and 19, as well as dependent claims 2–11, 13–18, and 20–25 (see Appeal Br. 5, 9). As to independent claim 1, Appellant contends (Appeal Br. 5–7) that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a), because the base combination of Sadafale and Yoneoka, and specifically Yoneoka, fails to teach or suggest limitation A, as recited in claim 1. Principal Issue on Appeal Based on Appellant’s arguments in the Appeal Brief (Appeal Br. 5–9), the following issue is presented on appeal: Did the Examiner err in rejecting claims 1–25 as being unpatentable over the base combination of Sadafale and Yoneoka, because Yoneoka fails to teach or suggest limitation A, as recited in claim 1, and commensurately recited in claims 12 and 19? ANALYSIS We have reviewed the Examiner’s rejections (Final Act. 4–15; Ans. 3–14) in light of Appellant’s contentions (Appeal Br. 5–9), and evidence of record, in light of the Examiner’s response to Appellant’s arguments in the Appeal 2019-002724 Application 14/341,481 5 Appeal Brief (Ans. 15–17). With regard to claims 1, 12, and 19, we concur with Appellant’s contentions (see Appeal Br. 5–7) that the Examiner erred in finding the cited portions of Yoneoka teach or suggest deferring rounding operations “until a final forward transform matrix is generated,” as recited in limitation A (see e.g., claim 1, limitation A). The USPTO “must examine the relevant data and articulate a satisfactory explanation for its action including a rational connection between the facts found and the choice made.” Motor Vehicle Mfrs. Ass’n v. State Farm Mut. Auto. Ins. Co., 463 U.S. 29, 43 (1983) (internal quotation marks and citation omitted); see Synopsys, Inc. v. Mentor Graphics Corp., 814 F.3d 1309, 1322 (Fed. Cir. 2016) (stating that, as an administrative agency, the PTAB “must articulate logical and rational reasons for [its] decisions” (internal quotation marks and citation omitted)). Here, the Examiner has stated that the basis for finding that Yoneoka teaches deferring a rounding operation until a final forward transform matrix is generated is that: given the broadest reasonable interpretation, the horizontal transform matrix generated by [Yoneoka’s] butterfly/post- processing unit 14 is considered to be a final transform matrix, and the round-off process is perform[ed] (as a post-process operation for the horizontal component of the transform matrix) after completing the calculation of [the] horizontal matrix operation. Hence, the limitation of ‘the processing circuitry to defer a rounding operation until a final forward transform matrix is generated’ has been disclosed by the combination of Sadafale and Yoneoka. Ans. 16. The Examiner also speculates in the Answer that “if we consider the horizontal transform matrix generated by the butterfly/post-processing Appeal 2019-002724 Application 14/341,481 6 unit 14 as the final transform matrix, the round-off operation would be performed after the final transform matrix is generated” (Ans. 17). Under the broadest reasonable interpretation standard, and absent any special definition, claim terms are given their ordinary and customary meaning, as would be understood by a person of ordinary skill in the art in the context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special definition for a claim term must be set forth with reasonable clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). “Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification and prosecution history.” Trivascular, Inc. v. Samuels, 812 F.3d 1056, 1062 (Fed. Cir. 2016). Here, we conclude the Examiner’s interpretation of the “final forward transform matrix” (claims 1, 12, 19) as being the horizontal transform matrix operation, which is described by Sadafale (see ¶ 73), Yoneoka (see ¶¶ 27, 35, 64, 100), and Appellant (see Spec. ¶ 22, 36) as being an intermediate stage operation, and not a final transform matrix operation, is unreasonable. Specifically, Sadafale describes performing rounding after each butterfly (i.e., intermediate, horizontal or vertical matrix operation) stage as follows: Some fast DCT algorithms implement DCT using a butterfly decomposition approach in multiple stages. For example, the DCT and IDCT implementations in TMuC-0. 7 .3 use several stages of butterfly decomposition. The multiple stages introduce serial dependency and cascaded multipliers. Also, after each butterfly stage involving multiplication, a rounding/truncation operation is carried out to prevent bit- width increase of data resulting from the cascaded multiplication. These factors lead to increased delay in a Appeal 2019-002724 Application 14/341,481 7 hardware implementation and limit the maximum frequency at which a DCT or IDCT can be executed. Sadafale ¶ 73 (emphasis added). Similarly, Yoneoka performs the rounding operation of Equation 10 after each horizontal and vertical (i.e., intermediate) matrix operation in paragraphs 64 and 100: The process disclosed above (Or Operations 1 to 3) is carried out twice, that is, as a horizontal inverse transform process and a vertical inverse transform process, before and after an operation performed by the trans-position RAM 16. A portion of multiplication (such as, Axf [OJ) in Equation (8) in the calculation of Operation 1 is carried out by the multiplication circuit units 12 and 18. A portion of addition or subtraction (such as, Axf10]+Exf14]+Cxf12]+Gx f16]) in Equation (8) in the calculation of Operation 1 is carried out by the cumulative addition units 13 and 19. Calculations of Operation 2 are carried out in the butterfly/post-processing units 14 and 20. A calculation process mode goes to a round-off process mode in the end of a horizontal matrix operation in the butterfly/post-processing unit 14 again, and a round-off process represented by Equation (10) shown below is performed on a result of the calculations in Operation 2. P[O]-(P[Oj+x)»y P[l]-(P[lj+x)»y P[2]-(P[2j+x)»y P[3]-(P[3j+x)»y P[4]-(P[4j+x)»y P[5]-(P[5j+x)»y P[6]-(P[6j+x)»y Appeal 2019-002724 Application 14/341,481 8 P[1]-(P[1]+x)»y (10) Yoneoka ¶ 64, including Equation 10 (emphases added); see also ¶ 27; Fig. 1 (butterfly/post-processing units 14 and 20). And, paragraph 100 describes specifically that “[a]fter completion of the butterfly calculations, the round- off process represented by Equation (10) is performed, as the post-process, by the butterfly/post-processing units 14 and 20 in FIG. 1” (Yoneoka ¶ 100). Finally, Appellant’s disclose deferring rounding that normally occurs after each intermediate stage until the final stage or when the final forward transform matrix is generated (see Spec. ¶ 22). One of ordinary skill in the art, upon reading Sadafale, Yoneoka, and Appellant’s Specification, would understand the horizontal and vertical transform matrix operations to be intermediate stages, and not a final forward transform matrix operation as claimed. Because the Examiner erred in interpreting the recited “final forward transform matrix” (see claims 1, 12, 19) as encompassing Yoneoka’s horizontal matrix operation, there is not sufficient evidence or reasoning to support the rejection. Therefore, we are constrained by the record to reverse the Examiner’s rejection of claims 1, 12, and 19, as well as claims 2–11, 13– 18, and 20–25 depending respectively therefrom. CONCLUSION Based on the record before us, we are constrained to reverse the Examiner’s decision rejecting claims 1–25 under 35 U.S.C. § 103(a) as being unpatentable over the base combination of Sadafale and Yoneoka. Appeal 2019-002724 Application 14/341,481 9 DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 3–7, 10, 12, 14–16, 19, 21–23 103(a) Sadafale, Yoneoka 1, 3–7, 10, 12, 14–16, 19, 21–23 2, 8, 9, 11, 13, 17, 18, 20, 24, 25 103(a) Sadafale, Yoneoka, Hall 2, 8, 9, 11, 13, 17, 18, 20, 24, 25 Overall Outcome 1–25 REVERSED Copy with citationCopy as parenthetical citation