Hamilton Sundstrand Corporation

Patent Trials and Appeals Board

Jun 23, 2021

2020000424 (P.T.A.B. Jun. 23, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/381,349 12/16/2016 Brian Fruechtenicht 95432US01 (U380839US) 1017
114172 7590 06/23/2021
Cantor Colburn LLP - Power Controls,
Sensing Systems
20 Church Street
22nd Floor
Hartford, CT 06103-3207
EXAMINER
GRULLON, FRANCISCO A
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
06/23/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
usptopatentmail@cantorcolburn.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte BRIAN FRUECHTENICHT, TERRENCE R. LEIBHAM,
ALEX PEREIRA, JEFFERY S. SCHMIDT,
and BALAJI KRISHNAKUMAR
________________

Appeal 2020-000424
Application 15/381,349
Technology Center 2100
____________

Before MAHSHID D. SAADAT, ERIC S. FRAHM, and
MATTHEW J. McNEILL, Administrative Patent Judges.

McNEILL, Administrative Patent Judge.

DECISION ON APPEAL

Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1‒14, which are all the claims pending in this application.
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as
HAMILTON SUNDSTRAND CORPORATION. Appeal Br. 1.
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STATEMENT OF THE CASE
Introduction
Appellant’s application relates to performing a deterministic timing
analysis of a plurality of software tasks by flushing cache memory to ensure
worst case execution time. Spec. ¶¶ 3‒5. Claim 1 is illustrative of the
appealed subject matter and reads as follows:
1. A system to perform deterministic timing analysis of a
plurality of software tasks, the system comprising:
cache memory that is shared by the plurality of software
tasks;
real memory accessible by the plurality of software tasks;
a task scheduler configured to establish a cache flush
between executions of consecutive tasks among the plurality of
software tasks, wherein the cache flush includes movement of
data in the cache memory to the real memory to prevent use of
the cache memory by any of the plurality of software tasks; and
a processor configured to execute the plurality of
software tasks to obtain a worst case execution time (WCET)
associated with each of the plurality of software tasks.

The Examiner’s Rejections
Claims 1, 7, and 11 stand rejected under 35 U.S.C. § 112(a) as failing
to comply with the written description requirement. Final Act. 4‒5.
Claims 1‒14 stand rejected under 35 U.S.C. § 103 as unpatentable
over Jensen (US 6,587,937 B1; July 1, 2003), Wilson (US 6,745,294 B1;
June 1, 2004), and Jegu (US 2012/0084525 A1; Apr. 5, 2012). Final Act. 5‒
10.
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ANALYSIS
We have reviewed the Examiner’s written description and
obviousness rejections in light of Appellant’s contentions that the Examiner
has erred. We disagree with Appellant’s contentions. Except as noted below,
we adopt as our own: (1) the findings and reasons set forth by the Examiner
in the action from which this appeal is taken and (2) the reasons set forth by
the Examiner in the Examiner’s Answer in response to Appellant’s Appeal
Brief.2 We concur with the conclusions reached by the Examiner. We
highlight the following additional points.
Written Description
The Examiner finds claim 1 fails to satisfy the written description
requirement because the Specification does not reasonably convey to an
ordinarily skilled artisan that the inventors were in possession of the
limitation “wherein the cache flush includes movement of data in the cache
memory to the real memory to prevent use of the cache memory by any of
the plurality of software tasks.” See Final Act. 4‒5. In particular, the
Examiner finds the Specification discloses a cache flush occurring between
executions of consecutive tasks, which would prevent the retention of data in
cache memory. Ans. 4‒5 (citing Spec. ¶¶ 11, 15). The Examiner finds this
removal of cache data would prevent a task from using cache data that was
associated with a preceding task. Id. at 5. The Examiner finds, however, that

2 See Icon Health and Fitness, Inc. v. Strava, Inc., 849 F.3d 1034, 1042 (Fed.
Cir. 2017) (“As an initial matter, the PTAB was authorized to incorporate
the Examiner’s findings.”); see also In re Brana, 51 F.3d 1560, 1564 n.13
(Fed. Cir. 1995) (upholding the PTAB’s findings, although it “did not
expressly make any independent factual determinations or legal
conclusions,” because it had expressly adopted the examiner’s findings).
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the Specification does not disclose preventing a subsequent task from using
the cache memory because merely removing data from the cache memory
does not prevent its use. Id. at 5.
Appellant argues the Examiner errs because even under the
Examiner’s interpretation of “use of the cache memory,” “a software task
will not access or use the cache memory when the cache memory has no
data, as is the case after the claimed cache flush.” Reply Br. 2. Appellant
argues the Specification discloses flushing the cache to prevent retention of
data and this, therefore, discloses preventing use of the cache memory, as
claimed. Id.
Appellant has not persuaded us of Examiner error. The Specification
discloses removing data from cache memory after execution of a preceding
task. Spec. ¶ 17. The Specification discloses flushing cache memory before
execution of a subsequent task prevents the subsequent task from using data
saved in the cache memory by the preceding task, which ensures worst case
execution time is not measured inconsistently. Id. However, we agree with
the Examiner that the Specification does not disclose that performing a
cache flush prevents use of the cache memory. See Ans. 5. That is,
performing a cache flush does not prevent a subsequent task from, for
example, saving data in the cache memory. Saving data in the cache memory
is one way to “use a cache memory.” See, e.g., Spec. ¶ 11 (“microprocessors
include cache memory for temporary storage of data and instructions.”).
Appellant has not identified any persuasive evidence in the record that
the limitation “use a cache memory” should be interpreted so narrowly as to
exclude any “use” other than reading data from a cache memory that was
stored by a preceding task. To the extent the Specification’s disclosure that
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performing a cache flush prevents the subsequent task from using data saved
in cache memory suggests that the subsequent task will not use the cache
memory, we note that a suggestion is insufficient to demonstrate possession
of this broader claim scope. See ICU Medical, Inc. v. Alaris Medical
Systems, Inc., 558 F.3d 1368, 1377 (Fed. Cir. 2009).
For these reasons, we sustain the written description rejection of
claim 1. We also sustain the written description rejection of independent
claims 7 and 11, for which Appellant relies on the same arguments. See
Appeal Br. 6‒8.
Obviousness
Appellant argues the Examiner errs in rejecting claim 1 as obvious
because the combination of Jensen, Wilson, and Jegu does not teach or
suggest “wherein the cache flush includes movement of data in the cache
memory to the real memory to prevent use of the cache memory by any of
the plurality of software tasks.” See Appeal Br. 9‒12; Reply Br. 2‒4.
In particular, Appellant argues Jensen teaches a cache flush degrades
performance and speed because the cache memory must be refilled from the
relatively slow main memory. Appeal Br. 9‒10 (citing Jensen 4:40‒47).
Appellant argues Jensen teaches away from implementing a cache flush
between virtual machine contexts to avoid this performance degradation. Id.
at 9‒10.
Appellant argues Wilson teaches performing a cache flush after data is
moved from the cache memory to a computer system that needs the data
and, therefore, Wilson’s cache flush is a clean-up action, not performed “to
prevent use of the cache memory by any of the plurality of software tasks.”
Id. at 10‒11.
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Appellant argues Jegu teaches each cache flush is immediately
followed by storing data into cache memory before execution of a task. Id. at
11‒12 (citing Jegu ¶¶ 64‒68). Appellant argues Jegu, therefore, does not
teach or suggest preventing use of the cache memory and Jegu’s cache flush
is not performed in furtherance of obtaining WCET. Id. at 12.
Appellant has not persuaded us of Examiner error. Appellant’s
argument that Jensen teaches away from using a cache flush because a cache
flush degrades performance and speed is unpersuasive. Jensen teaches a
cache flush degrades performance, which is a disadvantage of a cache flush,
but Jensen also teaches a cache flush maintains isolation between virtual
machines, which is of particular interest to security applications. Jensen
4:38‒43. Thus, Jensen identifies an important advantage to a cache flush. A
teaching away requires a reference to actually criticize, discredit, or
otherwise discourage the claimed solution. See In re Fulton, 391 F.3d 1195,
1201 (Fed. Cir. 2004). Instead of teaching away, Jensen identifies a trade-off
based on different aspects of a cache flush, and “[a] finding that two
inventions were designed to resolve different problems . . . is insufficient to
demonstrate that one invention teaches away from another.” Nat’l Steel Car,
Ltd. v. Canadian Pac. Ry., Ltd., 357 F.3d 1319, 1339 (Fed. Cir. 2004).
The Examiner finds, and we agree, Jensen teaches a cache flush to
ensure that data previously in cache memory is no longer there to be
accessed. Ans. 6 (citing Jensen 4:37‒49). Thus, Jensen teaches a system
containing a cache memory (the claimed structure) that performs the claimed
function of performing “a cache flush between executions of consecutive
tasks among the plurality of software tasks, wherein the cache flush includes
movement of data in the cache memory to the real memory.” Jensen teaches
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that after a cache flush, the “cache must be refilled from the relatively slow
main memory,” which indicates that the subsequent task will not be reading
retained data from the cache memory. See Jensen 4:46‒47. Accordingly,
Jensen at least suggests that performing a cache flush will “prevent use of
the cache memory by any of the plurality of software tasks,” as claimed.
Moreover, Appellant argues that performing a cache flush in the claimed
manner will “prevent use of the cache memory by any of the plurality of
software tasks.” See Reply Br. 2 (“A software tasks will not access or use
the cache memory when the cache memory has no data, as is the case after
the claimed cache flush.”). Thus, to the extent Appellant has identified a
cache flush as the mechanism for preventing use of the cache memory by
other software tasks, Jensen teaches the claimed cache flush and, therefore,
teaches the claimed prevention, as well.
For these reasons, we sustain the obviousness rejection of claim 1. We
also sustain the rejection of independent claims 7 and 11, and dependent
claims 2‒6, 8‒10, and 12‒14, for which Appellant relies on the same
arguments. See Appeal Br. 12.
DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
1, 7, 11 112(a) Written Description 1, 7, 11
1–14 103 Jensen, Wilson, Jegu 1–14
Overall
Outcome
1–14

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Application 15/381,349

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TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED