Ex Parte Yu et al

Patent Trial and Appeal Board

Dec 12, 2018

14037185 (P.T.A.B. Dec. 12, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/037,185 09/25/2013
43859 7590 12/14/2018
SLATER MATSIL, LLP/TSMC
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252
FIRST NAMED INVENTOR
Chen-Hua Yu
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TSM12-1310 8224
EXAMINER
ZARNEKE, DAVID A
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
12/14/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@slatermatsil.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHEN-HUA YU and DER-CHY ANG YEH
Appeal2018-001501
Application 14/037,185
Technology Center 2800
Before JAMES C. HOUSEL, GEORGE C. BEST, and
DEBRA L. DENNETT, Administrative Patent Judges.
DENNETT, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
Appellant2 appeals under 35 U.S.C. § 134(a) from a rejection of
claims 1-13 and 21-30. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
1 In our Decision, we refer to the Specification filed September 25, 2013
("Spec."); the Final Office Action dated September 23, 2016 Final Act.");
the Advisory Action dated December 21, 2016 ("Adv. Act."); the Appeal
Brief filed June 8, 2017 ("Br."); and the Examiner's Answer dated
September 22, 2017 ("Ans."). Appellant did not file a Reply Brief.
2 Appellant is the Applicant, Taiwan Semiconductor Manufacturing
Company, Ltd., identified as the real party in interest. Br. 2.
Appeal2018-001501
Application 14/037,185
The invention relates to wafer-level chip-scale packaging intermediate
structures, apparatuses, and methods. Claim 1, reproduced below from the
Claims Appendix of the Appeal Brief, illustrates the claimed subject matter:
1. A method of forming a device, comprising:
forming a first redistribution layer (RDL) on a carrier
wafer, the first RDL having one or more mounting pads
disposed on a first side of the first RDL;
mounting one or more interposer dies on a second side of
the first RDL, a first side of the one or more interposer dies
adjacent to the first RDL;
forming a second RDL over a second side of the one or
more interposer dies, the second RDL having a first side
adjacent to the interposer dies and a second side opposite the
first side, one or more lands disposed on the second side of the
second RDL, at least one of the one or more lands in electrical
contact with at least one of the one or more interposer dies or at
least one of the one or more mounting pads;
mounting a secondary component on the lands disposed
on the second side of the second RDL; and
removing the first RDL, the one or more interposer dies,
the second RDL and the secondary component from the carrier
wafer.
REFERENCES
The Examiner relies on the following prior art in rejecting the claims
on appeal:
Heo
Choi et al. ("Choi")
Do et al. ("Do")
US 6,555,917 Bl
US 7,923,304 B2
US 2012/0061855 Al
2
Apr. 29, 2003
Apr. 12, 2011
Mar. 15, 2012
Appeal2018-001501
Application 14/037,185
REJECTIONS
The Examiner maintains and Appellant seeks review of the following
rejections under 35 U.S.C. § 103(a): (1) claims 1-13 and 21-27 over Do in
view of Heo; and (2) claims 28-30 over Do in view of Heo, and further in
view of Choi. Final Act. 3-9; Br. 7-20.
OPINION
Rejection of claims 1-13 and 21-27 as obvious over Do
in view of Heo
The Examiner finds that Do teaches the elements of independent
claims 1, 7, and 21 except for removing the carrier wafer. Final Act. 3-6.
The Examiner finds that Do discloses use of a temporary carrier without
specifically stating that it is not removed until the entire package is formed
on it. Id. at 6. The Examiner finds that Heo teaches use of a temporary tape
that is not removed until the package is completely formed. Id.
Appellant argues that the rejection should be reversed because the
Examiner erred by finding that Do describes or suggests
forming a second RDL [having] one or more lands disposed on
the second side of the second RDL, at least one of the one or
more lands in electrical contact with at least one of the one or
more interposer dies or at least one of the one or more
mounting pads,
as recited in independent claim 1. Br. 7-8 ( emphasis omitted). Independent
claims 7 and 21 have the same or analogous language. See id. at 8, 21-23
(Claims App.).
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Appeal2018-001501
Application 14/037,185
The Examiner finds that Do discloses the limitation in question. Final
Act. 4; Ans. 2. The Examiner relies on Figure 14 of Do, reproduced below:
' 1410 1418 1432 I
1414 1440
FIG.14
Do' s Figure 14 is a cross-sectional view of an integrated circuit
packaging system in a device attaching phase. Do ,r,r 12-14, 24.
Redistribution layer 14383 (RDL) can be formed directly on the adhesive
film layer 1434. Id. ,r 129. RDL 1438 can electrically connect the exposed
portion 1436 of stack connectors 1432 to a semiconductor component (not
shown in Fig. 14) that is mounted over the integrated circuit packaging
system. Id.
In reference to Figure 14, the Examiner finds that Do discloses a
second RDL (RDL 1438) is electrically connected to solder balls
(connectors 1432), which are electrically connected to internal wiring in
substrate 1402, the top of substrate 1402 is electrically connected to the
bottom of substrate 1402, and substrate 1402 is electrically connected to one
to one more mounting pads. Ans. 2 (citing Do ,r,r 39, 43, 129). The
Examiner finds that (interposer) die 1410 is electrically connected to
substrate 1402. Id. (citing Do ,r,r 40, 41).
3 Throughout this Decision, for clarity, labels to elements are presented in
bold font, regardless of their presentation in the original document.
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Appeal2018-001501
Application 14/037,185
Appellant contends that Figure 14 does not illustrate one or more
landing pads in electrical contact with either the asserted (unlabeled)
mounting pads or the asserted interposer die 1410, through connectors 1432
or otherwise. Br. 10. Appellant argues that Do neither teaches nor suggests
that asserted second RDL 1438 could be in electrical contact with asserted
interposer 1410 or asserted unlabeled mounting pads. Id. at 11. Appellant
argues that Do discloses a different purpose for lands on asserted second
RDL, i.e., electrically connecting the exposed portions 1436 of the stack
connectors 1432 to a semiconductor component that is mounted over the
integrated circuit packaging system. Id. (citing Do ,r,r 129-130).
We are not persuaded that the Examiner reversibly errs in this
rejection.
In response to Appellant's arguments, the Examiner draws attention to
paragraph 39 of Do, which states "[t]he package substrate 102 can be
electrically connected between the substrate bottom side 104 and the
substrate top side 106." See Ans. 2. Package substrate 102 in Do, Figures 1
and 3, is analogous to package substrate 1402 in Do, Figure 14. Compare
Do Figs. 1, 3, 14. Thus, the Examiner effectively lays a trail of electrical
connection from lands of the second RDL to at least one or more mounting
pads, as required by claim 1.
In addition, Do' s claim 6 provides that the active side of an integrated
circuit (interposer die) is electrically connected by device connectors to a
substrate top side, which is electrically connected to stack connectors. Do
claim 6. Do describes stack connectors 1432 as being electrically connected
to redistribution layer 1438. Id. ,r 129. Thus, the second RDL is electrically
connected to at least one interposer die, in accordance with claim 1.
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Appeal2018-001501
Application 14/037,185
With respect to secondary reference Heo, Appellant merely argues
that Heo fails to teach the above-discussed claim elements that are assertedly
lacking in Do. Br. 14.
We, therefore, sustain the rejection of claim 1 over Do in view of Heo.
Because Appellant argues claims 2-13 and 21-27 (including independent
claims 7 and 21) are patentable for the same reasons as provided for claim 1
we, likewise, sustain the rejection of claims 2-13 and 21-27.
Rejection of claims 28-30 as obvious over Do, in view of Heo, and
further in view of Choi
Claims 28-30 depend from either claims 1, 7, or 21, and each has
similar recitations, viz.:
forming a molding compound around the one or more
interposer dies and over a portion of the first RDL prior to the
forming the second RDL;
forming an opening in the molding compound after
forming the molding compound around the one or more
interposer dies, the opening exposing a conductive element in
the first RDL; and
filling the opening with a conductor to form a conductive
via.
Br. 24--25 (Claims App'x).
The Examiner finds that Do fails to teach the above limitations, but
that they are disclosed by Choi. Final Act. 9 ( citing Choi, Figs. 3-5). The
Examiner determines that it would have been obvious to one of ordinary
skill in the art at the time of the invention to substitute Choi' s process in
Do' s invention because Choi teaches the equivalence of its method ( as
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Appeal2018-001501
Application 14/037,185
disclosed in Choi, Figs. 3-5) with Do' s method ( as disclosed in Choi, Figs.
11, 12). Id.
We do not sustain the rejection.
Do teaches laminating a substrate with a multi-layer film wherein
stack connectors penetrate the film. Do ,r,r 59, 60, 66, 68, 73. Choi teaches
at least two methods, neither of which involve lamination. See Choi, Figs.
3-7, 10-12. Neither the Final Office Action nor Answer indicate how far
the skilled artisan would follow Do' s path before switching to Choi' s, or
when to switch back to Do's. See generally Final Act. and Ans. Only
impermissible hindsight serves as a guide. See In re Kahn, 441 F.3d 977,
988 (Fed. Cir. 2006) (requiring "some articulated reasoning with some
rational underpinning to support the legal conclusion of obviousness."); In re
Rouffet, 149 F.3d 1350, 1358 (Fed. Cir. 1998) ("hindsight" is inferred when
the specific understanding or principal within the knowledge of one of
ordinary skill in the art leading to the modification of the prior art in order to
arrive at Appellant's claimed invention has not been explained). "[W]e
cannot allow hindsight bias to be the thread that stitches together prior art
patches into something that is the claimed invention." Metalcraft of
Mayville, Inc. v. The Toro Co., 848 F.3d 1358, 1367 (Fed. Cir. 2017).
The rejection of claims 28-30 is not sustained.
DECISION
The rejection of claims 1-13 and 21-27 is affirmed. The rejection of
claims 28-30 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
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Appeal2018-001501
Application 14/037,185
AFFIRMED-IN-PART
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