Ex Parte Yasuda et al

Patent Trials and Appeals Board

Jul 9, 2019

13963796 - (D) (P.T.A.B. Jul. 9, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO.
13/963,796
110647 7590
Sheridan Ross P.C.
1560 Broadway
Suite 1200
Denver, CO 80202
FILING DATE FIRST NAMED INVENTOR
08/09/2013 Shuichiro Yasuda
07/11/2019
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
6810-703 1071
EXAMINER
MUNOZ, ANDRES F
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
07/11/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
sony@sheridanross.com
edocket@sheridanross.com
spowers@sheridanross.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHUICHIRO YASUDA,
DALE COLLINS, and SCOTT E. SILLS
Appeal2018-007038
Application 13/963,796
Technology Center 2800
Before N. WHITNEY WILSON, MICHAEL G. McMANUS, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
CASHION, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF CASE
Pursuant to 35 U.S.C. § 134(a), Appellant 1 appeals from a Final
Action of claims 16-21 and 23-32. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We reverse.
1 Sony Semiconductor Solutions Corporation is the Applicant/ Appellant and
is also identified as the real party in interest. App. Br. 2.
Appeal2018-007038
Application 13/963,796
The invention is directed to a non-volatile memory array. Spec. ,r 1.
Claim 16 illustrates the subject matter claimed and is reproduced below:
16. A non-volatile memory system comprising:
a dielectric layer having a hole;
a first electrode deposited in the hole of the dielectric
layer;
a memory switching layer deposited in the hole and in
direct physical contact with the first electrode and the dielectric
layer;
an ion source layer in direct physical contact with the
memory switching layer and the dielectric layer, and on a side
of the memory switching layer opposite the first electrode; and
a second electrode including:
an interface layer in direct physical contact with
the ion source layer, wherein the interface layer is
chemically and mechanically bonded to the ion source
layer; and
a cap layer in direct physical contact with the
interface layer.
Independent claim 32 is also directed to a non-volatile memory
system but differs from the subject matter of claim 1 in that claim 32 further
requires the first electrode, second electrode, memory switching layer, and
ion source layer reside within the hole of the dielectric layer.
Appellant requests review of the following rejections maintained by
the Examiner:
I. Claims 16-21 and 23-32 rejected under 35 U.S.C. § 103 as
unpatentable over Yasuda (US 2009/0173930 Al, published July 9, 2009)
and Lin (US 2011/0180775 Al, published July 28, 2011).
II. Claims 16, 26-28, and 32 rejected under 35 U.S.C. § 103 as
unpatentable over Mizuguchi (US 2011/0155987 Al, published June 30,
2011) and Lin.
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Appeal2018-007038
Application 13/963,796
OPINI0N2
After review of the respective positions the Appellant provides in the
Appeal and Reply Briefs and the Examiner provides in the Final Action and
the Answer, we reverse the Examiner's prior art rejections of claims 16-21
and 23-32 under 35 U.S.C. § 103 essentially for the reasons the Appellant
presents in the Appeal and Reply Briefs. We add the following for
emphasis.
We refer to the Examiner's Final Action for a complete statement of
the rejections. Final Act. 3-16. Briefly, the Examiner finds that each of
Yasuda and Mizuguchi discloses a non-volatile memory system that differs
from the claimed invention in that the they do not disclose a non-volatile
memory system as comprising at least an ion source layer in direct physical
contact with the memory switching layer and the dielectric layer as claimed.
Final Act. 3--4, 11-12; Yasuda Figure 1; ,r,r 25-36; Mizuguchi Figure 1, ,r,r
24--33. The Examiner relies on Lin's teachings for the missing feature.
According to the Examiner, Lin discloses a memory switching layer (64)
deposited in the hole ( of dielectric layer 67 A/67B) and in direct physical
contact with the first electrode (65) and the dielectric layer (67 A/67B). Final
Act. 5, 12-13; Lin Figures 6, 8, ,r,r 9, 57. The Examiner further explains in
the Answer that Yasuda and Mizuguchi both disclose an ion source layer in
direct physical contact with the memory switching layer and Lin discloses
the ion source layer 62 in direct physical contact with the dielectric layer
67A/67B. Ans. 4--5, 14--15; Yasuda Figure 1, i-fi-f 25-36; MizuguchiFigure
2 We limit our discussion to independent claim 16 for both rejections. The
Appellants' persuasive arguments regarding claim 16 are equally applicable
the rejections of claim 32.
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Appeal2018-007038
Application 13/963,796
1, i-fi-f24-33; Lin Figure 6. From these disclosures, the Examiner determines
that it would have been obvious to one of ordinary skill in the art to modify
Yasuda's and Mizuguchi's layer structure to incorporate Lin's
arrangement/layers because of (1) various benefits and (2) it would be
routine rearrangement of parts by one skilled in the art. Final Act. 6-7, 13;
Ans. 8, 16.
Appellant argues that Lin does not teach at least an ion source layer in
direct physical contact with the memory switching layer and the dielectric
layer as claimed. App. Br. 9, 16. According to Appellant, Lin teaches the
ion source layer 62 is not in direct physical contact with the memory
switching layer 64 because there is a TiTe compound 63 between them.
App. Br. 10. That is, Appellant contends that the Examiner has not
explained how one skilled in the art would arrive at the claimed invention
from the combined teachings of the cited art. Id.
We agree with Appellant that there is reversible error in the
Examiner's determination of obviousness. "[R ]ejections on obviousness
grounds cannot be sustained by mere conclusory statements; instead, there
must be some articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness." In re Kahn, 441 F.3d 977, 988
(Fed. Cir. 2006), quoted with approval in KSR Int 'l Co. v. Teleflex Inc., 550
U.S. 398, 418 (2007).
While the Examiner contends that each reference discloses a partial
layer association that meets part of the claimed layer structure (Ans. 4--5,
14--15), the Examiner has not provided an adequate technical explanation of
why or how one skilled in the art would have arrived at the claimed layer
arrangement from the combined teachings of the cited art. The Examiner
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Appeal2018-007038
Application 13/963,796
has not adequately explained why Lin's arrangement of an ion source layer
in direct physical contact with the dielectric layer would have been suitable
for either Yasuda's or Mizuguchi's non-volatile memory systems.
The Examiner's contention that the combined references result in
various benefits (Ans. 5, 16) is also unpersuasive because it is unsupported
by objective evidence and is, at best, speculatory.
Thus, the Examiner does not provide the requisite rational
underpinning explaining why a person of ordinary skill in the art would have
arrived at the claimed invention from the teachings of the cited art.
Accordingly, we reverse the Examiner's prior art rejections under
35 U.S.C. § 103 for the reasons presented by Appellant and given above.
ORDER
The Examiner's prior art rejections of claims 16-21 and 23-32 under
35 U.S.C. § 103 are reversed.
REVERSED
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