Ex Parte Yan et al

Patent Trial and Appeal Board

Aug 18, 2017

13404558 (P.T.A.B. Aug. 18, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/404,558 02/24/2012 Shouli Yan SIL.0185US (D-11-600-54) 8100
21906 7590 08/22/2017
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
LABOY ANDINO, IVAN A
ART UNIT PAPER NUMBER
2838
NOTIFICATION DATE DELIVERY MODE
08/22/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
tphpto@tphm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHOULI YAN, DAZHI WEI, and ALAN L. WESTWICK
Appeal 2016-000967
Application 13/404,558
Technology Center 2800
Before CATHERINE Q. TIMM, BRIAN D. RANGE, and
JENNIFER R. GUPTA, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL1
STATEMENT OF CASE
Pursuant to 35 U.S.C. § 134(a), Appellants2 appeal from the
Examiner’s decision to reject claims 1—20 under 35 U.S.C. § 102(e) as
anticipated by Shrivas.3 We have jurisdiction under 35 U.S.C. § 6(b).
1 In explaining our Decision, we cite to the Specification dated February 24,
2012 (Spec.), Final Office Action dated September 19, 2014 (Final), the
Appeal Brief dated February 18, 2015 (Appeal Br.), the Examiner’s Answer
dated August 13, 2015 (Ans.), and the Reply Brief dated October 13, 2015
(Reply Br.).
2 Appellants identify the real party in interest as Silicon Laboratories, Inc.
3 Shrivas et al., US 8,344,713 B2, issued Jan.l, 2013.
Appeal 2016-000967
Application 13/404,558
We AFFIRM.
The claims are directed to a regulator and a method of using a
feedback path within the regulator. See, e.g., claims 1, 8, and 15. Figure 3,
reproduced below, shows the location of two feedback paths within the
regulator:
Figure 3 is a block diagram of a linear regulator.
Figure 3 does not depict the circuitry within the feedback paths. The
feedback circuitry is shown in Figure 5.
To further illustrate the claimed invention, we reproduce claim 1 with
reference numerals from Figure 3. We also emphasize the language at issue
in the appeal.
1. A method comprising:
using a pass device [210] of a linear regulator [200] to
provide an output signal [Vout] at an output terminal [194a] of the
linear regulator [200] in response to a signal received at a control
terminal [211] of the pass device [210], the control terminal
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Application 13/404,558
[211] being coupled to a node [at or near 205]4 and the node
being associated with a bias current; and
using a feedback path [230] coupled between the node and
the output terminal [211] of the linear regulator [200] to
communicate a feedback current between the output terminal
[194a] and the node to regulate the output signal [Vout], the using
comprising regulating a magnitude of the feedback current to be
within a range of magnitudes comprising a magnitude that
exceeds a magnitude of the bias current.
Claims Appendix, Appeal Br. 17 (emphasis added).
OPINION
Appellants argue claims 1 and 8 as a group, and separately argue
claims 4, 15, and 20. Appeal Br. 10-16. We address the separately argued
claims insofar as they present separate issues.
Claims 1 and 8
For the rejection of claims 1 and 8, we select claim 1 as
representative.
After considering the Examiner’s rejection and Appellants’
arguments, we frame the issue as follows: Have Appellants identified a
reversible error in the Examiner’s finding that Shrivas describes “using a
feedback path coupled between the node and the output terminal of the
linear regulator to communicate a feedback current between the output
terminal and the node to regulate the output signal” as recited in claim 1?
Appellants have not identified such an error.
4 The Specification does not identify the location of the node in the Figures.
However, it appears that the node is at, or near, the output terminal 205 as
the Specification discloses that the amplifier’s output terminal 205 is
associated with a bias current. Spec. 125.
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Appeal 2016-000967
Application 13/404,558
As acknowledged by Appellants, Shrivas teaches a regulator, depicted
in Figure 2, that includes an error amplifier 102, a pass transistor 104 (pass
device) and two current mirror circuits 202, 204. Appeal Br. 11; Shrivas
col. 3,11. 26-46; Fig. 2. Figure 2 is reproduced below:
VDD
Shrivas’ Figure 2 is a schematic circuit diagram of a regulator.
As can be seen by Shrivas’ Figure 2, the current mirror circuits 202,
204 are coupled to a current signal line between the amplifier 102 and pass
transistor 104. Shrivas Fig. 2. The Examiner finds that the intersection of
the lines between the amplifier 102 and pass transistor 104 is the node
required by claim 1. Final 3. We reproduce an annotated portion of
Shirvas’ Figure 2 to show the location:
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Appeal 2016-000967
Application 13/404,558
VD:D
Annotated Figure 2 of Shrivas with a label showing the location of the node
and arrows showing the direction of current
Shrivas’ pass device (pass transistor 104) provides an output signal
originating from the drain of the pass transistor 104. Annotated Fig. 2
(output signal originates from drain and moves towards resistors R1 and R2
as shown by the downward-facing arrow). The output signal is provided in
response to a signal received at a control terminal (gate) of the pass device.
Shrivas col. 4,11. 55—60. In Figure 2, the gate of pass transistor 104 is
depicted as a circle. The current signal received at the gate (circle shown in
Fig. 2) includes the current signal from the node, which travels from current
mirrors 202, 204 to the node as shown by the left-facing arrows in annotated
Figure 2.
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Appeal 2016-000967
Application 13/404,558
As explained by Shrivas, resistors R1 and R2 generate a scaled-down
version of the output voltage signal that is fed to the error amplifier 102.
Shrivas col. 4,11. 46—61. The error amplifier compares the scaled-down
version of the output voltage to a reference signal Vref and generates an
error-amplified signal that is fed to the gate terminal of the pass-transistor
104. Id. When the gate voltage of the pass transistor 104 changes, the
magnitude of the drain current of the pass transistor 104 also varies and this
varies the magnitude of the output of the voltage signal. Id.
As found by the Examiner, Shrivas discloses a feedback path (path
including current mirrors 202, 204) coupled between a node (located at
intersection of lines between amplifier 102 and pass transistor 104 in Fig. 2)
and output terminal (from pass transistor 104 drain). Final 3; Shrivas Fig. 2.
Appellants contend that “Shrivas fails to disclose using a feedback
path to communicate a feedback current between the output terminal of a
linear regulator and the gate terminal of the pass transistor 104.” Appeal
Br. 12. However, Appellants have not identified a reversible error in the
Examiner’s finding that the communicating required by the claim is
described by Shrivas. This is because Appellants do not address the specific
findings of the Examiner (Final 3). Instead, Appellants focus on C2 and C3
capacitors and the MOSFETs within the current mirror circuits 202, 204 in a
manner that ignores the overall function of the current mirror circuits in the
regulator. Appeal Br. 12; Reply Br. 2. Shrivas specifically teaches
supplying a current generated by either the first or second current mirror to
the gate of the pass transistor (by way of the node) so that the voltage at the
gate terminal is either pulled down or pulled up such that the magnitude of
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Application 13/404,558
the voltage difference between the gate and source changes, which in turn
changes the drain current and output signal. Shrivas col. 3,11. 2—19.
Thus, Appellants have not persuaded us that Shrivas fails to teach
using the feedback path in the manner required by claim 1.
Claim 15
Claim 15 requires a first feedback path and a second feedback path.
Claim 15 requires an amplifier rather than a node. According to claim 15,
“the second feedback path is adapted to communicate a feedback current
between the output terminal of the pass device and the output terminal of the
amplifier to regulate the output signal.”
Appellants focus their arguments on the Examiner’s findings with
regard to the second feedback path. Appeal Br. 14. The Examiner finds that
Shrivas’ circuit, including current mirrors 202, 204, is adapted to
communicate as required by claim 15. Final 13—14. Appellants contend that
“[a]s discussed above, neither circuit 202 nor circuit 204 of Shrivas
communicates a current from an output terminal of pass device 104 to an
output terminal of amplifier 102.” Appeal Br. 14. However, as found by the
Examiner, Shrivas communicates a current from the current mirrors 202,
204 to what was previously referred to as a node and this location is
“between the output terminal of the pass device and the output terminal of
the amplifier.” Moreover, by changing the magnitude of the gate voltage,
this feedback current from the current mirror circuits 202, 204 changes the
magnitude of the output signal across the drain of the pass transistor thus
regulating the output signal as required by claim 15.
Appellants have not persuaded us of a reversible error in the
Examiner’s findings with regard to claim 15.
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Application 13/404,558
Claim 4
Claim 4 depends from claim 1 and further limits the “using feedback
path to communicate the feedback current” step of claim 1 to one that
“comprises communicating the feedback current through a capacitor coupled
between the output terminal and the node.”
The Examiner finds that Shrivas’ capacitors C2 and C3 are used in the
manner required by claim 4. Final 6.
Appellants contend “Shrivas fails to disclose communicating a
feedback current between the output terminal of a regulator and a node (as
defined in claim 1) through either the C2 or C3 capacitor.” Appeal Br. 15.
However, C2 and C3 are within the feedback circuit because they are within
current mirrors 202, 204. Because the current mirrors communicate the
current as required by the claim and contain the C2 and C3 capacitors,
Appellants have not persuaded us of a reversible error in the Examiner’s
finding that Shrivas discloses a method including communicating feedback
current through a capacitor coupled between the output terminal and a node.
Claim 20
Claim 20 depends from claim 15 and requires the second feedback
path comprise “a capacitor coupled between an output terminal of the
regulator and the control terminal.”
Appellants make the same argument as against the rejection of
claim 4. Appeal Br. 15—16. For the reasons given above, we determine that
Appellants have not identified a reversible error in the Examiner’s rejection
of claim 20.
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Application 13/404,558
CONCLUSION
We sustain the Examiner’s rejection.
DECISION
The Examiner’s decision is affirmed.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
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