Ex Parte Yamagami et alDownload PDFPatent Trial and Appeal BoardOct 21, 201312007220 (P.T.A.B. Oct. 21, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/007,220 01/08/2008 Minoru Yamagami 099022-0103 8047 22428 7590 10/21/2013 FOLEY AND LARDNER LLP SUITE 500 3000 K STREET NW WASHINGTON, DC 20007 EXAMINER GOODWIN, DAVID J ART UNIT PAPER NUMBER 2818 MAIL DATE DELIVERY MODE 10/21/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte MINORU YAMAGAMI and HISAYUKI NAGAMINE ____________ Appeal 2011-007372 Application 12/007,220 Technology Center 2800 ____________ Before EDWARD C. KIMLIN, PETER F. KRATZ, and DONNA M. PRAISS, Administrative Patent Judges. KIMLIN, Administrative Patent Judge. DECISION ON APPEAL This is an appeal from the final rejection of claims 10-18 and 20-24. We have jurisdiction under 35 U.S.C. § 6(b). Claim 10 is illustrative: 10. A semiconductor device comprising: a semiconductor circuit region; a dicing line area formed along said semiconductor circuit region to define the semiconductor circuit region; at least one characteristic checking element formed in said dicing line area; Appeal 2011-007372 Application 12/007,220 2 a plurality of first pads formed in said dicing line area and electrically connected to said characteristic checking element; and at least one second pad formed in said semiconductor circuit region apart from said dicing line area and electrically connected to the characteristic checking element, wherein said at least one characteristic checking element is configured to be rendered inoperative by application of a sufficient electric voltage to said second pad during a semiconductor device test operation. The Examiner relies upon the following references as evidence of obviousness: Itoh 5,561,373 Oct. 1, 1996 Sang Gi 7,145,356 B2 Dec. 5, 2006 Maruyama 7,399,990 B2 Jul. 15, 2008 Appellants' claimed invention is directed to a semiconductor device comprising a checking element formed in a dicing line area that is electrically connected to a plurality of first pads formed in the dicing area. The checking element is also electrically connected to a second pad formed in the semiconductor circuit region that is apart from the dicing line area. The checking element is configured to be rendered inoperative by the application of a sufficient electric voltage to the second pad during a semiconductor device test operation. The checking element is used to evaluate a number of manufacturing processes, but the checking element contains manufacturing conditions that include a number of confidential matters of the semiconductor manufacture. Hence, it is desirable to render the checking element inoperative before shipping to a customer. Appeal 2011-007372 Application 12/007,220 3 The appealed claims stand rejected under 35 U.S.C. § 103(a) as follows: (a) claims 10, 11, and 20 over Maruyama, (b) claims 12-17 over Maruyama in view of Ito, and (c) claims 14-18 over Maruyama in view of Sang Gi. We have thoroughly reviewed the respective positions advanced by Appellants and the Examiner. In so doing, we agree with Appellants that the Examiner's legal conclusion of obviousness is not factually supported by the applied prior art. Accordingly, we will not sustain the Examiner's rejections. The Examiner appreciates that Maruyama does not disclose Appellants' claimed configuration wherein the characteristic checking element is rendered inoperative by application of a sufficient electric voltage to a second pad during a semiconductor device test operation. It is the Examiner's position, however, that since it is an inherent property of a circuit that a sufficient voltage can destroy the circuit, there is no difference in structure between the semiconductor devices of Appellants and Maruyama. The Examiner emphasizes that Appellants claim an apparatus and not a process of using the apparatus. We, like Appellants, do not subscribe to the Examiner's position. The appealed claims specifically require that the characteristic checking element is rendered operative upon the application of a sufficient voltage during a semiconductor device test operation. However, the Examiner points to no disclosure in Maruyama that the characteristic checking element is rendered inoperative during a test operation for the semiconductor device. In our view, the claims do not embrace a configuration wherein any applied voltage Appeal 2011-007372 Application 12/007,220 4 would destroy the information contained in the checking element, but only encompass a configuration wherein the checking element is rendered inoperative by the voltage applied during a typical testing operation that would be employed by one of ordinary skill in the art. Manifestly, a reasonable interpretation of the appealed claims does not include a configuration wherein the checking element is destroyed only upon application of a high voltage that is far greater than would be used during a conventional test operation by one of ordinary skill in the art, and which would render the device inoperative. The Examiner's additional citations of Sang Gi and Ito do not remedy the deficiency of Maruyama set forth above. In conclusion, based on the foregoing, we are constrained to reverse the Examiner's rejection. REVERSED cam Copy with citationCopy as parenthetical citation