Ex Parte WellsDownload PDFPatent Trial and Appeal BoardJul 31, 201311828092 (P.T.A.B. Jul. 31, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/828,092 07/25/2007 David H. Wells M4065.1421/P1421 8709 45374 7590 07/31/2013 DICKSTEIN SHAPIRO LLP 1825 EYE STREET, NW WASHINGTON, DC 20006 EXAMINER NEWTON, VALERIE N ART UNIT PAPER NUMBER 2897 MAIL DATE DELIVERY MODE 07/31/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte DAVID H. WELLS ____________ Appeal 2010-011746 Application 11/828,092 Technology Center 2800 ____________ Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM, and ANDREW J. DILLON, Administrative Patent Judges. WHITEHEAD, JR., Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-011746 Application 11/828,092 2 STATEMENT OF THE CASE Appellant is appealing claims 1-5 and 7-25.1 Appeal Brief 3. We have jurisdiction under 35 U.S.C. § 6(b) (2012). We reverse. Introduction The invention is directed to a method of forming a three dimensional variable resistance memory array. Abstract. Illustrative Claim (Emphasis Added) 1. A method of forming a three-dimensional memory array, comprising: forming a first plane of variable resistance memory cells, a second plane of variable resistance memory cells, and at least one central plane of variable resistance memory cells between said first and second planes; and using no more than one patterned mask and a sidewall etching step per each central plane to define the respective variable resistance memory cells. Rejections on Appeal Claims 1-4, 10, 11, 15-19, 23, and 24 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Toda (U.S. Patent Application Publication Number 2007/0285971 A1; published December 13, 2007). Answer 3-5. 1 Appellant indicates that claims 1-5 and 7-53 are appealed. Appeal Brief 3. Only claims 1-5 and 7-25 are appealed; claims 26-53 are withdrawn. See Appeal Brief 32-53. Appeal 2010-011746 Application 11/828,092 3 Claims 5, 7-9, 12, and 22 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Toda and Parkinson (U.S. Patent Number 6,795,338 B2; issued September 21, 2004). Answer 6-7. Claims 13, 14, 20, 21, and 25 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Toda and Chu (U.S. Patent Number 6,767,831 B2; issued July 27, 2004). Answer 7-8. Issue on Appeal Does Toda disclose a method of forming a three-dimensional memory array wherein a sidewall etching step is performed as recited in both independent claims 1 and 18? ANALYSIS Both Appellant and the Examiner agree that Toda fails to disclose a sidewall etching step as recited in independent claim 1 and similarly recited in independent claim 18. Appeal Brief 13-14; Answer 8-9. The Examiner finds, “However a dielectric material is formed and spacers materials are known to be dielectrics, so it would have been obvious to one of ordinary skill in the art at the time of the invention to include a spacer etching step [in Toda] in order isolate the adjacent memory cells from one another.” Answer 5. The Examiner reasons that “the dielectric formation is formed to complete the memory array fabrication” and concludes that the dielectric has to be patterned in order to be completed. Answer 9. However, Appellant argues: [I]t is incorrect that the mere presence of a dielectric fill layer surrounding the memory cell stack structures of Appeal 2010-011746 Application 11/828,092 4 Toda would make it obvious to use a single sidewall etch step to define an analogous memory cell stack. In the case of Toda, the memory cell stacks are first defined and then the dielectric material is deposited between the already defined memory cell stack, merely to isolate the various memory cells of the array. This dielectric fill of Toda plays no role in defining the memory cell stacks, but merely covers them. Appeal Brief 15. We find Appellant’s argument to be persuasive. “The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference . . . . Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art.” See In re Keller, 642 F.2d 413, 425 (CCPA 1981) (citations omitted). We recognize that employment of sidewall spaces is notoriously well known in the art, however, we are constrained by the record and Toda does not indicate or suggest that sidewall spacers are employed to form Toda’s resistance change memory device. Further, the Examiner has not cited a collaborating reference that when combined with Toda, would address Toda’s noted deficiency in regard to independent claims 1 and 18. See Answer 3-5. Therefore, we reverse the Examiner’s obviousness rejections of independent claims 1 and 18, as well as, dependent claims 2-5 and 7-17 and 19-25. DECISION The obviousness rejections of claims 1-5 and 7-25 are reversed. REVERSED llw Copy with citationCopy as parenthetical citation