Ex Parte Wells

Patent Trial and Appeal Board

Oct 17, 2018

14129940 (P.T.A.B. Oct. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/129,940 12/28/2013
57035 7590 10/19/2018
KACVINSKY DAISAK BLUNI PLLC
Attention: Tricia Riddle
430 Davis Drive
Suite 150
Morrisville, NC 27560
FIRST NAMED INVENTOR
Alex M. Wells
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
P54764US/1020P54764US 4744
EXAMINER
THAI,TUANV
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
10/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
inteldocs _ docketing@cpaglobal.com
docketing@kdbfirm.com
intel@kdbfirm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ALEX M. WELLS
Appeal 2018-003639
Application 14/129,940 1
Technology Center 2100
Before ERIC S. FRAHM, CATHERINE SHIANG, and
CARLL. SILVERMAN, Administrative Patent Judges.
SHIANG, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 26-50, which are all the claims pending and rejected in
the application. 2 We have jurisdiction under 35 U.S.C. § 6(b).
We reverse. 3
1 Appellant identifies Intel Corporation as the real party in interest. App. Br.
2.
2 Claims 1-25 have been cancelled. Final Act. 2.
3 Appellant repeatedly lists claims incorrectly. See App. Br. 2 (incorrectly
stating no claim was cancelled); App. Br. 24 (addressing only "claims 1-6,
10-20 and 26-35" in the conclusion).
Appeal 2018-003639
Application 14/129,940
STATEMENT OF THE CASE
Introduction
According to the Specification, the present invention relates to
"increasing the efficiency with which data of a three-dimensional array data
structure is retrieved." Spec. ,r 1. In particular,
data of the cells of a 3D array having a row-column-plane
organization are stored in a storage of a computing device in a
manner in which the data of a set of rows that are adjacent to
each other in two dimensions, including across two or more
adjacent planes, are stored in contiguous storage locations of
the storage to form a tile of storage locations that fits within a
single page of the storage.
Spec. ,r 12. Claim 26 is exemplary:
26. An apparatus comprising:
a processor component of a computing device;
a storage of the computing device, the storage communicatively
coupled to the processor component; and
an interleaving component of the computing device for execution by
the processor component to interleave storage of data of cells of adjacent
rows of a first plane with data of cells of adjacent rows of an adjacent second
plane of a three-dimensional (3D) array among contiguous storage locations
of the storage, the interleaving component to generate an alternating order of
adjacent rows from the first plane and the second plane of the 3D array in an
interleaving pattern by interleaving on a row-by-row basis causing at least
one row of the first plane to be followed by a same row of the adjacent
second plane in contiguous storage locations of the storage.
2
Appeal 2018-003639
Application 14/129,940
References and Rejections4
Claims 26, 32, 34--36, 38, 40, 44, and 49 are rejected under 35 U.S.C.
§ I03(a) as being unpatentable over Donofrio (WO 2013/07092 Al; May 16,
2013) and Kaufman et al (US 2010/0231600 Al; September 16, 2010)
("Kaufman"). Final Act. 2-8.
Claims 27-31, 37, 41, and 45--48 are rejected under 35 U.S.C. § 103
as being unpatentable over Donofrio, Kaufman, and Seigneret et al (US
2008/0055325 Al; March 6, 2008) ("Seigneret"). Final Act. 9-13.
Claims 33, 39, 43, and 50 are rejected under 35 U.S.C. § 103 as being
unpatentable over Donofrio, Kaufman, and Hussain et al (US 2003/0142103
Al; July 31, 2003) ("Hussain"). Final Act. 13-14.
Claim 42 is rejected under 35 U.S.C. § 103 as being unpatentable over
Donofrio, Kaufman, Seigneret, and Egan (US 6,222,561 Bl; April 24,
2001). Final Act. 15. 5
ANALYSIS 6
We have reviewed the Examiner's rejection in light of Appellant's
contentions and the evidence of record. We concur with Appellant's
4 Throughout this opinion, we refer to (1) the Final Rejection dated
November 21, 2016 ("Final Act."); (2) the Appeal Brief dated August 30.
2017 ("App. Br."); (3) the Examiner's Answer dated December 20, 2017
("Ans."); and (4) the Reply Brief dated February 20, 2018 ("Reply Br.").
5 The Examiner cites 35 U.S.C. § I03(a) for the rejections, but the correct
basis for the rejections is 35 U.S.C. § 103. We note Appellant does not
contend the discrepancy caused prejudice.
6 Appellant raises additional arguments. Because the identified issue is
dispositive of the appeal, we do not need to reach the additional arguments.
3
Appeal 2018-003639
Application 14/129,940
contention that the Examiner erred in determining the cited portions of
Donofrio and Kaufman collectively teach
an interleaving component ... to generate an alternating order
of adjacent rows from the first plane and the second plane of the
3D array in an interleaving pattern by interleaving on a row-by-
row basis causing at least one row of the first plane to be
followed by a same row of the adjacent second plane in
contiguous storage locations of the storage,
as recited in independent claim 26 ( emphasis added). See App. Br. 18-21;
Reply Br. 3---6.
The Examiner finds "Donofrio does not disclose interleaving logic."
Final Act. 3. The Examiner then cites Kaufman's Figures 1-2 and
paragraphs 41--42 for teaching the above limitation, but does not specifically
map the italicized limitation. See Final Act. 3; Ans. 19. Nor do the
Examiner's findings (Final Act. 3; Ans. 19) explain why Donofrio and
Kaufman collectively teach the italicized limitation.
We have reviewed the cited Kaufman's portions, and they do not
describe
an interleaving component ... to generate an alternating order
of adjacent rows from the first plane and the second plane of the
3D array in an interleaving pattern by interleaving on a row-by-
row basis causing at least one row of the first plane to be
followed by a same row of the adjacent second plane in
contiguous storage locations of the storage,
as required by claim 26 ( emphasis added). Absent further explanation from
the Examiner, we do not see how the cited Kaufman's portions teach the
italicized claim limitation.
Because the Examiner fails to provide sufficient evidence or
explanation to support the rejection, we are constrained by the record to
reverse the Examiner's rejection of claim 26.
4
Appeal 2018-003639
Application 14/129,940
Each of independent claims 35, 40, and 44 recites a claim limitation
that is substantively similar to the disputed limitation of claim 26. See
claims 35, 40, and 44. Therefore, for similar reasons, we reverse the
Examiner's rejection of independent claims 3 5, 40, and 44.
We also reverse the Examiner's rejection of corresponding dependent
claims 27-34, 36-39, 41--43, and 45-50. Although the Examiner cites
additional references for rejecting some dependent claims, the Examiner has
not shown the additional references overcome the deficiency discussed
above regarding the rejection of claims 26 35, 40, and 44. See Final Act. 9-
15.
DECISION
We reverse the Examiner's decision rejecting claims 26-50.
REVERSED
5