Ex Parte Weber et alDownload PDFPatent Trial and Appeal BoardNov 17, 201613242842 (P.T.A.B. Nov. 17, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 13/242,842 09/23/2011 Hans Weber 57579 7590 11/21/2016 MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES 1255 Crescent Green Suite 200 CARY, NC 27518 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 1012-0298 5404 EXAMINER BELL, LAUREN R ART UNIT PAPER NUMBER 2816 NOTIFICATION DATE DELIVERY MODE 11/21/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): official@mbhiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte HANS WEBER, ROMAN KNOEFLER, and KURT SORSCHAG Appeal2015-003888 Application 13/242,842 Technology Center 2800 Before TERRY J. OWENS, N. WHITNEY WILSON, and MICHAEL G. MCMANUS, Administrative Patent Judges. OWENS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's rejection of claims 1-12. We have jurisdiction under 35 U.S.C. § 6(b ). The Invention The Appellants claim a method for producing a capacitive structure. Claims 1 and 10 are illustrative: 1. A method for producing a capacitive structure in a semiconductor body, comprising: forming a first trench in a first surface of the semiconductor body; forming a first dielectric layer on sidewalls and a bottom of the first trench; forming a first electrode layer on the first dielectric layer; Appeal2015-003888 Application 13/242,842 forming a second trench by removing a part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap; forming a second dielectric layer on sidewalls and a bottom of the second trench; and forming a second electrode layer on the second dielectric layer, such that the second electrode layer is electrically separated from the first electrode layer by the second dielectric layer. 10. A method for forming a multi-level capacitive structure, compnsmg: forming a 1st level capacitive structure in a semiconductor body, the 1st level capacitive structure comprising a first trench, a first dielectric layer on sidewalls and a bottom of the first trench and a first electrode layer on the first dielectric layer; and forming a 2nd level capacitive structure in the semiconductor body, the 2nd level capacitive structure comprising a second trench adjusted to one of the sidewalls of the first trench and extending laterally beyond the one of the sidewalls of the first trench in a direction away from a center of the first trench, a second dielectric layer on sidewalls and a bottom of the second trench and a second electrode layer arranged on the second dielectric layer such that the second electrode layer is electrically isolated from the first electrode layer by the second dielectric layer. Challa Chen The References US 2008/0138953 Al US 2009/0269896 Al The Rejections June 12, 2008 Oct. 29, 2009 The claims stand rejected as follows: claims 1-12 under 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the 2 Appeal2015-003888 Application 13/242,842 inventors regard as the invention, and under 35 U.S.C. § 103 over Challa in view of Chen. OPINION We reverse the rejections. Re} ection under 3 5 US. C. § 112, second paragraph "[T]he indefiniteness inquiry asks whether the claims 'circumscribe a particular area with a reasonable degree of precision and particularity."' Marley Mouldings Ltd. v. Mikron Indus. Inc., 417 F.3d 1356, 1359 (Fed. Cir. 2005) (quoting In re Moore, 439 F.2d 1232, 1235 (CCPA 1971)). The independent claims (1 and 10) require a method for making a capacitive structure wherein a second electrode layer is electrically separated (claim 1) or isolated (claim 10) from a first electrode layer by a second dielectric layer. The Examiner finds that the capacitive structure requires a second dielectric layer which is capable of storing electrical energy between the first and second electrode layers and, therefore, cannot electrically separate or isolate those electrode layers from each other (Final Act. 3; Ans. 4). Thus, the Examiner concludes, the claims are indefinite (id.). As stated in In re Dance, 160 F.3d 1339, 1344 (Fed. Cir. 1998), "the inventor may be his own lexicographer, and may use common words in uncommon ways, provided only that the intended meaning is clear." The Appellants' Specification indicates that the claim terms "electrically separated" and "electrical isolated" refer to the electrical separation or isolation provided by a dielectric layer between two electrode layers in a capacitive structure (Spec. i-fi-143--44). Claim 12 depends from claim 10 and requires "forming at least two additional capacitive structures higher than the 2nd level capacitive 3 Appeal2015-003888 Application 13/242,842 structure, the at least two additional capacitive structures having different levels from one another and at least one of the additional capacitive structures comprising a further trench adjusted to one sidewall of a trench of one capacitive structure at a lower level than the additional capacitive structure." The Examiner concludes that claim 12 is indefinite because "at a lower level than the additional capacitive structure" "is unclear as to which additional structure the limitation refers" (Final Act. 3) and "it is unclear if 'the additional capacitive structure' is one of the 'at least two additional capacitive structures,' one of the 'at least one of the additional capacitive structures,' or is meant to indicate another additional capacitive structure" (Ans. 7). The Appellants' Specification discloses two second level capacitive structures, one comprising dielectric layer 221 between electrode layers 31 and 321 and the other comprising dielectric layer 222 between electrode layers 31 and 322, and two additional capacitive structures (i.e., third level capacitive structures), one comprising dielectric layer 2321 between electrode layer 3321 and electrode layers 31 and 322 and the other comprising dielectric layer 2322 between electrode layer 3322 and electrode layer 322 (Spec. i-f 68; Fig. 10). 1 The Appellants' Specification states that "these two 3rd level capacitive structures are adjusted to one of the 2nd level capacitive structures, namely the second capacitive structure arranged in the right section of Figure 10" (Spec. i-f 68). Hence, the Appellants' Specification 1 Those two additional structures are not described or shown as having the different levels from each other required by claim 12, but the rejection is based upon indefiniteness under 35 U.S.C. § 112, second paragraph, not inadequate written description under 35 U.S.C. § 112, first paragraph. 4 Appeal2015-003888 Application 13/242,842 indicates that the capacitive structure at a lower level than the additional capacitive structure (i.e., the third level capacitive structure) is the second level capacitive structure and that the second level capacitive structure's sidewall at a lower level than the additional capacitive structure is the sidewall on the right in Figure 10 (id.). Accordingly, we reverse the rejection under 35 U.S.C. § 112, second paragraph. Rejection under 35 US.C. § 103 We need address only the independent claims (1 and 10). Claim 1 requires forming a second trench by removing part of a first dielectric layer to form a first gap in a first trench's first surface, widening the gap, and forming a second dielectric layer on sidewalls and a bottom of the second trench. Claim 10 requires forming a second trench which is adjusted to one of a first trench's sidewalls and extends laterally beyond that sidewall in a direction away from a center of a first trench, and forming a second dielectric layer on sidewalls and a bottom of the second trench. Challa lines a first trench (3302) with shield oxide (3308), deposits shield polysilicon (3311) within the shield oxide (3308), removes part of the shield oxide (3308) to form a trough on each side of protruding shield polysilicon (3311 ), and covers the shield polysilicon (3311) and the sidewalls and bottom of the trough with a thin layer of gate oxide (3308a) (if 161; Figs. 33B - 33G). Chen teaches that when forming semiconductor structure trenches having a high aspect ratio (depth/width ratio), "[ s Jome common problems are formation of gaps, voids and/or defects in the filling material, which can adversely impact the device performance characteristics" (if 2). Chen uses a 5 Appeal2015-003888 Application 13/242,842 bevel etch to form sloped trench sidewalls to provide "precise control over the profile of the trenches for low, medium or high aspect ratio trenches" (i1i14, 23; Fig. ID). "The precise control for any given trench aspect ratio enables forming trenches with profiles that are best suited for subsequent processings, such as filling the trenches with gate electrode material (as in trench gate FETs), or filling the trenches with silicon epitaxial material (as in alternating p-n pillar structures in charge balance devices), or filling the trenches with dielectric material (e.g., to form the thick bottom dielectric (TBD, or to form the inner-electrode dielectric (IED) in shielded gate FETs)" (i-f 23). "The ability to form the desired trench profile for any aspect ratio ensures that the material[ s] subsequently formed in the trenches have the desired characteristics and are void-free" (i-f 24). The method "can be used in any semiconductor structure with trenches where control over the trench profile would be beneficial" (id.). The Examiner concludes that because Chen "discloses the broad applicability of the trench formation method by reciting '[t]he techniques in accordance with the invention can be used in any semiconductor structure with trenches where control over the trench profile would be beneficial" (Ans. 8-9) and "Challa is a semiconductor structure with trenches, said trenches used for subsequent processings such as filling with electrode material and dielectric material, one of ordinary skill would have found it obvious to apply the teachings of Chen to the invention of Challa" (Ans. 9). Establishing a prima facie case of obviousness requires an apparent reason to modify the prior art as proposed by the Examiner. See KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). 6 Appeal2015-003888 Application 13/242,842 Chen's disclosure is limited to situations in which precise control of a semiconductor device trench's profile, i.e., degree of slope, is beneficial (i1i123, 24). The Examiner does not establish that such trench profile control is beneficial for semiconductor trenches generally, or that one of ordinary skill in the art would have considered it to be beneficial in Challa's trench having a trough in shield oxide (3308) on each side of protruding shield polysilicon (3311) (i-f 161; Figs. 33F, 33G). The Examiner finds that "[ o ]ne of ordinary skill in the art would understand that with the placement of the gate electrode (3311) and poly shield (3310) [i-f 161; Fig. 33H] in the same recess in the substrate as shown in Figs. 33A-M of Challa, the decreased widths of the spaces to be filled would make filling defects or voids more likely" (Ans. 10). The Examiner does not establish that even if the narrower width of Challa's troughs relative to the width of the trench (Fig. 33F) increases the likelihood of defects or voids in the subsequently-applied thin layer of gate oxide 3308a within the troughs (Fig. 33G), that increased likelihood of defects or voids would have been sufficient, in that particular structure, to have led one of ordinary skill in the art to taper the trench's sidewalls. See In re Warner, 379 F .2d 1011, 1017 (CCP A 1967) ("A rejection based on section 103 clearly must rest on a factual basis, and these facts must be interpreted without hindsight reconstruction of the invention from the prior art"). For the above reasons we reverse the rejection under 35 U.S.C. § 103. DECISION/ORDER The rejections of claims 1-12 under 35 U.S.C. § 112, second paragraph, and under 35 U.S.C. § 103 over Challa in view of Chen are 7 Appeal2015-003888 Application 13/242,842 reversed. It is ordered that the Examiner's decision is reversed. REVERSED 8 Copy with citationCopy as parenthetical citation