Ex Parte Ware

Patent Trial and Appeal Board

Aug 25, 2017

13315149 (P.T.A.B. Aug. 25, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/315,149 12/08/2011 Frederick A. Ware RA940.P.US 4534
89207 7590
Shemwell / Rambus
P.O. Box 70307
Sunnyvale, CA 94086
08/29/2017 EXAMINER
BASHAR, MOHAMMED A
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
08/29/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
annw@rambus.com
charlie @ shemwellaw. com
eofficeaction @ appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte FREDERICK A. WARE
Appeal 2016-004982
Application 13/315,149
Technology Center 2800
Before BEVERLY A. FRANKLIN, JAMES C. HOUSEL, and
DEBRA L. DENNETT, Administrative Patent Judges.
HOUSEL, Administrative Patent Judge.
DECISION ON APPEAL1
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision finally rejecting claims 1—27 under 35 U.S.C. § 102(b)
as anticipated by Lee.3 We have jurisdiction over the appeal under 35
U.S.C. § 6(b).
We AFFIRM.
1 Our decision refers to the Specification (Spec.) filed December 8, 2011, the
Examiner’s Final Office Action (Final Act.) dated April 22, 2014,
Appellant’s Appeal Brief (Br.) filed October 22, 2014, and the Examiner’s
Answer (Ans.) dated March 12, 2015.
2 According to Appellant, the real party in interest is Rambus Inc. Br. 3.
3 Lee et al., US 7,176,714 Bl, issued February 13, 2007 (“Lee”).
Appeal 2016-004982
Application 13/315,149
STATEMENT OF THE CASE
The invention relates to a method of operation within a memory
component having a signaling interface that may be switched to either a first
or a second logical width. Br. 5. Appellant disclose, in an integrated circuit
(IC) device having an adjustable width interface, a selectable number of
input/output (I/O) pins may be used to convey information-bearing signals.
Spec. 13.
Claim 1, reproduced below from the Claims Appendix to the Appeal
Brief, is illustrative of the subject matter on appeal.
1. A method of operation within a memory component, the method
comprising:
receiving write data exclusively via a first set of signaling-
link receivers if a signaling interface of the memory component
is set to a first logical width; and
receiving write data exclusively via a second set of
signaling-link receivers if the signaling interface of the memory
component is set to a second logical width, wherein the second
logical width exceeds the first logical width and the first set of
signaling-link receivers includes at least one signaling-link
receiver not included in the second set of signaling-link
receivers.
Additional independent claims 12 and 27 are directed to a memory
component for performing the method, whereas independent claim 24 is
directed to an IC device having a date interface and a command interface for
performing the method with the memory component.
ANALYSIS
Appellant argues claims 1 and 24 separately, but does not otherwise
argue the claims separately. Specifically, Appellant relies on the same
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Application 13/315,149
arguments for each of independent claims 12 and 27 as presented for claim
1, but adds an additional argument with regard to independent claim 24. Br.
12—13. In accordance with 37 C.F.R. § 41.37(c)(l)(iv), claims 2—23 and 27
stand or fall with claim 1 and claims 25 and 26 stand or fall with claim 24.
The Examiner construes the phrase, “method of operation within a
memory component,” as a method of operation that can be done in any
component of a memory system rather than a method of operation that is
performed within a memory array itself. Ans. 2. The Examiner also
construes the claim recitation, “receiving write data,” as merely receiving
data that is to be written such as to a register or interface, and not requiring
that the data be from an element external to a memory cell to be written on
the memory cell. Id. at 3.
With these constructions in mind, the Examiner finds Lee teaches a
method of operation with a memory component comprising receiving write
data exclusively via a first set of signal-link receivers (DQ circuitry are the
signal-link receivers) if the signaling interface of the memory component is
set to a first logical width and receiving write data exclusively via a second
set of signal-link receivers if the signaling interface is set to a second logical
width that is greater than the first logical width, such that the first set
includes at least one signal-link receivers that is not included in the second
set. Final Act. 2.
Appellant argues that Lee fails to teach each of the two recited steps
of the process of claim 1. Br. 8. In particular, Appellant argues that the
Examiner’s claim interpretation is mistaken because claim 1 requires a
memory component receiving write data. Id. at 9. However, Appellant fails
to explain with any particularity why the Examiner’s interpretation is
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Application 13/315,149
erroneous.4 As indicated above, the Examiner construes the claim as a
method of operation that can be done in any component of a memory system
rather than a method of operation that is performed within a memory array
itself. Claim 1 does not specify in which memory component the operation
is performed and, therefore, by its literal terms, does not restrict the
operation to any particular component, e.g., a memory array. In addition,
Appellant does not direct our attention to any disclosure or other evidence
that would limit the meaning of the claim to operation within a memory
array.
Appellant next argues that Lee’s tree structures are not in a memory
component. Br. 9—10. According to Appellant, Lee fails to disclose or
suggest that the timing tree structures in Lee’s memory controller 2105 could
be deployed within memory 220. Id. at 9. In addition, Appellant asserts that
Lee is silent regarding the internal structure and operation of memory 220.
However, the Examiner finds that Lee’s memory system 200 has two main
components—memory array 220 and memory controller 210—and, as such,
memory controller 210 is a memory component. Ans. 3. Because memory
controller 210 is a memory component, the Examiner’s finding that Lee
teaches that a memory component receives write data is supported by Lee’s
timing tree structures within a memory component, i.e., memory controller
210 and, therefore, within memory system 200.
4 An applicant seeking a narrower construction must either show why the
broader construction is unreasonable or amend the claim to expressly state
the scope intended. In re Morris, 127 L.3d 1048, 1057 (Led. Cir. 1997).
5 Throughout this Opinion, for clarity, we present labels to elements in
figures in bold font, regardless of their presentation in the original document.
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Application 13/315,149
Appellant further argues that even if Lee’s memory 220 was modified
to include the timing tree structures, Lee would fail to meet the limitations of
claim 1 because every DQ line is connected to a dedicated DQ pin 502 that
is likewise coupled to a dedicated internal register 510. Br. 10. Appellant
contends that Lee fails to disclose or suggest that read data arriving within
the memory controller 210 via DQ lines is somehow received via different
sets of read data receivers. Id. Appellants also contend that Lee’s
strobe/timing signals are different from read signals. Id. at 11.
Appellant’s argument is not persuasive because the Examiner’s
rejection does not require modification of Lee’s memory array 220 because,
as explained above, Lee’s memory controller 210 is a memory component of
memory 200 within the scope of claim 1. In addition, the Examiner finds
Lee teaches that register 510 outputs read data to PLD core 420 (part of
memory controller 210), where the PLD core receives write data from
memory, based on data signal receiver DQ and associated strobe signal
receiver DQS where the strobe signal goes through DQS bus 520 to register
510. Ans. 5. As such, the Examiner finds Lee teaches timing signal DQS
relates to data DQ because DQS drives register 510 which receives data via
DQ and the specific strobe timing must be set up before data transfer to PLD
core 420. Id. In addition, the Examiner finds Lee’s logic data width
depends on the specific configuration of DQS bus 520 selected by selection
devices 710, which activates a first set of DQS with their respective set of
DQ lines to receive data for a first logic width, and activates a second,
different set of DQS with their respective set of DQ lines to receive data for
a second logic width. Id. Lee supports the Examiner’s finding. Lee teaches
that “the DQS bus may route DQS signals from one, two, four, or eight
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Application 13/315,149
strobe circuits to a number of register blocks 510.” Lee 7:56—59. Lee
further teaches that “tree network 700 can be configured to interface with
memories having different data widths.” Id. at 7:62—63.
Regarding independent claim 24, the Examiner finds Lee teaches an
integrated circuit device having a command interface to output a logic width
value to the memory component. Final Act. 7—8. Appellant submits that
Lee fails to teach such a command interface or a data interface. Br. 13.
However, Appellant fails to identify with any specificity how or why the
Examiner’s finding regarding the presence of a command interface and a
data interface in Lee is in error or otherwise lacks support in Lee’s
disclosure. See 37 C.F.R. § 41.37(c)(l)(vii) (noting that an argument that
merely points out what a claim recites is unpersuasive). The Examiner
specifically identifies selection device 710 as the command interface
because “it set up the logical width value to the memory component,” and
specifically identifies register 510 as the data interface because “PLD core
420 receive write data through register block 510.” Ans. 6. Appellant fails
to address these specific findings or otherwise identify error therein.
DECISION
Upon consideration of the record, and for the reasons given above and
in the Final Office Action and the Answer, the decision of the Examiner
rejecting claims 1—27 under 35 U.S.C. § 102(b) as anticipated by Lee is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
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