Ex Parte Vineis et al

Board of Patent Appeals and Interferences

Feb 20, 2009

10268425 (B.P.A.I. Feb. 20, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte CHRISTOPHER J. VINEIS, RICHARD WESTHOFF and
MAYANK BULSARA
____________

Appeal 2008-5873
Application 10/268,425
Technology Center 1700
____________

Decided:1 February 24, 2009
____________

Before BRADLEY R. GARRIS, MICHAEL P. COLAIANNI, and
JEFFREY B. ROBERTSON, Administrative Patent Judges.

ROBERTSON, Administrative Patent Judge.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) (2002) from the
Examiner’s rejection of claims 1-12, 14-16, 18-34, and 65-82.2 (Examiner’s
Answer entered January 22, 2008, hereinafter “Ans.”). We have jurisdiction
pursuant to 35 U.S.C. § 6(b) (2002).
We AFFIRM-IN-PART.
THE INVENTION
Appellants describe methods for forming semiconductor structures.
Appellants state that the methods result in substantially relaxed cap layers of
uniform composition. (Spec. 5, ll. 10-14).
Claims 1, 2, and 14, reproduced below, are representative of the subject
matter on appeal.
1. A method for forming a semiconductor structure, comprising
the steps of:
providing a semiconductor substrate having a top surface
and a rough edge angled away from the surface;
thereafter growing a cap layer over the top surface of the
substrate, the cap layer being substantially relaxed, having a
uniform composition, and having a lattice constant different
from a lattice constant of the semiconductor substrate; and
polishing the rough edge of the substrate after at least a
portion of the cap layer is grown.

2. A method for forming a semiconductor structure, comprising
the steps of:
providing a semiconductor substrate having a top surface
and a rough edge angled away from the surface;

2 Claims 13, 17, and 35-64 have been canceled. (Appeal Brief filed
November 9, 2007, hereinafter “App. Br.,” 2).
Appeal 2008-5873
Application 10/268,425

forming a relaxed compositionally graded layer over the
top surface of the substrate having the rough edge; and
forming a cap layer over the graded layer, the cap layer
being substantially relaxed and having a uniform composition,
and having a lattice constant different from a lattice constant of
the semiconductor substrate,
wherein the rough edge has a roughness greater than 10
angstroms.

14. A method for forming a semiconductor structure,
comprising the steps of:
providing a semiconductor substrate having a top surface
and a rough edge angled away from the surface;
thereafter forming a relaxed compositionally graded layer
over the top surface of the substrate;
polishing the rough edge of the substrate after at least a
portion of the graded layer is formed; and
forming a cap layer over the graded layer, the cap layer
being substantially relaxed, having a uniform composition, and
having a lattice constant different from a lattice constant of the
semiconductor substrate,
wherein the graded layer is proximate the relaxed cap
layer.

THE REJECTIONS
The prior art and disclosures relied upon by the Examiner in rejecting the
claims on appeal are:
Noguchi JP 10-270685 Oct. 9, 19983

Feichtinger et al., "Misfit Dislocation Nucleation Study in p/p+
Silicon", Journal of Electrochemical Society, 148 (7) June 2001, pp
G379-G382.

3 An English translation of Noguchi is of record.
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Application 10/268,425

Cheng et al., "Electron Mobility Enhancement in Strained-Si n-
MOSFETs Fabricated on SiGe-On-Insulator (SGOI) substrates", IEEE
Electronic Device Letters, Vol. 22, No. 7, July 2001, pp. 321-323.

Akino US 6,417,108 B1 Jul. 9, 2002

Applicant's Admitted Prior Art (AAPA), pages 3, 11, and 12 of the
Specification filed October 10, 2002 in the instant application.

Noguchi US 6,682,965 B1 Jan 27, 20044

There are five grounds of rejection under 35 U.S.C. § 103(a) on
appeal: (1) the Examiner rejected claims 2, 3, 73, 74, and 80 as being
unpatentable over Cheng in view of Feichtinger; (2) the Examiner rejected
claims 2, 3, 73, 74, and 80 as being unpatentable over Cheng in view of
AAPA; (3) the Examiner rejected claims 1, 4-12, 14-16, 18-25, 27-31, 33,
65-72, 75-79, 81, and 82 as being unpatentable over Cheng in view of
Akino; (4) the Examiner rejected claims 32 and 34 as being unpatentable
over Cheng in view of Akino and further in view of Noguchi; and (5) the
Examiner rejected claim 26 as being unpatentable over Cheng in view of
Akino, and further in view of AAPA or Feichtinger.

Rejection of claims 2, 3, 73, 74, and 80 as being unpatentable over
Cheng in view of Feichtinger

The Examiner found that Cheng describes the claimed method for
forming a semiconductor substrate except for providing a semiconductor
substrate having a rough edge with a roughness greater than 10 Angstroms.

4 The Examiner cited US 6,682,965 B1 to Noguchi as a translation of JP 10-
270685 to Noguchi. (Ans. 9).
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(Ans. 3 and 4). The Examiner found that the semiconductor substrate
disclosed by Feichtinger inherently has a rough edge due to the mechanical
edge shaping process used to produce the semiconductor substrate. (Ans. 4).
The Examiner determined that it would have been obvious to modify
Cheng’s substrate with the mechanical edge shaping process of Feichtinger
so that the substrate could withstand further mechanical handling and to
produce a wafer that is more resistant to breakage. (Ans. 4). The Examiner
also determined that because Cheng in view of Feichtinger disclose a similar
method of edge shaping as Appellants, the semiconductor substrate would be
expected to have an edge roughness greater than 100 Angstroms. (Ans. 4
and 5).
Appellants contend that Feichtinger teaches polishing the substrate
edge prior to deposition of a silicon epitaxial layer, which teaches against
depositing a layer on a substrate having a rough edge. (App. Br. 13).

ISSUE
Have Appellants shown that the Examiner reversibly erred in
determining that providing a semiconductor substrate having a rough edge
would have been obvious over Cheng in view of Feichtinger?
We answer this question in the negative.

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellants disclose that substrates with a rough edge provide a
heterogeneous source for nucleation of misfit dislocations, which
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helps prevent localized regions of high misfit densities, reducing
the conditions that cause dislocation pile-ups. (Spec. 5, ll. 5-9).
2. Appellants’ Specification states, “the process of relaxation occurs
through the formation of misfit dislocations at the interface
between two lattice-mismatched layers . . . Because dislocations
cannot terminate inside a crystal, misfit dislocations have vertical
dislocation segments at each end (termed ‘threaded dislocations’),
that may rise through the crystal to reach a top surface of the
wafer.” (Spec. 2, ll. 18-22).
3. Appellants’ Specification states, “[t]he stress field associated with
misfit dislocations may also cause dislocation pile-ups under
certain conditions. Dislocation pile-ups are a linear agglomeration
of threading dislocations. Because pile-ups represent a high
localized density of threading dislocations, they may render
devices formed in that region unusable.” (Spec. 2, l. 29 - 3, l. 2).
4. Cheng describes a substrate fabrication process where a relaxed
SiGe cap layer is deposited over a SiGe buffer layer grown on a Si
donor wafer. (p. 321, right column).
5. Cheng does not disclose whether the Si donor wafer has been edge
polished.
6. Cheng discloses that the donor wafer is bonded to a handle wafer,
and the donor wafer is removed, where a strained Si layer is grown
on top of a relaxed SiGe layer. (Paragraph bridging pages 321 and
322).
7. Cheng teaches that no relaxation via misfit dislocation is
introduced into the strained Si layer. (p. 322, left column).
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8. Feichtinger discloses that crystalline damage to semiconductor
wafers is introduced during the mechanical edge shaping process,
where the edge shaping process is employed to make wafers more
resistant to breakage. (P. G379, right column).
9. Feichtinger discloses that different damage removal steps are
employed to reduce the damage to the wafer, including caustic
etching and a combination of caustic etching and chemical
mechanical edge polishing. (P. G379, right column).
10. Feichtinger teaches that “[t]he misfit dislocation density and length
decreases with the change of the mechanical edge shaping from
coarse to fine (decreased roughness).” (p. G380, right column).
11. Feichtinger teaches that the roughness of the substrate edge is
between 100 and 150 Angstroms when no polishing treatment is
applied, about 50 Angstroms when a caustic etch step is applied,
and greater than 0 Angstroms when a combination of caustic
etching and chemical mechanical polishing is applied. (P. G381,
right column; Fig. 6).

PRINCIPLES OF LAW
In an obviousness rejection, the combination of references must be
considered as a whole, rather than the specific teaching of each reference. In
re McLaughlin, 443 F.2d 1392, 1395 (CCPA 1971); In re Simon, 461 F.2d
1387, 1390 (CCPA 1972).

ANALYSIS
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We select appealed claim 2 as being representative pursuant to 37
C.F.R. § 41.37(c)(1)(vii) (2006).
Appellants contend that the combination of Cheng and Feichtinger
would make no sense because Cheng requires the presence of a relaxed
layer, and Feichtinger teaches removal of misfit dislocations, where misfit
dislocations provide the only mechanism of relaxation. (Reply Brief filed
March 24, 2008, hereinafter “Rep. Br.,” 4). However, Appellants overlook
what Feichtinger as a whole conveys to one of ordinary skill in the art.
Specifically, Feichtinger discloses that in order to decrease misfit dislocation
density the edge roughness of the substrate may be decreased. (FF 10).
However, Feichtinger also discloses that the substrate edge is rough when no
polishing treatment is applied. (FF 11). Thus, we agree with the Examiner
that because Cheng is silent as to the characteristics of the substrate (FF 5),
one of ordinary skill in the art would have performed Feichtinger’s
mechanical edge shaping process to render the substrate more resistant to
breakage. (FF 8). One of ordinary skill in the art would have also not
polished the substrate edge subsequent to mechanical edge shaping to allow
for sufficient misfit dislocations in order to form Cheng’s relaxed layer.
(See FF 10 and 11). Indeed, one of ordinary skill in the art would seek to
avoid polishing the substrate after edge shaping, otherwise, a strained layer
would form. (See Rep. Br. 4).
Appellants also assert that the Examiner incorrectly interprets
Feichtinger to disclose that polishing the wafers after mechanical edge
shaping makes a wafer more vulnerable to breakage. (Rep. Br. 5). The
Examiner’s statement is: “Feichtinger [teaches] that it would have been
obvious to a person of ordinary skill in the art at the time of the invention to
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perform epitaxial deposition on a substrate without any subsequent polishing
because mechanical edge shaping [makes] wafers more resistant to
breakage.” (Ans. 13). Contrary to Appellants’ assertion, the Examiner does
not state that polishing makes a wafer more vulnerable to breakage, but
merely recognizes that polishing is not necessary to obtain the benefits of
breakage resistance obtained from mechanical edge shaping. Therefore,
Appellants’ argument is not persuasive.

Rejection of claims 2, 3, 73, 74, and 80 as being unpatentable over
Cheng in view of AAPA

The Examiner found that Cheng describes the claimed method for
forming a semiconductor substrate except for providing a semiconductor
substrate having a rough edge with a roughness greater than 10 Angstroms.
(Ans. 3 and 4). The Examiner found that AAPA teaches that the recited
roughness of the substrate is inherently present as a result of the mechanical
edge shaping process conventionally used to form the semiconductor
substrate. (Ans. 4). The Examiner determined that it would have been
obvious to modify Cheng’s substrate with the mechanical edge shaping
process of AAPA so that the substrate could withstand further mechanical
handling and produce a wafer that is more resistant to breakage. (Ans. 4).
The Examiner also determined that in view of AAPA, the use of the
conventional edge shaping process would be expected to produce substrates
that have an edge roughness greater than 100 Angstroms. (Ans. 4).
Appellants argue that the material characterized by the Examiner as
AAPA, is not prior art, but a description of the invention. (App. Br. 13).

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ISSUE
Have Appellants shown that the Examiner erred in determining that
Appellants’ Specification is admitted prior art?
We answer this question in the affirmative.

ADDITIONAL FINDING OF FACT
12. Appellants Specification states, “[t]he roughness of the rough edge
20 is inherently present in substrate 10 when, for example,
substrate 10 is cut from a boule traditionally formed by the
Czochralski method, and is subjected to the conventional
mechanical edge shaping process described above.” (Spec. 11, l.
30 – 12, l. 2).
PRINCIPLES OF LAW
A statement by an applicant in the specification or made during
prosecution identifying the work of another as “prior art” is an admission
which can be relied upon for both anticipation and obviousness
determinations, regardless of whether the admitted prior art would otherwise
qualify as prior art under the statutory categories of 35 U.S.C. 102.
Riverwood Int ’l Corp. v. R.A. Jones & Co., 324 F.3d 1346, 1354 (Fed. Cir.
2003).
ANALYSIS
We agree with Appellants that the portion of the Specification relied
on by the Examiner as AAPA is not admitted prior art, but a description of
how to obtain the recited rough edge of the semiconductor substrate.
Although Appellants rely on techniques that are “traditionally” used or
“conventional” in the course of forming their substrate, Appellants do not
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identify the semiconductor substrate recited in the claims as the work of
another. (See FF 12). Thus, the recited semiconductor substrate is not
admitted prior art. Therefore, we reverse the Examiner’s rejection of Cheng
in view of AAPA because the Examiner improperly relies on Appellants’
disclosure to reject the claims.

Rejection of claims 1, 4-12, 14-16, 18-25, 27-31, 33, 65-72, 75-79, 81,
and 82 as being unpatentable over Cheng in view of Akino and
Rejections of claims 26, 32, and 34

The Examiner found Cheng teaches the claimed method of forming a
semiconductor structure except for polishing the rough edge of the substrate
after at least a portion of the graded layer or cap layer is formed. (Ans. 5
and 7). The Examiner found that Akino teaches a structure including a
support made of silicon, a semiconductor layer of SiGe, and an insulation
layer, where the semiconductor layer and insulating layer are edge polished
in order to prevent chipping. (Ans. 6). The Examiner determined that it
would have been obvious to modify Cheng by polishing the edge of the SiGe
layer to prevent chipping. (Ans. 6).
Appellants argue that neither Cheng nor Akino teaches or suggests
polishing a rough edge of the substrate after the growth of a graded layer or
cap layer over the substrate. (App. Br. 15 and 16). Appellants contend that
Akino discloses polishing a handle wafer, while Cheng discloses growing a
cap layer over a graded layer over a donor wafer. (App. Br. 15). Appellants
argue that one of ordinary skill in the art would not have polished the donor
wafer of Cheng in accordance with the method of Akino prior to transferring
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the material to the handle wafer and removing the donor wafer. (App. Br.
15).

ISSUE
Have Appellants shown that the Examiner erred in determining that
polishing the rough edge of the substrate after a portion of a graded layer or
cap layer is formed would have been obvious over Cheng in view of Akino?
We answer this question in the affirmative.

ADDITIONAL FINDINGS OF FACT

13. Akino states:
According to an aspect of the invention, the above object is
achieved by providing a semiconductor substrate comprising a
support member, an insulation layer arranged on the support
member and a semiconductor layer arranged on the insulation
layer, characterized in that the outer peripheral extremity of said
semiconductor layer is located inside the outer peripheral
extremity of said support member and the outer peripheral
extremity of said insulation layer is located between the outer
peripheral extremity of said semiconductor layer and that of
said support member so that the outer peripheral portion of the
semiconductor substrate including said insulation layer and said
semiconductor layer shows a stepped profile.
(Col. 3, ll. 4-16).
14. Akino states:
More specifically, the bottom of the outer peripheral extremity
of the semiconductor layer 3 and the top of the outer peripheral
extremity of the insulation layer 2 are offset relative to each
other by a horizontal distance d so that . . . the outer peripheral
extremity of the semiconductor layer 3 does not show an
overhanging profile. . . . Therefore, the outer peripheral
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extremity of the semiconductor layer 3 can hardly give rise to a
chipping phenomenon and debris.
(Col. 4, ll. 30-40).
15. Akino discloses that a rotary-type edge polisher may be used to
remove the outer peripheral portions of the substrate. (Col. 11, ll.
51-65).

PRINCIPLES OF LAW
It is well settled that all the claim limitations must be taught or
suggested by the prior art to establish a prima facie case of obviousness.
In re Royka, 490 F.2d 981, 985 (CCPA 1974). The Court in KSR stated,
“[o]ften, it will be necessary for a court to look to interrelated teachings of
multiple patents; the effects of demands known to the design community or
present in the marketplace; and the background knowledge possessed by a
person having ordinary skill in the art, all in order to determine whether
there was an apparent reason to combine the known elements in the fashion
claimed by the patent at issue. To facilitate review, this analysis should be
made explicit. See In re Kahn, 441 F.3d 977, 988 (CA Fed. 2006)
(“[R]ejections on obviousness grounds cannot be sustained by mere
conclusory statements; instead, there must be some articulated reasoning
with some rational underpinning to support the legal conclusion of
obviousness”).” KSR Int'l Co. v. Teleflex Inc., 127 S. Ct. 1727, 1740-41
(2007).

ANALYSIS
The claims recite polishing the rough edge of the substrate after at
least a portion of the cap layer (claim 1) or graded layer (claim 14) is
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formed. Cheng describes fabricating a substrate where a relaxed cap layer is
deposited over a buffer layer grown on a Si donor wafer. (FF 4). Therefore,
in order to meet the claim limitation, the donor substrate of Cheng must be
polished, because it is the substrate on which the graded layer and/or cap
layer is formed. We agree with Appellants, that Cheng in view of Akino
fails to disclose polishing the donor substrate. (App. Br. 15).
Akino describes polishing the outer peripheral layer of a
semiconductor substrate to produce a stepped profile and eliminate an
overhanging profile to reduce chipping. (FF 13 and 14). As argued by
Appellants, Cheng discloses that the donor wafer is “flipped” and bonded to
the handle wafer. (App. Br. 17). Thus, if a stepped profile according to
Akino is applied to Cheng’s donor wafer prior to bonding with the handle
wafer, the stepped profile would be inverted, resulting in an overhanging
profile when transferred onto the handle wafer. This is the very problem
that Akino seeks to eliminate in order to prevent chipping and debris. (FF
14). Therefore, one of ordinary skill in the art would not have applied
Akino’s polishing method to Cheng in the manner suggested by the
Examiner. The Examiner’s statement that “removing the [chipping]
problem at its earliest stage would have been obvious to one of ordinary skill
at the time of the invention” (Ans. 15) does not sufficiently explain how one
of ordinary skill in the art would have modified Akino’s method in order to
polish Cheng’s donor wafer before it is removed from the semiconductor
structure while still producing the stepped profile necessary for reduced
chipping.
Further, if Cheng’s handle wafer is polished after the donor wafer is
bonded thereto and removed, the claim limitation of “polishing the rough
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edge of the substrate” would not be met. The handle wafer substrate is not
the substrate over which the cap layer or graded layer is grown. (See FF 4
and 6). Thus, polishing the handle wafer to form a stepped profile after the
donor wafer is removed is not polishing the rough edge of “the substrate” as
recited in the claim. The Examiner has not provided any other sufficient
rationale to account for the deficiencies of the combination of Cheng and
Akino. Therefore, we reverse the Examiner’s rejection of claims 1, 4-12,
14-16, 18-25, 27-31, 33, 65-72, 75-79, 81 as being unpatentable over Cheng
in view of Akino.
We reverse the Examiner’s rejection of claims 32 and 34 as being
unpatentable over Cheng in view of Akino and further in view of Noguchi
and claim 26 as being unpatentable over Cheng in view of Akino, and
further in view of AAPA or Feichtinger for the same reasons.

CONCLUSION
Appellants have failed to demonstrate that the Examiner erred in
determining that providing a semiconductor substrate having a rough edge
would have been obvious over Cheng in view of Feichtinger.
Appellants have demonstrated that the Examiner erred in determining
that Appellants’ Specification is admitted prior art.
Appellants have demonstrated that the Examiner erred in determining
that polishing the rough edge of the substrate after a graded layer or cap
layer is formed would have been obvious over Cheng in view of Akino.

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ORDER
We affirm the Examiner’s decision rejecting claims 2, 3, 73, 74, and
80 under 35 U.S.C. § 103(a) as being unpatentable over Cheng in view of
Feichtinger.
We reverse the Examiner’s decision rejecting claims 2, 3, 73, 74, and
80 under 35 U.S.C. § 103(a) as being unpatentable over Cheng in view of
AAPA.
We reverse the Examiner’s decision rejecting claims 1, 4-12, 14-16,
18-25, 27-31, 33, 65-72, 75-79, 81, and 82 under 35 U.S.C. § 103(a) as
being unpatentable over Cheng in view of Akino.
We reverse the Examiner’s decision rejecting claims 32 and 34 as
being unpatentable over Cheng in view of Akino and further in view of
Noguchi.
We reverse the Examiner’s decision rejecting claim 26 as being
unpatentable over Cheng in view of Akino, and further in view of AAPA or
Feichtinger.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. §1.136(a)(1)(iv).
AFFIRMED-IN-PART

tc

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