Ex Parte Thayer et alDownload PDFPatent Trial and Appeal BoardAug 30, 201311394585 (P.T.A.B. Aug. 30, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte LARRY J. THAYER, ANDREW C. WALTON, MIKE H. COGDILL, and GEORGE KREJCI ____________________ Appeal 2011-003686 Application 11/394,585 Technology Center 2100 ____________________ Before ROBERT E. NAPPI, DENISE M. POTHIER, and IRVIN E. BRANCH, Administrative Patent Judges. BRANCH, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-003686 Application 11/394,585 2 STATEMENT OF CASE Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. Illustrative Claims The claims are directed to systems and methods of selectively managing errors in memory modules. Abstract. Claims 1, 10, and 19, reproduced below with disputed limitations italicized, are illustrative of the claimed subject matter: 1. A method for selectively managing errors in memory modules, comprising: monitoring for persistent errors in the memory modules; mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors; and initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache. 10. A memory system comprising: a memory controller for a plurality of memory modules; a management processor operatively associated with the memory controller and a spare memory cache, the management processor executing: program code for identifying errors in the memory modules; program code selectively invoked to obviate persistent errors in the memory modules by routing at least some read/write requests to the spare memory cache; and program code selectively invoked to erase a portion of the memory modules if the spare memory cache is exhausted. Appeal 2011-003686 Application 11/394,585 3 19. A system for selectively managing errors in memory modules, comprising: means for identifying persistent errors in the memory modules; means for rerouting IO addressed to at least a portion of the memory modules instead to a spare memory cache only in response to persistent errors; and means for erasing at least a portion of the memory modules only in response to all cache lines in the spare memory cache being used for the rerouted IO. References The prior art relied upon by the Examiner in rejecting the claims on appeal is: Franaszek US 2001/0044880 A1 Nov. 22, 2001 Olarig US 6,467,048 B1 Oct. 15, 2002 Hou US 2003/0041295 A1 Feb. 27, 2003 Sato US 2003/0065891 A1 Apr. 3, 2003 Bink US 2007/0005897 A1 Jan. 4, 2007 (filed Aug. 17, 2004) Cheng US 2004/0210803 A1 Oct. 21, 2004 Lin US 6,820,224 B1 Nov. 16, 2004 Rejections The Examiner made the following rejections. Claims 1 and 3-6 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Lin, Hou, and Bink. Ans. 3-7. Claims 7, 9, 10, 12, 13, 15,16, and 18-20 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Lin, Hou, Bink, and Cheng. Ans. 7-16. Claims 11 and 14 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Lin, Hou, Bink, Cheng, and Franaszek. Ans. 16-17. Appeal 2011-003686 Application 11/394,585 4 Claim 8 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Lin, Bink, Hou, Franaszek, Sato, and Cheng. Ans. 18-19. Claim 2 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Lin, Hou, Bink, and Franaszek. Ans. 19-20. Claim 17 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Lin, Hou, Bink, Cheng, and Olarig. Ans. 20-22. ANALYSIS We have reviewed the Examiner’s rejections in light of Appellants’ arguments in both the Appeal Brief and Reply Brief. Rather than exhaustively repeat the arguments here, we refer to the Briefs and the Answer for the respective positions of Appellants and the Examiner. Claim 1 Appellants argue that the Examiner’s rejection of claim 1 is in error (App. Br. 6-7; Reply Br. 3-5), presenting us with the issue of whether the Examiner erred in finding claim 1 obvious over Lin, Hou, and Bink. Appellants make the following contentions: (1) The cited references, either alone or in combination, do not teach both the “mapping” and “memory erasure” limitations (App. Br. 6-7; Reply Br. 3-4); and (2) Bink “teaches against” “initiating memory erasure [on at least a portion of the memory modules] only if insufficient cache lines are available in the spare memory cache” (Reply Br. 4). First Contention Appellants state that “[t]he cited references do not teach or suggest at Appeal 2011-003686 Application 11/394,585 5 least [the “mapping” and “erasure”] recitations.” Reply Br. 3; see also App. Br. 6. Appellants concede that Bink “describes a mapping function,” but take issue with the Examiner’s assertion that “memory erasure” is not necessarily tied to “mapping.” Reply Br. 3, referring to Ans. 23. Appellants assert that because Bink “only discloses ‘mapping’ and fails to disclose ‘memory erasure,’ . . . the reference is deficient and does not support the rejection.” Reply Br. 3. We are not persuaded of error based on Bink not teaching both the “mapping” and the “erasure” limitations. The Examiner correctly points out (Ans. 23) that the argument amounts to an inappropriate attack on individual references where the rejection is based on a combination. See In re Keller, 642 F.2d 413, 426 (CCPA 1981) (“one cannot show nonobviousness by attacking references individually where, as here, the rejections are based on combinations of references” (citations omitted)). The Examiner cites Lin for the mapping limitation (Ans. 3, citing Lin col. 1, ll. 29-37), which Appellants do not dispute. Further, according to claim 1, memory erasure is initiated “only if insufficient cache lines are available in the spare memory cache.” Initiating memory erasure is, therefore, conditional, and it does not necessarily take place. Conditional steps in a method claim need not be found in the prior art if, under the broadest scenario, the method need not invoke the steps. See Ex parte Katz, 2011 WL 514314, *4 (BPAI Jan. 27, 2011) (citing In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004)). Here, initiating memory erasure does not take place if sufficient cache lines are available in the spare memory cache. Accordingly, since the erasure limitation is conditional and Appellants’ other arguments amount to Appeal 2011-003686 Application 11/394,585 6 an unpersuasive piecemeal attack, we are not persuaded of error in the rejection based on the foregoing. Second Contention Appellants’ contention that Bink “teaches against” the memory erasure limitation is unpersuasive. A reference may be said to teach away when a person of ordinary skill, upon reading the reference, would be discouraged from following the path set out in the reference, or would be led in a direction divergent from the path that was taken by the applicant. In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994) (citations omitted). “The prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed in the … application.” In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Here, Appellants have not persuaded us that Bink’s teaching that “there is no need for spare modules” (Bink ¶ 43) “criticize[s], discredit[s], or otherwise discourage[s]” initiating memory erasure only if insufficient cache lines are available in the spare memory cache. We do not see where a lack of need for spare modules amounts to a teaching away from initiating memory erasure only if the spare memory cache is full. Accordingly, because Appellants’ contentions have not persuaded us of error based on the record before us, we sustain the rejection of claim 1 and of claims 3-5, 7, and 9, which depend therefrom and are not separately argued with particularity. Claim 6 Appeal 2011-003686 Application 11/394,585 7 Appellants argue that the Examiner’s rejection of claim 6 is in error (App. Br. 7-8; Reply Br. 5-6), presenting us with the issue of whether the Examiner erred in finding claim 6 obvious over Lin, Hou, and Bink. Claim 6 depends from claim 1 and recites, “identifying the portions of the memory modules for memory erasure based on an error rate of the memory modules.” In addition to the reasons Appellants argue for claim 1, Appellants contend that the rejection of claim 6 is in error because Hou’s teaching of “blocking the memory the second time an error occurs is not the same as an error rate.” App. Br. 7-8; Reply Br. 5-6. Appellants reject as “pure conjecture” the Examiner’s reasoning that Hou at paragraph 25 teaches obviating an error when the same error occurs twice (e.g., an error rate) by counting the number of errors in two tries and making a different decision accordingly. Reply Br. 6, citing Ans. 24. We agree with the Examiner’s reasoning (Ans. 24; see also Ans. 7) and are unpersuaded by Appellants that the rejection is in error. We sustain the rejection of claim 6. Claim 10 Appellants argue that the Examiner’s rejection of claim 10 is in error (App. Br. 8-9; Reply Br. 6), presenting us with the issue of whether the Examiner erred in finding claim 10 obvious over Lin, Hou, Bink, and Cheng. Appellants argue the rejection of claim 10 by incorporating arguments from claim 1 and further arguing that the limitations of claim 10 differ from claim 1. App. Br. 8-9; Reply Br. 6. Unlike claim 1, Appellants’ arguments have persuaded us of error. Appeal 2011-003686 Application 11/394,585 8 As discussed above Appellants arguments directed to claim 1 have not persuaded us of error, in part because the memory erasure step is part of a conditional step. Claim 10, however, differs from claim 1 in that it is an apparatus claim and positively recites the management processor executing program code for implementing the conditional erasing method step of claim 1. Thus, our analysis of claim 10 differs from our analysis of claim 1 in this regard. In rejecting claim 1, the Examiner finds Bink teaches “erasing defective blocks when no spares are available” (Ans. 4, citing Bink, Fig. 2 and ¶ 43), concluding: It would have been obvious to a person of ordinary skill of the art at the time the invention was made to incorporate the teachings of Bink into the teachings of Lin to initiate memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache. The modification would be obvious because erasing technique allows the memory to have no spare modules. Id. At paragraph 43 Bink recites, The difference between the remapping scheme according to the invention and remapping schemes related to main memories with redundant modules for replacing faulty modules is that in a cache there are no really “redundant” modules, since each module contributes to the associativity and thus the performance. The advantage is that there is no need for spare modules, i.e. modules that are not used unless they replace some faulty modules. The Examiner also references Bink, paragraph 3, explaining that Bink teaches “a process of erasing defective blocks when the redundant cache is not the desirable choice.” Ans. 23. The Examiner’s reasoning does not persuade us, however, that Bink teaches erasing defective memory blocks “if Appeal 2011-003686 Application 11/394,585 9 the spare cache is exhausted” as recited in claim 10. Hence, we are persuaded that the Examiner erred in rejecting claim 10. Accordingly, for the reasons stated by Appellants, we reverse the Examiner’s rejections of claim 10 and of claims 11-18 which depend therefrom. Claim 19 Appellants argue that the Examiner’s rejection of claim 19 is in error citing the rejection of claim 1, adding that “Cheng at paragraph [0041], Hou at paragraph [0025], and Lin at col. 3, lines 1-18 still do not teach means for erasing” (App. Br. at 11). This presents us with the issue of whether the Examiner erred in finding claim 19 obvious over Lin, Hou, Bink, and Cheng. Claim 19 is an independent claim in which all limitations recite “means for” followed by functional language. When a claim uses “means for” language, there is a presumption that the claim invokes 35 U.S.C. § 112, ¶ 6. See Biomedino, L.L.C. v. Waters Techs. Corp., 490 F.3d 946, 950 (Fed. Cir. 2007). As such, these limitations shall be construed to cover the corresponding structure described in the specification and its equivalents. In re Donaldson Co., Inc., 16 F.3d 1189, 1195 (Fed. Cir. 1994) (en banc). Thus, claim 19, like claim 10, is drawn to an apparatus claim and positively recites a means for erasing in response to all cache lines in the spare memory cache being used for the rerouted IO. The Examiner’s rejection (Ans. 14-15) and response to Appellants’ arguments (id. at 27) do not aid us in understanding how Cheng, Hou, and Lin collectively teach or suggest “means for erasing . . . only in response to all cache lines in the spare memory cache being used for the rerouted IO.” Appeal 2011-003686 Application 11/394,585 10 Accordingly, based on the record and for the reasons stated by Appellants, we are constrained to reverse the rejection of claim 19 and of claim 20, which depends therefrom. Claim 2 Claim 2 depends from claim 1 and recites, “initiating page de- allocation for at least one of the memory modules only after using the spare memory cache and initiating memory erasure.” Appellants argue that the Examiner erred in rejecting claim 2 because Franaszek, either alone or in combination with Lin, Hou, Bink, does not teach page de-allocation as claimed. App. Br. 13-14; Reply Br. 9. We note our analysis of claim 1, supra, and find that, like the erasing limitation of claim 1, the page de- allocation limitation of claim 2 is conditional and is not necessarily invoked; it occurs “only after . . . initiating memory erasure,” which is not required to occur. Accordingly, we sustain the rejection of claim 2. Claim 8 Claim 8 depends from claim 1 and recites, “determining there are insufficient cache lines available in the spare memory cache if additional cache lines are predicted to be needed before memory erasure frees the additional cache lines.” Appellants argue that the Examiner erred in rejecting claim 8. App. Br. 12-13; Reply Br. 8. We find claim 8 to be conditional because the “determining” is not invoked if additional cache lines are not predicted to be needed before memory erasure frees the additional cache lines. We therefore sustain the rejection of claim 8. Appeal 2011-003686 Application 11/394,585 11 IN THE EVENT OF FURTHER PROSECUTION We have decided the appeal before us. In the event of further prosecution, we leave it to the Examiner to consider whether claim 19 complies with 35 U.S.C. § 112, ¶ 2. We further leave it to the Examiner to consider whether, although nominally reciting a “system” in the preamble (see, e.g., Catalina Marketing Int'l, Inc., v. Coolsavings.com Inc., 289 F.3d 801, 808 (Fed. Cir. 2002); see also Am. Med. Sys., Inc. v. Biolitec, 618 F.3d 1354, 1358 (Fed. Cir. 2010) (noting that a preamble that “merely gives a descriptive name to the set of limitations in the body of the claim that completely set forth the invention” has no separate limiting effect)), claim 19 is eligible subject matter under 35 U.S.C. § 101 (see In re Ferguson, 558 F.3d 1359, 1363 (Fed. Cir. 2009)). CONCLUSIONS On the record before us: The Examiner did not err in rejecting claims 1 and 3-6 under 35 U.S.C. § 103(a) as unpatentable over Lin, Hou, and Bink; The Examiner did not err in rejecting claims 7 and 9 under 35 U.S.C. § 103(a) as unpatentable over Lin, Hou, Bink, and Cheng; The Examiner erred in rejecting claims 10, 12-13, 15-16, and 18-20 under 35 U.S.C. § 103(a) as unpatentable over Lin, Hou, Bink, and Cheng; The Examiner erred in rejecting claims 11 and 14 under 35 U.S.C. § 103(a) as unpatentable over Lin, Hou, Bink, Cheng, and Franaszek; The Examiner did not err in rejecting claim 8 under 35 U.S.C. § 103(a) as unpatentable over Lin, Bink, Hou, Franaszek, Sato, and Cheng; Appeal 2011-003686 Application 11/394,585 12 The Examiner did not err in rejecting claim 2 under 35 U.S.C. § 103(a) as unpatentable over Lin, Hou, Bink, and Franaszek; and The Examiner erred in rejecting claim 17 under 35 U.S.C. § 103(a) as unpatentable over Lin, Hou, Bink, Cheng, and Olarig. DECISION For the above reasons, the Examiner’s rejection of claims 1-9 is affirmed and the Examiner’s rejection of claims 10-20 is reversed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED-IN-PART tj Copy with citationCopy as parenthetical citation