Ex Parte Tawadrous et alDownload PDFBoard of Patent Appeals and InterferencesApr 27, 200910438441 (B.P.A.I. Apr. 27, 2009) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte SAMEH W. TAWADROUS, RONALD H. DECK, and THOMAS E. VOOR ____________ Appeal 2008-4693 Application 10/438,441 Technology Center 3600 ____________ Decided:1 April 27, 2009 ____________ Before JENNIFER D. BAHR, LINDA E. HORNER, and STEVEN D.A. McCARTHY, Administrative Patent Judges. HORNER, Administrative Patent Judge DECISION ON APPEAL 1 The two month time period for filing an appeal or commencing a civil action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date shown on this page of the decision. The time period does not run from the Mail Date (paper delivery) or Notification Date (electronic delivery). Appeal 2008-4693 Application 10/438,441 2 STATEMENT OF THE CASE Sameh W. Tawadrous et al. (Appellants) seek our review under 35 U.S.C. § 134 of the final rejection of claims 1-40. We have jurisdiction under 35 U.S.C. § 6(b) (2002). SUMMARY OF DECISION We AFFIRM-IN-PART. THE INVENTION The Appellants’ claimed invention is to techniques for generating and managing precision frequency sources in cellular telephones or other communications devices having a positioning capability, such as Global Positioning System (GPS) or other location service. Spec. 1:16-18. Claim 1, reproduced below, is representative of the subject matter on appeal. 1. A system for generating a frequency reference in a hybrid communications device, comprising: a clock source in a communications portion of the hybrid communications device, the clock source generating a clock signal at a first frequency; a frequency correction module, communicating with the clock source, the frequency correction module generating a clock signal at a corrected first frequency; a frequency converter, the frequency converter communicating with the frequency correction module to receive the clock signal at the Appeal 2008-4693 Application 10/438,441 3 corrected first frequency and outputting a clock signal at a second frequency which is lower than the first frequency to operate a positioning receiver portion of the hybrid communications device to receive a wireless positioning signal such that the positioning receiver portion does not need an additional oscillator. THE REJECTIONS The Examiner relies upon the following as evidence of unpatentability: Horton US 6,041,222 Mar. 21, 2000 The Appellants seek review of the Examiner’s rejection of claims 1- 40 under 35 U.S.C. § 102(b) as anticipated by Horton.2 ISSUES The Appellants contend the Examiner erred in rejecting claims 1-40 because Horton does not show a frequency correction module as recited in claims 1 and 14. Br. 9. The Examiner found that Horton discloses a phase locked loop circuit that acts as a frequency correction module. Ans. 4. The first issue presented by this appeal is: Have the Appellants shown the Examiner erred in finding that Horton discloses the claimed frequency correction module? 2 The Examiner withdrew an alternate rejection of claims 1-40 under 35 U.S.C. § 102(e) as anticipated by U.S. Patent No. 6,400,314 to Krasner. Ans. 2. Appeal 2008-4693 Application 10/438,441 4 The Appellants further contend the Examiner erred in rejecting claims 4 and 17, because the Examiner relies on Horton’s frequency synthesizer 192 as both the frequency correction module of claims 1 and 14 and the frequency synthesizer of claims 4 and 17. Br. 9. The Examiner found that a portion of Horton’s frequency synthesizer 192 operates as the frequency correction module and another portion of Horton’s frequency synthesizer 192 operates as the claimed frequency synthesizer of claims 4 and 17. Ans. 6-7. The second issue presented by this appeal is: Have the Appellants shown the Examiner erred in finding that Horton discloses both a frequency correction module and a frequency synthesizer? The Appellants further argue the Examiner failed to make adequate findings to show where the elements of claims 5-11 and 18-24 are disclosed in Horton. Br. 8-9. The third issue presented by this appeal is: Have the Appellants shown the Examiner failed to set forth a prima facie case of anticipation of claims 5-11 and 18-24? FINDINGS OF FACT We find that the following enumerated findings are supported by at least a preponderance of the evidence. Ethicon, Inc. v. Quigg, 849 F.2d 1422, 1427 (Fed. Cir. 1988) (explaining the general evidentiary standard for proceedings before the Office). Appeal 2008-4693 Application 10/438,441 5 1. The Appellants identify the frequency correction module of claim 1 as phase locked loop circuit 110 and identify the step of generating a clock signal at a corrected first frequency as corresponding to element 210 of Figure 2 described on page 9, lines 11-15, which refers to transmission of the output of the base oscillator 102 to phase locked loop 110. Br. 4. 2. The Appellants’ Specification describes a frequency correction module (phase locked loop circuit 110) as follows: The phase locked loop 110 may include a phase comparator 112, to compare the phase of the base oscillator 102 with the phase of a high-frequency oscillator 116. High-frequency oscillator 116 may for instance be implemented as a voltage controlled high-frequency oscillator (VCO) generating frequencies, for instance, in the 800/900 MHz, 1900 MHz or other ranges for cellular or other operation. A loop filter 114 may low-pass filter the output of the phase comparator 112 to remove higher frequency artifacts or other noise. The output of the loop filter 114 may in turn drive the high-frequency oscillator 116 to operating frequencies, which through the return provided by loop divider 118 completes a closed feedback loop to phase comparator 112. The phase of the high-frequency oscillator 116 is thereby locked to the phase of the base oscillator 102, so that the phase angle between them remains zero or approximately zero, or at a fixed or approximately fixed separation during operation. Spec. 7:3-15. Appeal 2008-4693 Application 10/438,441 6 3. Horton discloses a wireless mobile terminal having a wireless transceiver and a GPS receiver, where the wireless transceiver and the GPS receiver share a frequency reference signal. Horton, col. 2, l. 64 – col. 3, l. 1. 4. Horton discloses that the frequency reference signal is a radio frequency control signal generated by a phase locked loop (PLL) circuit of the wireless transceiver. Horton, col. 3, ll. 54-57. 5. Horton discloses a PLL circuit 162 including a main frequency synthesizer 192, a loop filter 196, a voltage controlled oscillator (VCO) 198, and a feedback divider. Horton, col. 9, l. 66 – col. 10, l. 4; Fig. 9. 6. Horton discloses that a voltage-controlled, temperature compensated reference crystal oscillator 190 provides a reference frequency signal as an input to a phase detector 245 in the frequency synthesizer 192. Horton, col. 9, ll. 38-41; Fig. 9. 7. The phase detector 245 also receives as input a synthesized signal derived from the signal output by the VCO, fed back through the feedback divider of the PLL circuit. Horton, Fig. 9. 8. In Horton, the phase detector 245 compares the phase of the base oscillator 190 with the phase of the voltage-controlled high- frequency oscillator 198. The loop filter 196 filters output derived from this comparison. The output of the loop filter 196 drives the VCO 198 to operating frequencies, which through the return Appeal 2008-4693 Application 10/438,441 7 provided by feedback divider completes a closed feedback loop to the phase detector 245. Horton, Fig. 9. 9. Horton discloses a reference divider that divides the base signal from the oscillator 190 to provide a synthesized signal to phase detector 245. Horton, Fig. 9. PRINCIPLES OF LAW “A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference.†Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628, 631 (Fed. Cir. 1987). To establish anticipation, every element and limitation of the claimed invention must be found in a single prior art reference, arranged as in the claim. Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir. 2001). In other words, there must be no difference between the claimed invention and the reference disclosure, as viewed by a person of ordinary skill in the field of the invention. Scripps Clinic & Research Found. v. Genentech Inc., 927 F.2d 1565, 1576 (Fed. Cir. 1991). ANALYSIS The Appellants argue that Horton’s frequency synthesizer 192 is “analogous to [Appellants’] claimed clock source†and is not the frequency correction module of claims 1 and 14. Br. 9. Appeal 2008-4693 Application 10/438,441 8 We note at the outset that claims 27-40 do not include the limitation of a frequency correction module or the step of generating a clock signal at a corrected first frequency. Although the Appellants state that claims 1-40 are being appealed (Ans. 3), the Appellants have not alleged any particular error in the Examiner’s rejection of claims 27-40 as being anticipated by Horton. Br. 9. As such, we summarily sustain the Examiner’s rejection of claims 27- 40 under 35 U.S.C. § 102(b). Turning to the Appellants’ argument as to independent claims 1 and 14, we find no error in the Examiner’s reading of Horton. The Appellants identify the frequency correction module of claim 1 as corresponding to the phase locked loop circuit 110 and the frequency correction step of claim 14 as being implemented by the phase locked loop circuit 110 (Fact 1). The Appellants’ Specification describes the phase locked loop circuit 110 as including a phase comparator 112, a loop filter 114, a high-frequency oscillator 116, and a loop divider 118 (Fact 2). We agree with the Examiner’s finding that Horton discloses a PLL circuit including a phase comparator 245, a loop filter 196, a high-frequency oscillator 198, and a loop divider, which PLL circuit operates as a frequency correction module (Facts 4-8). Thus, Horton anticipates all of the elements of claim 1 and the steps of claim 14. With regard to claims 4 and 17, which recite that the clock source comprises a synthesizer, we find that Horton discloses a reference divider which provides a synthesized clock signal to the phase comparator 245 of the phase locked loop circuit (Fact 9). Appeal 2008-4693 Application 10/438,441 9 The Appellants further argue that the rejection fails to specify where the limitations of claims 5-11 and 18-24 are found in Horton. Br. 8-9. To make a showing of anticipation, the Examiner must make a finding that the prior art reference discloses every element of the claimed invention. Karsten Mfg. Corp., 242 F.3d at 1383. Neither the Examiner’s Final Office Action nor the Examiner’s Answer contains sufficient findings to put the Appellants on notice as to where the limitations of claims 5-11 and 18-24 are found in Horton. Thus, we cannot sustain the rejection of these dependent claims. CONCLUSIONS Appellants have failed to show that the Examiner erred in rejecting claims 1-4, 12-17, and 25-40 under 35 U.S.C. § 102(b) as anticipated by Horton. Appellants have shown, however, that the Examiner failed to set forth a prima facie case of anticipation of claims 5-11 and 18-24. DECISION The decision of the Examiner to reject claims 1-4, 12-17, and 25-40 is affirmed, and the decision of the Examiner to reject claims 5-11 and 18-24 is reversed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv) (2007). AFFIRMED-IN-PART Vsh Appeal 2008-4693 Application 10/438,441 10 SCOTT M. GARRETT MOTOROLA, INC. LAW DEPARTMENT 8000 WEST SUNRISE BOULEVARD FORT LAUDERDALE, FL 33322 Copy with citationCopy as parenthetical citation