Ex Parte Tatapudi et al

Patent Trial and Appeal Board

Feb 25, 2014

12050876 (P.T.A.B. Feb. 25, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/050,876 03/18/2008 Suryanarayana B. Tatapudi MICS:0258/MAN/DRY 9479
52142 7590 02/25/2014
FLETCHER YODER (MICRON TECHNOLOGY, INC.)
P.O. BOX 692289
HOUSTON, TX 77269-2289
EXAMINER
ROJAS, DANIEL E
ART UNIT PAPER NUMBER
2842
MAIL DATE DELIVERY MODE
02/25/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte SURYANARAYANA B. TATAPUDI
and
JEFFREY P. WRIGHT
____________

Appeal 2011-011372
Application 12/050,876
Technology Center 2800
____________

Before TERRY J. OWENS, ROMULO H. DELMENDO, and
MICHAEL P. COLAIANNI, Administrative Patent Judges.

DELMENDO, Administrative Patent Judge

DECISION ON APPEAL

The Appellants1 seek our review of a final rejection of claims 1-25.
We have jurisdiction under 35 U.S.C. §§ 6(b) and 134(a).
We reverse.

1 The Appellants identify the real party in interest as “Micron Technology,
Inc.” Appeal Brief filed September 27, 2010 (“App. Br.”) 2.
Appeal 2011-011372
Application 12/050,876

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BACKGROUND

The invention relates to memory devices and sub-systems of such
devices. Specification (“Spec.”) ¶ 1.
Representative claim 1 is reproduced below:
1. An output driver, comprising:
a driver stage, wherein the driver stage can be configured
to one of a plurality of output impedances; and
a pre-driver circuit coupled the driver stage, wherein the
pre-driver circuit can be configured based at least partially on
the output impedance.
App. Br. 25 (Claims App’x).
The Examiner rejected the claims as follows:
I. Claims 1-10 and 12-25 under 35 U.S.C. § 102(b) as anticipated
by Rho (U.S. Patent Application Publication 2008/0303558 A1
published December 11, 2008); and
II. Claim 11 under 35 U.S.C. § 103(a) as unpatentable over Rho.

DISCUSSION
I.
Claims 1-6 & 13-25:
Independent claim 1, reproduced above, recites that “the pre-driver
circuit can be configured based at least partially on the output impedance.”
Independent claim 13, which is directed to a method of operating a memory
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device, recites a step of “configuring a pre-driver based at least partially on
the determined output driver strength.” App. Br. 27.
The Examiner found that Rho describes these claim limitations. Ans.
3-4, 6.
The Appellants contend that the Examiner’s findings regarding these
claim limitations are erroneous. App. Br. 10-13.
We agree with the Appellants that the Examiner’s findings constituted
reversible errors. As acknowledged by the Examiner, Ans. 10, Rho teaches
a pre-driver that appears to be configured based on a sensed external voltage
that changes with respect to PVT (process, voltage temperature), not “output
impedance” (claim 1) or “determined output driver strength” (claim 13).
See, e.g., Rho’s ¶¶ 5, 16.
Appreciating these differences, the Examiner argues that “[t]he phrase
‘can be configured’ [in claim 1] only requires that the device is capable of
being modified or configured to be used for the intended function.” Ans. 10
(emphasis added). That is incorrect. Setting aside the Examiner’s failure to
explain in detail what modifications would be necessary, the phrase “can be
configured based at least partially on the output impedance” (claim 1), when
properly construed, requires the specified pre-driver circuit, without
modification, to be capable of performing the recited function.
The Examiner further asserts that “Ohm’s law teaches that current,
voltage, and impedance are all related.” Ans. 10. Ohm’s Law, however,
does not establish that a pre-driver circuit that can be configured to be based
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on external voltage, as disclosed in Rho, is necessarily capable of being
configured to be based at least partially on output impedance without
modification of Rho’s system, as required by claim 1. See also Reply Brief
filed April 7, 2011 at 6-7. Similarly, we find no persuasive evidence or
reasoning to support the Examiner’s finding that Rho’s system or method is
capable of being configured based at least partially on determined output
driver strength, as required by claim 13.
For these reasons, we cannot uphold the rejection of claims 1-6 and
13-25.

Claims 7-10:
Independent claim 7 recites:
7. An output driver system, comprising:
a pre-driver configured to maintain a generally constant
slew rate of an output driver across a plurality of output
impedances.
App. Br. 25.
The Examiner stated that Rho inherently describes a pre-driver
configured to maintain a generally constant slew rate of an output driver
across a plurality of output impedances. Ans. 5. In support, the Examiner
relied on Rho’s Figure 1 and paragraph 16. Id.
The Appellants contend that the Examiner’s finding of inherent
disclosure in Rho is not supported. App. Br. 14-15.
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Again, we agree with the Appellants. Rho teaches improving the slew
rate by taking into account sensed external voltage. Rho’s ¶ 16. The
Examiner failed to direct us to persuasive evidence or reasoning why a
device configured to be based on external voltage is necessarily capable of
being configured based at least partially on output impedance.
Accordingly, we cannot affirm the rejection of claim 7 and claims 8-
10 dependent thereon.

Claim 12:
Claim 12 recites:
12. A memory device, comprising:
an output driver having a configurable output driver
strength and comprising:
a plurality of driver stages arranged in parallel and
wherein each of the plurality of driver stages comprises a
respective pull-up leg and a respective pull-down leg, wherein
each of the respective pull-up legs and each of the respective
pull-down legs comprise a transistor and a fixed resistor; and
a plurality of pre-drivers each having an output coupled
to an input of at least a respective one of the transistors,
wherein each of the plurality of pre-drivers comprises a
configurable circuit comprising a plurality of control inputs
configured to receive signals that are enabled or disabled based
on the output driver strength, and wherein each of the plurality
of pre-drivers is configured to maintain a generally constant
slew rate of the output driver regardless of the output driver
strength.
App. Br. 27 (emphasis added).
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The Examiner found that Rho’s Figure 1 and 2 and paragraph 16
inherently describe the limitation “wherein each of the plurality of pre-
drivers is configured to maintain a generally constant slew rate of the output
driver regardless of the output driver strength.” Ans. 5-6.
The Appellants contend, inter alia, that “there is simply nothing to
support the Examiner's contention that by controlling slew rate to account
for detected PVT variations, the pre-driver 210 of Rho also necessarily
provides for a generally constant slew rate of an output driver regardless of
output driver strength.” App. Br. 16.
Again, we agree with the Appellants. The Examiner has failed to
direct us to persuasive evidence or reasoning to support the finding of
inherent disclosure of the disputed claim limitation.

Claim 11:
Claim 11 recites:
11. A pre-driver circuit, comprising:
an inverter;
a first CMOS inverter;
a second CMOS inverter; and
a third CMOS inverter
wherein the inverter comprises an output coupled in
parallel to the gates of the first CMOS inverter, the second
CMOS inverter, and the third CMOS inverter, and an output of
the pre-driver circuit is coupled in parallel to outputs of the
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first CMOS inverter, the second CMOS inverter, and the third
CMOS inverter.
App. Br. 26 (emphasis added).
Relying on Rho’s Figure 4, the Examiner found, inter alia, that Rho
describes a pre-driver circuit 100 comprising an inverter b1, a first inverter
INV1, a second inverter INV2, and a third inverter within L3, but
acknowledged that the reference does not disclose the first, second, and third
inverters as CMOS inverters. Ans. 8-9, 14. The Examiner asserted,
however, that “it is notoriously old and well known to implement inverters
in a CMOS configuration and that it is common to implement buffers
comprising inverters.” Id. at 9. The Examiner then concluded:
[I]t would have been obvious to one of ordinary skill in the art
that [Rho’s] b1 comprises an inverter and to implement the
first, second, and third inverters as CMOS inverters since all the
claimed elements were known in the prior art and one skilled in
the art could have combined the elements as claimed by known
methods with no change in their respective functions, and the
combination would have yielded predictable results to one of
ordinary skill in the art at the time of invention.
Id.
The Appellants contend, inter alia, that the Examiner failed to account
for the limitation “the inverter comprises an output coupled in parallel to the
gates of the first CMOS inverter, the second CMOS inverter, and the third
CMOS inverter” in claim 23 (emphasis added). App. Br. 23.
We agree with the Appellants. In response to the Appellants’
argument, the Examiner asserted that “all of the elements on Figure 4 are
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connected in parallel at least between their power supplies (they are all
supplied with the same power supplies).” Ans. 14. We do not find the
assertion to be sufficient in addressing the Appellants’ argument based on
the disputed claim limitation.

SUMMARY

Rejections I and II are reversed.

REVERSED

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