Ex Parte Takemura

Patent Trial and Appeal Board

Aug 7, 2017

14552556 (P.T.A.B. Aug. 7, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/552,556 11/25/2014 Yasuhiko TAKEMURA 12732-0965002 8204
26171 7590 08/09/2017
FISH & RICHARDSON P.C. (DC)
P.O. BOX 1022
MINNEAPOLIS, MN 55440-1022
EXAMINER
ALROBAIE, KHAMDAN N
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
08/09/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PATDOCTC@fr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Appeal 2016-007967
Application 14/552,556
Technology Center 2800
Before LINDA M. GAUDETTE, JAMES C. HOUSEL, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
CASHION, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134 from a final rejection of
claims 2—13. We have jurisdiction under 35 U.S.C. § 6.
We AFFIRM.
1 The inventor is identified as Yasuhiko Takemura.
Appeal 2016-007967
Application 14/552,556
Appellant’s invention is best illustrated by independent claim 2,
reproduced below (emphasis added to highlight disputed features):
2. A semiconductor memory device comprising:
a writing bit line;
a writing word line;
a reading bit line;
a reading word line;
a memory cell;
an inverting amplifier circuit configured to supply an
inverted and amplified potential of the reading bit line to the
writing bit line; and
a switch provided between the reading bit line and an
input terminal of the inverting amplifier circuit,
wherein the memory cell comprises a writing transistor, a
reading transistor, and a capacitor comprising a first electrode
and a second electrode,
wherein the switch is configured to control the
connection between the reading bit line and the input terminal
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Application 14/552,556
of the inverting amplifier circuit, depending on whether the
memory cell is rewritten with new data or not,
wherein one of a source and a drain of the writing
transistor, a gate of the reading transistor, and the first electrode
of the capacitor are connected to each other,
wherein the other of the source and the drain of the
writing transistor is connected to the writing bit line,
wherein a gate of the writing transistor is connected to
the writing word line,
wherein one of a source and a drain of the reading
transistor is connected to the reading bit line, and
wherein the second electrode of the capacitor is
connected to the reading word line.
Appellant (see generally Appeal Brief) appeals the following
rejections:
(a) claims 2, 6—8, 12 and 13 rejected under 35 U.S.C. § 103(a) as
unpatentable over Emori (US 6,314,017 Bl, issued November 6, 2001) and
Leigh (US 5,007,022, issued April 9, 1991);
(b) claims 3 and 9 rejected under 35 U.S.C. § 103(a) as unpatentable
over Emori, Leigh, and Yang (US 2006/0098469 Al, published May 11,
2006);
(c) claims 4 and 10 rejected under 35 U.S.C. § 103(a) as unpatentable
over Emori, Leigh, and Worley (US 6,016,268, issued January 18, 2000);
(d) claims 5 and 11 rejected under 35 U.S.C. § 103(a) as unpatentable
over Emori, Leigh, and Shimano (US 2008/0137394 Al, published June 12,
2008); and
(e) claims 2—13 rejected under the judicially created doctrine of
obviousness-type double patenting as unpatentable over claims 2 and 8—12
of Takemura (US 8,902,637 B2, issued December 2, 2014) and Leigh.
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OPINION
Prior Art Rejections under 35 U.S.C. § 103(a)
For Rejections (a)—(d). Appellant relies on the same arguments in
addressing the rejection of independent claims 2 and 8 and of their
respective dependent claims. App. Br. 6. Accordingly, we select claim 2 as
representative of the subject matter before us on appeal for the prior art
rejections. Claims 3—13 stand or fall with claim 2.
We have reviewed each of Appellant’s arguments for patentability.
However, a preponderance of the evidence supports the Examiner’s position
that the subject matter of representative claim 2 is unpatentable.
Accordingly, we sustain the Examiner’s prior art rejections for the reasons
explained in the Answer, and we add the following for emphasis.
Independent claim 2 is directed to a semiconductor memory device
comprising an inverting amplifier circuit configured to supply an inverted
and amplified potential of a reading bit line to a writing bit line and a switch
between the reading bit line and an input terminal of the inverting amplifier
circuit, wherein the switch is configured to control the connection between
the reading bit line and the input terminal of the inverting amplifier circuit,
depending on whether the memory cell is rewritten with new data or not.
The Examiner finds, and Appellant does not dispute, that Emori
discloses a semiconductor memory device that differs from the claimed
invention in that Emori does not disclose the claimed inverting amplifier
circuit and the claimed switch provided between the reading bit line and an
input terminal of the inverting amplifier circuit. Final Act. 5—6; App. Br. 4;
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Emori Figure 21, col. 1,11. 36-41. The Examiner finds Leigh’s Figure 2
shows a refresh circuit 40 comprising (1) an inverting amplifier circuit 46
configured to supply an inverted and amplified potential of the reading bit
line 22 to the writing bit line 14 and (2) a switch 42 between the reading bit
line 22 and an input terminal of the inverting amplifier circuit 46 with the
switch configured to control the connection between the reading bit line and
the input terminal of the inverting amplifier circuit as recited in claim 2.
Final Act. 6—7; Leigh col. 6,11. 19—47. The Examiner further finds a person
of ordinary skill in the art would have used Leigh’s refresh circuitry to
refresh the charge stored in the capacitor of the memory cell to preserve the
data in the memory cell and to help improve the speed of the refresh
operation. Final Act. 7.
Appellant argues there is no reason to modify Emori to incorporate
Leigh’s refresh circuit because Emori is silent about a refresh operation and
does not describe or suggest what type of refresh operation is appropriate.
App. Br. 4.
We find this argument unavailing for the reasons provided by the
Examiner. Ans. 3^4. Appellant’s arguments are premised on bodily
incorporation and are not focused on the Examiner’s reason for combining
the cited art. It is well established that the obviousness inquiry does not ask
“whether the references could be physically combined but whether the
claimed inventions are rendered obvious by the teachings of the prior art as a
whole.” In reEtter, 756 F.2d 852, 859 (Fed. Cir. 1985) (enbanc); see also
In re Keller, 642 F.2d 413, 425 (CCPA 1981) (stating “[t]he test for
obviousness is not whether the features of a secondary reference may be
bodily incorporated into the structure of the primary reference”).
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The portion of Emori relied upon by the Examiner involves a
semiconductor memory device comprising a DRAM. Ans. 3^4; Emori col.
1,11. 19—62. As noted by the Examiner, Leigh is directed to improving
semiconductor memory devices comprising DRAMs because a DRAM
memory cell is a volatile memory cell in which the capacitor loses the
charge and data if the memory cell is not refreshed. Ans. 4; Leigh col. 1,11.
29—33. Cf. Spec. 13. We note that Emori also recognizes an issue
concerning stability of operation at a read operation and guaranteeing
precision of the read data. Emori col. 1,11. 25—28. The Examiner finds
Leigh’s disclosed refresh circuit 40 comprising inverting amplifier circuit 46
and switch 42, connected as required by the subject matter of claim 2,
periodically refreshes the cell so that valid data can be maintained over a
long period of time. Final Act. 6—7; Leigh col. 6,11. 19-47, 62—64. A
person of ordinary skill in the art desiring to effectively use DRAM based
semiconductor memory devices would have reasonably expected that the use
of Leigh’s refresh circuit in the DRAM based semiconductor memory device
of Emori would stabilize the operation of Emori’s semiconductor device by
periodically refreshing the cell so that valid data can be maintained over a
long period of time, as taught by Leigh. In re O’Farrell, 853 F.2d 894, 904
(Fed. Cir. 1988) (“For obviousness under § 103, all that is required is a
reasonable expectation of success.”). Thus, there is a reasonable basis to
combine the teachings of the prior art and arrive at the claimed invention.
Appellant’s arguments do not adequately explain why one skilled in the art
would not have been capable of incorporating Leigh’s refresh circuit into the
semiconductor memory device of Emori and expect Leigh’s refresh circuit
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to periodically refresh Emori’s cell so that valid data can be maintained over
a long period of time.
Appellant further contends the memory cells of Emori are so different
from those of Leigh that one skilled in the art would have had no reason to
apply Leigh’s refresh circuit to the memory device of Emori. App. Br. 4.
According to Appellant, Emori describes the read bit line potential is
changed or unchanged from the precharged potential in accordance with the
stored data at the reading step while Leigh describes the read bit line is
raised or lowered from the precharged potential in accordance with the
stored data at the reading step. App. Br. 4; Emori col. 1,1. 66-col. 2,1. 16;
Leigh col. 4,11. 6—35. Thus, Appellant argues one skilled in the art would
have had no reason to apply Leigh’s refresh or reading circuit to the memory
of Emori because the reading step of Emori is different from that of Leigh.
App. Br. 4.
We are unpersuaded by these arguments as well. The Examiner
explains how the read operations performed by the semiconductor memory
devices of Emori and Leigh, while different, result on their respective read
bit lines having the same value indicating the data stored in the DRAM
memory cell. Ans. 4—5; Emori col. 2,11. 1-16; Leigh col. 4,11. 15—36.
Appellant has not adequately identified error in the Examiner’s
determination.2 Appellant has provided mere attorney argument and such
2 We note that Appellant presented arguments for the first time in the Reply
Brief filed August 25, 2016 in furtherance of their assertion that Emori and
Leigh describe different results of the read operation on a read bit line based
on Leigh’s disclosure that the bit line 22 is charged up to a higher level (than
the precharged level) if the capacitor stores charge. Reply Br. 2; Leigh col.
4,11. 26—31. Any argument not presented in the Appeal Brief will not be
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arguments of counsel cannot take the place of evidence (see e.g., Ans. 12,
13). In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984); In re Payne, 606
F.2d303, 315 (CCPA 1979).
Moreover, even assuming arguendo that the memory cells of Emori
and Leigh are different as contended by Appellant, Appellant has not
adequately explained why such a difference would impact the function of
Leigh’s refresh circuit (of periodically refreshing the cell so that valid data
can be maintained over a long period of time) once incorporated into the
semiconductor memory device of Emori. Leigh col. 6,11. 62—64.
We are also unpersuaded by the argument that the combined teachings
would render Emori unsatisfactory for its intended purpose. App. Br. 6.
Emori and Leigh are both directed to semiconductor memory devices
comprising two transistors and a capacitor. Emori Abstract; Leigh col. 3,11.
12—25. Given these disclosures, Appellant has not adequately explained
why one skilled in the art, using no more than ordinary creativity, would
have not have been capable of incorporating Leigh’s refresh circuit into the
semiconductor memory device of Emori. KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 421 (2007) (“[a] person of ordinary skill is also a person of
ordinary creativity, not an automaton.”); In re Sovish, 769 F.2d 738, 743
considered when filed in a Reply Brief, absent a showing of good cause
explaining why the argument could not have been presented in the Appeal
Brief. See Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010)
(informative) (“[T]he reply brief [is not] an opportunity to make arguments
that could have been made during prosecution, but were not. Nor is the
reply brief an opportunity to make arguments that could have been made in
the principal brief on appeal to rebut the Examiner’s rejections, but were
not.”); see also 37 C.F.R. § 41.41(b)(2). Appellant has not shown good
cause why this argument should now be considered.
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(Fed. Cir. 1985) (skill is presumed on the part of one of ordinary skill in the
art); In re Bozek, 416 F.2d 1385, 1390 (CCPA 1969).
Accordingly, we affirm the Examiner’s prior art rejections of claims
2—13 under 35 U.S.C. § 103(a) for the reasons presented by the Examiner
and given above.
Rejection under the judicially created doctrine of obviousness-type double
patenting
We refer to the Examiner’s Final Action for a statement of the
rejection. Final Act. 3^4. Of note, the basis for this rejection is essentially
similar to the basis for the rejection under 35 U.S.C. § 103(a) discussed
above. Compare Final Act. 3^4 (obviousness-type double patenting
rejection) with Final Act. 5—7 (35 U.S.C. § 103(a) rejection).
As with the rejection discussed above, Appellant argues (1) the
Examiner provides no reason why one skilled in the art would modify claims
2 and 8 of the ’637 patent to incorporate Leigh’s switch 42, in the context of
Leigh’s DRAM circuit, in view of the features recited in claims 2 and 8.
(App. Br. 2—3) and (2) the memory cells recited in the claims of the ’637
patent are so different from those of Leigh, one skilled in the art would have
had no reason to apply the input transistor 42 in the refresh circuit described
by Leigh to the memory device of the ’637 patent {id. at 3).
We are unpersuaded by these arguments for the reasons presented by
the Examiner and given above. Ans. 2—3. Therefore, we affirm the
Examiner’s obviousness-type double patenting rejection.
ORDER
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The Examiner’s prior art rejections of claims 2—13 under
35 U.S.C. § 103(a) are affirmed.
The Examiner’s rejection of claims 2—13 under the judicially created
doctrine of obviousness-type double patenting is affirmed.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
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