Ex Parte SyuDownload PDFPatent Trial and Appeal BoardMar 27, 201712607011 (P.T.A.B. Mar. 27, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/607,011 10/27/2009 Mei-Man Syu 069985-0307 3824 128298 7590 03/29/2017 McDermott Will & Emery LLP (WD/HGST) The McDermott Building 500 North Capitol St., N.W. Washington, DC 20001 EXAMINER CYGIEL, GARY W ART UNIT PAPER NUMBER 2137 NOTIFICATION DATE DELIVERY MODE 03/29/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): mweipdocket @ mwe. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MEI-MAN SYU1 Appeal 2016-002324 Application 12/607,011 Technology Center 2100 Before MICHAEL J. STRAUSS, DANIEL N. FISHMAN, and JAMES W. DEJMEK, Administrative Patent Judges. FISHMAN, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134(a) from a Non-Final Rejection of claims 1—5 and 10-14. Claims 6—9 and 15—18 have been canceled. App. Br. 3.2 We have jurisdiction over the pending claims under 35 U.S.C. § 6(b). We reverse. 1 Appellant identifies Western Digital Corporation as the real party in interest. App. Br. 3. 2 We note Appellant erroneously refers to claims 6—9 and “5—18” as being cancelled. App. Br. 3. We find Appellant’s typographical error to be harmless. Appeal 2016-002324 Application 12/607,011 THE INVENTION Appellant’s invention is directed to reducing the amount of garbage collection in a non-volatile semiconductor memory. Spec., 2, Title. Independent claim 1, reproduced below, is illustrative: 1. A non-volatile semiconductor memory comprising: a memory device comprising a memory array including a plurality of memory segments; and control circuitry operable to: allocate a first set of the plurality of memory segments to a first zone and a second set of the plurality of memory segments to a second zone, wherein the first zone is reserved for storing sequential data and the second zone is reserved for storing random data; receive a plurality of sequential access write commands including sequential data from a host after said allocation of memory segments to the first zone, wherein each of the sequential access write commands identifies one or more logical block addresses (LBAs); receive a plurality of random access write commands including random data from the host after said allocation of memory segments to the second zone, wherein each of the random access write commands identifies one or more LBAs; map the LBAs identified by the sequential access write commands to one or more memory segments of the first zone to generate sequential mapping data including zone number and page number information associated with the one or more memory segments of the first zone; store the sequential data in the one or more memory segments of the first zone; allocate a third set of the plurality of memory segments to a third zone for storing sequential mapping 2 Appeal 2016-002324 Application 12/607,011 data and store the sequential mapping data in the third zone; map the LB As identified by the random access write commands to one or more memory segments of the second zone to generate random mapping data including zone number and page number information associated with the one or more memory segments of the second zone; store the random data in the one or more memory segments of the second zone; and allocate a fourth set of the plurality of memory segments to a fourth zone for storing random mapping data and store the random mapping data in the fourth zone. THE REJECTION Claims 1—5 and 10-14 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Bennett et al. (US 2005/0144360 Al; published June 30, 2005) (“Bennett”) and Chang (US 2008/0270680 Al; published Oct. 30, 2008). Non-Final Act. 3—11. ANALYSIS In rejecting claim 1, the Examiner relies on Bennett to teach or suggest, inter alia, control circuitry operable to “allocate a first set of the plurality of memory segments to a first zone and a second set of the plurality of memory segments to a second zone, wherein the first zone is reserved for storing sequential data and the second zone is reserved for storing random data,” as recited in claim 1. Non-Final Act. 3—4, 11—12. In particular, the Examiner asserts “[t]he claims do not appear to define zones in any way 3 Appeal 2016-002324 Application 12/607,011 other than by the type of data that is stored.” Non-Final Act. 12. The Examiner maps the recited zones to update metablocks having a sequential or non-sequential (chaotic) state as depicted in Bennett’s Figure 13B. Non- Final Act. 3^4. The Examiner further relies on Figures 12A and 12B of Bennett and finds an allocation or re-allocation of update blocks as either sequential or chaotic. Non-Final Act. 4; see also Non-Final Act. 11—12 (citing Bennett Figures 7A, 7B, 19). Appellant contends Bennett fails to teach or suggest allocating memory segments to separate zones, one reserved for storing sequential data and the other reserved for storing random data. App. Br. 8—14; Reply Br. 2— 5. In particular, Appellant asserts Bennett teaches designating a block as either sequential or chaotic according to the type of data that is written therein. App. Br. 10—11 (citing Bennett || 83, 90; Figure 12A). Appellant argues Bennett’s designation of the block is not a pre-designation of the block itself for a particular type of data. App. Br. 10-11. We disagree with the Examiner’s interpretation of claim 1. Claim 1 clearly requires allocation of memory segments to a first zone and allocation of a different set of memory segments to a second zone where each zone is reserved for a corresponding type of data (random or sequential). Here, the Examiner has failed to adequately explain how, nor are we able to ascertain that, Bennett teaches or suggests allocating a memory segment to a zone reserved for storing either sequential or random data. Bennett is generally directed to a non-volatile memory management system. Bennett, Abstract. Bennett’s non-volatile memory is organized in original metablocks for storing logical groups of data. Bennett 117. Bennett teaches an original metablock is sequential when the data stored in the metablock is in the same 4 Appeal 2016-002324 Application 12/607,011 logical order as the logical group, or the original metablock is chaotic otherwise. Bennett || 60-61. Thus, Bennett’s metablocks are not reserved for a corresponding type of data as in claim 1 but, instead, are identified as either sequential or chaotic depending on the sequence of data as it is stored therein. In like manner, an update metablock in Bennett is initially allocated (Bennett | 87) and is identified as a sequential metablock so long as write operations maintain a sequential order {id. at 190). When a write operation in an update metablock is not in sequential order, the update metablock is changed to a non-sequential (chaotic) metablock. Id. 192. Thus, Bennett’s metablocks are not allocated as recited in claim 1 so as to be reserved for a corresponding type of data but, instead, are allocated initially as sequential metablocks and are changed to chaotic metablocks when non-sequential data is written thereto. In view of the above discussion and on the record before us, we find the Examiner erred in rejecting independent claims 1 and 10 and, thus, for the same reason, erred in rejecting all dependent claims therefrom. Therefore, we do not sustain the Examiner’s rejection of claims 1—5 and 10— 14. Appellant raises additional issues in the Briefs. We are persuaded of error with regard to the identified issue discussed supra, which is dispositive as to the rejection of all claims. We, therefore, do not reach the additional issues. 5 Appeal 2016-002324 Application 12/607,011 DECISION We reverse the Examiner’s decision to reject claims 1—5 and 10—14. REVERSED 6 Copy with citationCopy as parenthetical citation