Ex Parte SUNDAHL et al

Patent Trial and Appeal Board

Jan 7, 2019

15198235 (P.T.A.B. Jan. 7, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
15/198,235 06/30/2016 Bradley Edman SUNDAHL
60909 7590 01/09/2019
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134-1709
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SPN11018C3 5503
EXAMINER
TRAN, ANDREW Q
ART UNIT PAPER NUMBER
2812
NOTIFICATION DATE DELIVERY MODE
01/09/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@cypress.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRADLEY EDMAN SUNDAHL,
SEAN MICHAEL O'MULLAN, GREGORY CHARLES YANCEY,
and KENNETH ALAN OKIN
Appeal 2018-004 7 4 7
Application 15/198,23 5
Technology Center 2800
Before TERRY J. OWENS, JEFFREY T. SMITH, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
CASHION, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-5, which constitute all the claims pending in this application. We
have jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.
Appeal2018-004747
Application 15/198,235
The invention relates to an apparatus for a staggered start of flash
memories in a memory module. Spec. 1. Claim 1 illustrates the subject
matter on appeal and is reproduced below:
1. An apparatus, comprising:
a power supply;
at least one memory module coupled to the power supply
comprising a plurality of subsets of memory devices, wherein
each of the plurality of subsets of memory devices comprises a
plurality of memory devices; and
one or more processors configured to access one or more
of the plurality of subsets of memory devices based on a
voltage of the power supply reaching a predetermined level;
wherein the at least one memory module is configured to
be removable from the apparatus.
Appellant1 requests review of the Examiner's rejection of claims 1-5
under 35 U.S.C. § 102(a)(l) as anticipated by Brittain (US 7,587,559 B2,
issued September 8, 2009). App. Br. 4; Final Act. 2.
OPINION
The Prior Art Rejection
After review of the respective positions provided by Appellant and the
Examiner, we REVERSE the Examiner's prior art rejection of claims 1-5
under 35 U.S.C. § 102(a)(l) for the reasons presented by Appellant and add
the following.
1 Cypress Semiconductor Corporation is the Applicant/ Appellant and the
real party in interest. App. Br. 1.
2
Appeal2018-004747
Application 15/198,235
The apparatus of independent claim 1 2 requires "at least one memory
module coupled to the power supply comprising a plurality of subsets of
memory devices, wherein each of the plurality of subsets of memory devices
comprises a plurality of memory devices."
We refer to the Examiner's Final Action for a complete statement of
rejection of independent claim 1. Final Act. 2. Briefly, the Examiner relies
on Brittain's disclosed Figure 5 for an embodiment that anticipates claim 1
which, according to the Examiner, describes a plurality of subsets of
memory devices (503, 509), wherein each of the plurality of subsets of
memory devices comprises a plurality of memory devices (509). Id.
Appellant argues neither Fig. 5 nor any passage of Brittain describes
or suggests that the "one or more memory devices" of ref. 509 are being
accessed as subsets or are otherwise being grouped into subsets. App. Br. 4;
Reply Br. 2. Appellant contends that Brittain describes that multiple
independent cascade interconnected busses 506 that are logically aggregated
together to operate in unison to support a single independent access request
with data and error detection/correction being distributed/"striped" across
the parallel busses and associated devices. Reply Br. 2; Brittain col. 2, 11.
30-36. According to Appellant, the Examiner's assertion that ref. 509 in
Brittain' s Fig. 5 corresponds to both the plurality of subsets of memory
devices and the plurality of memory devices in each subset of Claim 1 is an
implicit acknowledgement that the elements indicated by ref. 509 are not in
the same arrangement as claimed in Claim 1. Id. Thus, Appellant asserts
that, if the same element (Brittain's ref. 509) corresponds to two separately
2 We limit discussion to independent claim 1.
3
Appeal2018-004747
Application 15/198,235
claimed elements, then Brittain does not describe the exact same
arrangement of elements that is claimed in Claim 1. Id.
We agree with Appellant that there is reversible error in the
Examiner's determination of anticipation. For the Examiner to carry the
burden of establishing a prima facie case of anticipation, the Examiner must
establish where each and every element of the claimed invention, arranged
as required by the claim, is found in a single prior art reference, either
expressly or under the principles of inherency. See generally In re
Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997).
The Examiner maintains that Brittain's memory devices 509 in
memory modules 503 can be accessed as subsets through subsets of cascade-
interconnected memory bus 506 and that each memory module 503 which
comprises a plurality of memory devices 509, would be considered as a
subset of the memory devices 509. Ans. 3; Brittain col. 2, 11. 27--45.
However, the Examiner does not adequately address Appellant's contention
that Brittain does not describe the one or more memory devices 509 as
subsets or grouped into subsets for purposes of operational access. Further,
the Examiner does not direct us to any disclosure in Brittain describing this
claimed feature or adequately explain why the claimed feature would be
inherent in the device and method of Brittain within the meaning of 3 5
U.S.C. § 102.
Accordingly, we reverse the Examiner's prior art rejection under
35 U.S.C. § 102(a)(l) of claims 1-5 for the reasons presented by Appellant
and given above.
4
Appeal2018-004747
Application 15/198,235
DECISION
The Examiner's prior art rejection of claims 1-5 under 35 U.S.C.
§ 102(a)(l) is reversed.
REVERSED
5