Ex Parte SPRY et al

Patent Trials and Appeals Board

Jun 27, 2019

14040316 - (D) (P.T.A.B. Jun. 27, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/040,316 09/27/2013
57035 7590 07/01/2019
KACVINSKY DAISAK BLUNI PLLC
Attention: Tricia Riddle
430 Davis Drive
Suite 150
Morrisville, NC 27560
FIRST NAMED INVENTOR
BRYANL. SPRY
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
P58083/1020P58083 1151
EXAMINER
HUYNH,KIMT
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
07/01/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
inteldocs _ docketing@cpaglobal.com
docketing@kdbfirm.com
intel@kdbfirm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRYAN L. SPRY, LILY P. LOOI, and
SHAUN M. CONRAD
Appeal2018-003901
Application 14/040,316 1
Technology Center 2100
Before HUNG H. BUI, IRVINE. BRANCH, and JOSEPH P. LENTIVECH,
Administrative Patent Judges.
BRANCH, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-25, which are all of the claims pending in the application. We
have jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.
1 According to Appellants, the real party in interest is Intel Corporation.
App. Br. 2.
Appeal2018-003901
Application 14/040,316
Technology
The application relates to "[i]mproved power control techniques for
integrated peripheral component interconnect express (PCie) controllers."
Spec. Abstract
Illustrative Claim
Claims 1-25 are pending; of these, claims 1, 10, and 20 are
independent. Claim 1 is reproduced below for reference:
1. A processor circuit, comprising:
an integrated peripheral component interconnect express
(PCie) controller; and
logic, at least a portion of which is in hardware, the logic
to detect a power reduction trigger, disable the integrated PCie
controller, and remove power from the integrated PCie
controller based on a power removal setting for the integrated
PCie controller.
References and Rejections2
Claims 1-5, 7-14, and 16-24 stand rejected under 35 U.S.C.
§ I02(a)(2) as anticipated by Teoh (US 2013/0086400 Al, published April
4, 2013). Final Act. 2-10.
Claims 6, 15, and 25 stand rejected under 35 U.S.C. § 103 as
unpatentable over Teoh and Jaber et al. (US 2014/0025947 Al, published
January 23, 2014). Final Act. 11-12.
2 Rather than repeat the Examiner's positions and Appellants' arguments in
their entirety, we refer to the above mentioned Appeal Brief filed November
11, 2017 ("App. Br."), as well as the following documents for their
respective details: the Final Rejection mailed January 9, 2017 ("Final Act."),
the Examiner's Answer mailed December 28, 2017 ("Ans."), and
Appellants' Reply Brief filed February 28, 2017 ("Reply Br.").
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Appeal2018-003901
Application 14/040,316
ANALYSIS
In support of the anticipation rejection of claims 1-5, 7-14, and 16-
24, the Examiner finds Teoh describes "logic ... to detect a power reduction
trigger, disable the integrated PCie controller, and remove power from the
integrated PCie controller based on a power removal setting," as recited in
claim 1. Final Act. 2-3 (citing Teoh ,r,r 20-25). The Examiner finds that
"when a PCie controller triggers power gating during ASPM L 1, the PCie
controller is required to retain power on the logics that stored the link's
context information." Id. (citing Teoh ,r 20). The Examiner further finds
that "when a PCie controller exits ASPM L 1 to reenter the fully functional
LO state, most of the context of the PCie Link is not exchanged between the
Upstream component and Downstream component, wherein not exchanged
between the components implies removed power from the controller." Id.
( citing Teoh ,r,r 20-25). The Examiner concludes that "it is[, therefore,]
expected that between a PCie controller triggers power gating during ASPM
L 1, the PCle controller is required to retain power on the logics that stored
the link's context information in order not to lose the context information."
Id. The Examiner further finds that
The Ll and LO state is showing in the table of PCI specification,
summary of PCI express link management states. This is
equivalent as Applicant recited removed power from the
integrated PCie controller based on a power removing setting.
Thus, the prior art teaches the invention as claimed and the
claims do not distinguish over the prior art as applied.
Ans. 11-12.
We are persuaded of error. Specifically, we are not persuaded that
"the PCle controller [being] required to retain power on the logics that
stored the link's context information in order not to lose the context
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Appeal2018-003901
Application 14/040,316
information" is equivalent to the claimed "remove power from the integrated
PCie controller based on a power removal setting." Final Act. 2-3
(emphasis added); Ans. 11-12; Claim 1. See App. Br. 11-13. The
Examiner does not adequately explain this equivalency. Further, we agree
with Appellants that "Teoh cites to the PCie base specification and states
that the power must continue to be supplied to portions of the PCie
controller during [the] LI state." App. Br. 12; see also Teoh ,r 20.
Accordingly, we do not sustain the Examiner's rejection of claim 1
and of claims 2-9, which depend therefore. For similar reasons, we also do
not sustain the rejections of independent claims 10 and 20, and those that
depend therefore.
DECISION
For the reasons above, we reverse the Examiner's decision rejecting
claims 1-2 5.
REVERSED
4