Ex Parte Rogers et al

Patent Trials and Appeals Board

Mar 23, 2016

12749254 - (D) (P.T.A.B. Mar. 23, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121749,254 03/29/2010
40418 7590
HEIMLICH LAW
5952 DIAL WAY
SAN JOSE, CA 95129
03/25/2016
FIRST NAMED INVENTOR
Norman L. Rogers
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
Digi-P014Cl 6719
EXAMINER
SIEK, VUTHE
ART UNIT PAPER NUMBER
2851
NOTIFICATION DATE DELIVERY MODE
03/25/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
alanheimlich@heimlichlaw.com
sroberts@peloquinlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NORMAN L. ROGERS, JOHN W. HOFFMAN, JUN FENG, and
CHARLES KRAUTER
Appeal2014-005038
Application 12/749,254
Technology Center 2800
Before TERRY J. OWENS, N. WHITNEY WILSON, and
JULIA HEANEY, Administrative Patent Judges.
HEANEY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek our review pursuant to 35 U.S.C. § 134(a) of a
decision of the Examiner to reject claims 3-22 of Application 12/749,254.
We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part.
BACKGROUND
The subject matter on appeal relates to a printed circuit board having
one or more electrically conductive layers separated by one or more
1 Appellants identify the real party in interest as Digi International, Inc.
App. Br. 4.
Appeal2014-005038
Application 12/749,254
insulating layers, and a stiffener having a plurality of plated through vias.
App. Br. 6.
Claim 3 is illustrative and reproduced from the Claims Appendix of
the Appeal Brief as follows:
3. A printed circuit board comprising:
one or more electrically conductive layers separated by
one or more insulating layers; and
a stiffener having a plurality of plated through vias, said
stiffener non-electrically connectedly attached to said one or
more electrically conductive layers separated by one or more
insulating layers.
THE REJECTIONS
I. Claims 3-10, 12-17, and 20-22 stand rejected under 35 U.S.C.
§ 102(b) as anticipated by Walk. 2
II. Claim 11 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Walk and Jandzio. 3
III. Claims 18 and 19 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Walk and Cheng. 4
2 Walk, US 2005/0285255 Al, published Dec. 29, 2005 (hereinafter
"Walk").
3 Jandzio et al., US 2008/0106475 Al, published May 8, 2008 (hereinafter
"Jandzio").
4 Cheng, US 2001/0000156 Al, published Apr. 5, 2001 (hereinafter
"Cheng").
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Application 12/749,254
§ 102(b) Rejections
Claim 3
DISCUSSION
The Examiner finds that Figures IA and 4 of Walk disclose a stiffener
125 coupled to conductive layer 110 and having a plurality of plated through
holes 140 extending across stiffener. Ans. 7; Walk i-f 27. Appellants argue
that Walk does not disclose "plated through vias" as recited in claim 3. App.
Br. 20. Specifically, Appellants argue that plated through holes 140 of Fig.
4 are not a "through via" structure because they do not go "from the bottom
of 125 to the top of 125." Reply Br. 3. We have reviewed each of
Appellants' arguments, and find that a preponderance of the evidence, as
described, for example, at page 7 of the Answer)supports the Examiner's
finding that Walk's through holes 140 extend across stiffener 125 as shown
in Fig. 4 and described in Walk i-f 27. 5 Accordingly, we affirm the rejection
of claim 3.
Claim 4
Claim 4 depends from claim 3 and additionally recites that "one or
more electrically conductive layers is a topmost layer on said printed circuit
board." Appellants argue that Walk does not anticipate claim 4 because 110
of Fig. 1 A is not a "topmost layer" and substrate 100 is not conductive.
5 Appellants further argue that the Examiner has failed to provide an
Affidavit of Personal Knowledge concerning the finding that Walk i-f 27 is
apparently in error by identifying 140 of Figure 4 as "a plurality of pads"
and 135 as "a plurality of plated through holes." Reply Br. 3. We determine
that the Examiner is not relying on personal knowledge as a basis for this
rejection, or any other rejection at issue in this appeal, and do not find
Appellants' argument persuasive.
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Application I2/749,254
App. Br. 20. Appellants further argue that a "topmost layer is understood by
one of skill in the art to refer to the layer on top of the printed circuit board."
Reply Br. 5.
We do not find Appellants' argument persuasive. As shown in
Walk's Fig. 5 and described in if 28, substrate IOO is situated on top of
printed circuit board 560. Further, as shown in Walk's Fig. IA and
described in if I9, substrate IOO has a plurality of conductive layers I IO. As
to Appellants' claim interpretation argument seeking to limit the scope of
"topmost layer" to "the layer on top of the printed circuit board," Appellants
have not pointed us to anything in the Specification consistent with that
interpretation, nor have they submitted any evidence in support of the
understanding of a person of ordinary skill in the art. We have reviewed the
Specification in order to determine the broadest reasonable interpretation of
"topmost layer" and determined that it does not provide a definition for
"topmost layer." See In re ICON Health & Fitness, Inc., 496 F.3d I374,
1379 (Fed. Cir. 2007). Therefore, we apply a broad interpretation and
decline to adopt the Appellants' proposed finding as the understanding of a
person of ordinary skill in the art, for lack of support. Accordingly, we
affirm the rejection of claim 4.
Claim 5
Claim 5 depends from claim 4 and additionally recites that "said
topmost layer has one or more components mounted on it." Appellants
argue that Walk's Fig. IA does not show components mounted on a topmost
layer (App. Br. 2 I), and further that contacts 450 shown in Figs. 4 and 5 are
not formed on a topmost layer because the top layer of substrate I 00 is not a
"topmost layer," for the reasons set forth above (i.e., "topmost layer" is "the
layer on top of the printed circuit board"). Appellants' arguments are not
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Application 12/749,254
persuasive, as Fig. 5 (described in Walk i-f 28) clearly shows die 555
mounted on top of the substrate. Further, as discussed with respect to claim
4 supra we declined to adopt Appellants' proposed interpretation of
"topmost layer." Accordingly, we affirm the rejection of claim 4. 6
Claims 6, 7, 9, 10, 15, and 16
Each of these claims depends, directly or indirectly, from claim 3, 4,
or 5 and recites an additional limitation of "circuit routing on said topmost
layer." Appellants argue that Walk does not disclose circuit routing. App.
Br. 21-23. We agree with Appellants and find reversible error in the
rejection of claims 6, 7, 9, 10, 15, and 16 because the Examiner did not
identify any circuit routing on the top layer of substrate 100.
Claim 8
Claim 8 depends from claim 4 and additionally recites that "said
topmost layer has one or more gull wing surface mount components
mounted on it." Appellants argue that die 555 shown in Walk's Fig. 5 and
described in i128 is not a gull wing surface mount component. Reply Br. l 0.
Appellants' argument has insufficient evidentiary support and therefore does
not persuade us of reversible error. The Specification identifies component
1102 of Figure 11 as "a gull wing surface mount component." Spec. i-f 53.
Having reviewed the Specification, and all record evidence, we do not find
that Appellants have shown differences between Walk's component 555 and
the gull wing surface mount component that is recited in Appellants' claims.
Accordingly, we affirm the rejection of claim 8.
6 Appellants' argument that Walk's substrate is not "non-electrically
connectedly attached" is waived because it was not raised prior to the Reply
Brief. Reply Br. 7. 37 C.F.R. §41.41.
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Appeal2014-005038
Application I2/749,254
Claims 12 and 13
Claims I2 and I3 depend from claim 3 and recite the additional
limitation "one or more of said one or more electrically conductive layers is
a power plane layer." Appellants argue that Walk's Figs. IA and 5 do not
show a power plane layer, and that Walk nowhere mentions a power plane
layer. Reply Br. I6-I 7. Although the Examiner relies on inherency, i.e.,
"[ c ]omponents mounted on a circuit board need power; so it must include
power plane layer" (Ans. I2), this does not establish anticipation because the
presence of a power connection does not necessarily require that an
electrically conductive laver of Walk' s substrate I 00 is a power plane layer,
or a ground plan layer. The Examiner has not satisfied the initial burden of
providing a basis in fact or technical reasoning to support the finding of a
power plane layer or ground plane layer. In re King, 80I F.2d I324, I327
(Fed. Cir. I986). Accordingly, we reverse the rejection of claims I2 and I3.
Claim 14
Claim 14 depends from claim 3 and recites the additional limitation
"one or more electrically conductive layers is four or more electrically
conductive layers." Appellants argue that Walk's Fig. IA only shows three
electrically conductive layers, because "only 3 lines emanat[e] from I IO."
App. Br. 24; Reply Br. I9. Having reviewed all the evidence, we are not
persuaded that Appellants have shown that Walk discloses only three
electrically conductive layers. As the Examiner finds, Walk's Fig. IA
shows six conductive layers I IO. Ans. I2. Accordingly, we affirm the
rejection of claim I4.
Claim 17
Claim I 7 depends from claim 4 and recites the additional limitation
"said stiffener non-electrically connectedly attached is to other than said
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Application I2/749,254
topmost layer." Appellants argue that Walk's Fig. IA does not disclose the
topmost layer being a conductive layer because I I 0 is not a topmost layer.
App. Br. 25. We declined to adopt Appellants' proposed interpretation of
"topmost layer" in our discussion of claim 4, supra. Further, Walk i-fi-f I 9-20
describe that stiffener layer I25 is any suitable non-conductive material, and
Fig. IA shows that stiffener is not attached to a topmost electrically
conductive layer; therefore, Walk' s stiffener is encompassed by claim I 7.
Accordingly, we affirm the rejection.
Claim 20
Appellants argue that Walk's Fig. IA does not show an insulating
layer between I25 and I IO lowermost layer, and thus Walk does not
anticipate claim 20. App. Br. 26. As the Examiner correctly notes, the
feature that Appellants argue is not a limitation of claim 20. Ans. I4.
Further, claim 20 is the same as claim 3, except that claim 20 does not
require "a plurality of plated through vias." Having affirmed the rejection of
claim 3, we also affirm the rejection of claim 20.
Claims 21 and 22
Claims 2 I and 22 depend from claim 20 and additionally recite that
the stiffener is copper coated steel or aluminum coated steel, respectively.
The Examiner has not shown that Walk' s stiffener is copper coated steel or
aluminum coated steel; the Examiner's findings as to how Walk corresponds
to these claim limitations relate to through holes I 40, not a stiffener. Ans.
I 5. Accordingly, we find reversible error in the rejection of claims 2 I and
22.
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Appeal2014-005038
Application 12/749,254
§ 103(a) Rejections
Claim 11
Claim 11 depends from claim 10 and therefore includes the limitation
of "circuit routing." As we determined supra, Walk does not disclose circuit
routing. In the §103(a) rejection, the Examiner does not rely on Walk or
Jandzio for a suggestion of circuit routing. Accordingly, we reverse the
rejection of claim 11.
Claims 18 and 19
Claims 18 and 19 depend from claim 3 and recite, respectively, that
"said vias are approximately 2 mm in diameter" and "said vias are 20 per
square inch." Appellants do not present a substantively distinct argument as
to the rejection of claim 18 as unpatentable over Walk in view of Cheng.
App. Br. 26. As to claim 19, Appellants' only substantively distinct
argument is that the Examiner has not provided an Affidavit of Personal
Knowledge as to the via density disclosed in Cheng. Reply Br. 25. As
discussed above (n. 5), we determine that the Examiner has not relied on
personal knowledge for any of the rejections at issue in this appeal. Further,
the Examiner's calculation of the number of vias per square inch is sufficient
to support the rejection. Ans. 14. Accordingly, we affirm the rejection of
claims 18 and 19.
SUMMARY
For the foregoing reasons, we affirm the rejection of claims 3-5, 8,
14, 17-20 and reverse the rejection of claims 6, 7, 9-13, 15, 16, 21, and 22.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
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Appeal2014-005038
Application 12/749,254
AFFIRMED-IN-PART
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