12860156 (P.T.A.B. Dec. 8, 2015)

Ex Parte Refai-Ahmed et al

Patent Trial and Appeal BoardDec 8, 2015

12860156 (P.T.A.B. Dec. 8, 2015)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/860, 156 08/20/2010 16501 7590 Timothy M, Honeycutt Attorney at Law 37713 Parkway Oaks Ln. Magnolia, TX 77355 12/10/2015 FIRST NAMED INVENTOR Gama! Refai-Ahmed UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. AMDI:230\HON 9445 EXAMINER SALERNO, SARAH KATE ART UNIT PAPER NUMBER 2814 NOTIFICATION DATE DELIVERY MODE 12/10/2015 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): timhoney@sprynet.com timhoneycutt@earthlink.net elizabethahoneycutt@earthlink.net PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Exparte GAMAL REFAI-AHMED, MICHAEL Z. SU, BRYAN BLACK, MAXAT TOUZELBAEV, and YIZHANG YANG Appeal2014-000700 Application 12/860,156 Technology Center 2800 Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and JAMES C. HOUSEL, Administrative Patent Judges. TIMM, Administrative Patent Judge. DECISION ON APPEAL 1 Appellants2 appeal the Examiner's decision to reject claims 1, 2, 4, 5, 11, 12, 14-16, 25, and 27 under 35 U.S.C. Â§ 102(b) as anticipated by 1 In our opinion below, we reference the Final Office Action filed October 10, 2012 (Final), and the Appeal Brief filed May 8, 2013 (Appeal Br.). 2 Appellants identify the real parties of interest as Advanced Micro Devices, Inc., and ATI Technologies, ULC. Appeal Br. 6. Appeal2014-000700 Application 12/860,156 - - '1 - - - - . - - - - - - -Â· - - . - - ' ' - - - - - Gealer,-' claims 3 and 13 under 35 U.S.C. Â§ 103(a) as obvious over Gealer in view ofCablao,4 and claims 28 and 29 under 35 U.S.C. Â§ 103(a) as obvious over Gealer in view of Mallik. 5 We have jurisdiction under 35 U.S.C. Â§Â§ 6(b) and 134(a). We REVERSE. The claims are directed to a method of assembling a semiconductor chip device (see, e.g., claims 1 and 28), and an apparatus with two semiconductor chips and an interposer (see, e.g., claim 11 ). Appellants' Figure 1 depicts an embodiment of the device and is reproduced below: Figure 1 depicts a cross-sectional side view of a semiconductor device 10 including semiconductor chip 15 within the aperture 55 of an interposer 50 seated on a semiconductor chip 20 to create stacked semiconductor chips on a circuit board 25 surrounded by a heat spreader 30 To further illustrate the claimed invention, we reproduce claim 1 with reference numerals from Figure 1. We also highlight a particular claim limitation at issue in the appeal. 3 Gealer, US 2005/0121757 Al, pub. Jun. 9, 2005. 4 Cablao et al., US 7,518,226, patented Apr. 14, 2009. 5 Mallik et al., US 2005/0127489 Al, pub. Jun. 16, 2005. 2 Appeal2014-000700 Application 12/860,156 1. A method of assembling a semiconductor chip device [ 1 OJ, comprising: placing an interposer [50] on a first semiconductor chip [20], the interposer [50] including a lower surface seated on the first semiconductor chip [20] and an upper surface adapted to thermally contact a heat spreader [30], the upper surface including a first aperture [55] defining a seating surface facing away from the lower surface; and placing a second semiconductor chip [15] in the first aperture [55]. Claims Appendix at Appeal Br. 27 (emphasis added). OPINION All of the claims require an interposer on a first semiconductor chip, the interposer including a lower surface seated on the first semiconductor chip, the first semiconductor shown as semiconductor chip 20 in Figure 1 above. See claims 1, 11, and 28. The Examiner finds that element 20 of Gealer is a semiconductor chip in the location of the first semiconductor chip of the claims. Final 2. The ordinary artisan would understand Gealer's element 20 to be a substrate of an IC package, and not a semiconductor chip. Although Gealer calls element 20 an "IC package," Gealer uses the term "IC package" to describe the structure upon which an IC die sits. Gealer i-f 2. Gealer seats an IC die 10 on "IC package 20." Gealer i-f 16. Gealer then refers to element 20 as a substrate. Gealer i-f 1 7. According to Gealer, substrate 20 may comprise an IC package, a circuit board, or other substrate. Id. Gealer then lists the substrate as formed from any ceramic, organic, and/or other suitable material. Id. Then Gealer refers to the structure as an "IC package 3 Appeal2014-000700 Application 12/860,156 substrate," exemplifies forming it from an organic laminated glass-weave polymer, and describes a step of cutting it during a singulating step. Gealer i-fi-125 and 34. When one reads Gealer as a whole, it becomes clear that element 20 is an IC package substrate intended to support IC die 10. There is no convincing evidence that one of ordinary skill in the art would have understood "IC package" to refer to either a semiconductor chip or an IC package containing a semiconductor chip other than IC die 10. The Examiner has failed to establish that Gealer describes within the meaning of 35 U.S.C. Â§ 102 "an interposer on a first semiconductor chip, the interposer including a lower surface seated on the first semiconductor chip" as required by Appellants' claims. The Examiner's application of Cablao and Mallik does not cure the deficiency discussed above. Thus, we do not sustain any of the rejections. DECISION The Examiner's decision is reversed. REVERSED mat 4